JPS62269237A - Data processor - Google Patents

Abstract

PURPOSE:To flexibly and efficiently control a peripheral device by providing a means for outputting a part of a field of an instruction which is read by a processor, to the outside at a processing stage determined in advance of said instruction, in the processor. CONSTITUTION:An output field 4 of an instruction is transferred by output registers 11-13 corresponding to an instruction register 5, a micro-instruction register 7, and an execution register 9, respectively. The contents of the output register 12, 13 are outputted to instructing terminals 14, 15, respectively. That is to say, the instructing terminals 14, 15 are terminals for outputting the corresponding value of an output field of an instruction being in a micro-instruction decoding cycle and an executing cycle, respectively. In such a way, the providing the output field 4 and the instructing terminals 14, 15, the number of instructions of a processor is increased substantially, and also, a complicated and a powerful peripheral device can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a processor having an output line for external device control or coprocessor control.

BACKGROUND OF THE INVENTION When constructing a desired system using a data processing device (hereinafter referred to as a processor) such as a microcomputer, it is normal to have a processor assist the operation of the processor or perform some of the operations that the processor should perform. Use some device to do it for you. An example of such a device is the Direct Me
Examples include a near 7 controller, an input/output controller, and an additional processor for numerical calculations. These are generally called processor peripheral devices, or simply peripheral devices. There are two main ways to link these peripheral devices with the processor.

The first method is for processors and peripheral devices to exchange information necessary for cooperative operation via general-purpose signal lines such as system buses, bus control lines, interrupt control lines, and the like.

Data exchange using this method is performed, for example, in the following procedure when the processor is a mask of the system bus. That is, ■ The processor reads instructions from peripheral devices placed in memory into internal registers.

■ 1 The processor writes the instruction read in ■ to the instruction register of the peripheral device, which is located in the processor's address space like memory 0 ■ The peripheral device decodes the instruction set in the instruction register and sends it to the processor. Issue a request to use the system bus.

■ Obtain permission to use the system bus from the processor and access memory.

A second method for enabling cooperative operation between a processor and a peripheral device is for the two to be tightly coupled via dedicated signal lines. This method is implemented in a relatively high-level processor system, and in particular, the peripheral device in this method is a coprocessor (Go-Pro: essor).
)It is called. Processors that perform such operations generally have two types of dedicated signal lines. One is a group of signal lines that conveys the internal state of the processor or coprocessor to the coprocessor or processor, respectively, and the other is a group of signal lines that prompt the processor or coprocessor to output or input information such as instructions, data, addresses, etc. to the processor or coprocessor, respectively. This is a group of signal lines. Data exchange using this method is performed, for example, in the following procedure. That is, ① The coprocessor monitors the internal state of the processor and takes in instructions in synchronization with the processor.

If the imported instruction is an instruction that the processor should execute, the coprocessor reads it.0 ■ If the imported instruction is an instruction that the coprocessor should execute, the processor continues to instruct the coprocessor. A signal that prompts the capture of data to be read is transmitted via a dedicated signal line. Alternatively, the coprocessor takes over the bus cycle of the processor and actively fetches data.

■ The coprocessor decodes the instruction and prepares it for execution.

■ The coprocessor continues to monitor the internal state of the processor and uses free cycles on the system bus to access memory.

In the conventional method as explained above, the following points are gained and lost. That is, in the first method, the processor does not require any special control means;
Similar to writing to memory, the processor must address and write to the peripheral device's instruction register. Still, regarding the use of the system bus, peripheral devices require exclusive use for a relatively long time (several to ten times the bus cycle time).

In the second method, the coprocessor can know the internal state of the processor, such as whether or not the processor is executing an instruction that uses the system bus, thereby greatly improving the efficiency of system bus use. however,
The processor needs to be provided with means for informing the outside of its internal state and means for controlling the coprocessor.

Problems to be Solved by the Invention In such a conventional configuration, it is necessary to add complex additional functions to the processor and peripheral devices in order to improve system performance, particularly the transfer efficiency of the system bus. This not only increases the complexity of the system configuration, but also means that the processor and processor must be specialized.The present invention was made in this regard.
This makes it possible to control peripheral devices more flexibly and efficiently than before without significantly changing the versatility of the processor.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides means within the processor for outputting part of the field of an instruction read by the processor to the outside at a predetermined processing stage of the instruction. It is something.

Effect of the Invention With the above-described configuration, the processor can supply control signals to peripheral devices in synchronization with instructions to be executed. Additionally, system designers can establish control of such peripheral devices independent of processor instructions.

Embodiment FIG. 1 is a block diagram showing a first embodiment of the processor of the present invention. In FIG. 1, 1 is an external data bus;
2 is an instruction queue; instructions to be executed by the processor are temporarily stored in the instruction queue 2 via a bus 1; Instructions are transferred from an instruction queue 2 to an instruction register 5 in accordance with the instruction execution cycle of the processor, and are interpreted by an instruction decoder 6. This phase is called an instruction decode cycle (hereinafter abbreviated as In cycle). This result is stored in the microinstruction register 7 and sent to the microinstruction decoder 8.
Microinstructions are interpreted in

This phase is called the microinstruction decode cycle (hereinafter referred to as MD psyle). This result is execution register 9
The instructions are stored in the execution unit 10 and executed. This phase is called an execution cycle (hereinafter referred to as EX cycle). Normally, these cycles are executed sequentially by a method called pipelining as shown in FIG. On the other hand, the output field 4 of the instruction is transferred by output registers 11, 12, and 13 corresponding to the instruction register 5, microinstruction register 7, and execution register 9, respectively. The contents of output registers 12.13 are output to respective instruction terminals 14.16.

That is, the instruction terminals 14 and 15 are respectively MD cycle and EX
This is a terminal that outputs the corresponding value of the output field of the instruction in the cycle. The above-mentioned operation will be specifically explained using FIG. 2. In a processor, four consecutive instructions A
, B, C, and D are executed one after another from To, and the respective output fields are (0°1), (0,0), (1,○), (1
, o). Here, x+7 in (x, y) is the output field corresponding to the indicator terminal 14.15. The instruction terminal 14 outputs a signal in response to the MD psiles of instructions C and D, and the instruction terminal 15 outputs a signal in response to the EX cycle of instruction A. An example of how a processor having such a function is used will be explained with reference to FIG. In the figure,
20, 21, and 22 are a processor, a DMA controller, and a memory, respectively, and are connected to a common system bus 23. The instruction terminals 14 and 15 of the processor 20 are DM respectively.
It is connected to the chip select terminal 24 and bus use permission terminal 25 of the A controller 21. In such a configuration, when the processor 20 wants to transfer an instruction from the DMA controller 21, the processor accesses the address storing the instruction in the memory 22 and at the same time transfers the instruction terminal 1.
5 to a high logic level; or, if the instruction is generated within the processor 20, a dummy write cycle may be executed with the instruction terminal 15 set to a high logic level. Of the commands,
By writing "1" in the output field of the relevant command, the command can be transferred to the DMA controller. In FIG. 3, the instruction terminal 14 and the bus permission terminal 25 show another example of use. It is assumed that II 11+ is written in the output field corresponding to the instruction terminal 14 if the instruction does not use the bus 23, and is output to the MD psile. That is, the instruction terminal 14 indicates that the next cycle is a bus idle cycle.

The DMA controller 21 monitors this signal and transfers it to the bus 2.
3 can be used in one cycle.

In this way output field 4 and indicator terminal 14.15
This substantially increases the number of instructions for the processor and allows control of complex and powerful peripheral devices.

Next, a second embodiment of the present invention will be described using FIG.

The difference between this embodiment and the first embodiment is that in the first embodiment, the output field exists in the instruction read by the processor, whereas in the second embodiment, the output field exists in the instruction decoder 6. It exists in the microinstruction ROM 35. That is, 36 indicates a microinstruction field in the ROM 35, and 37 indicates an output field. Therefore, the signals output to the instruction terminals 14 and 15 correspond to the execution cycle of the microinstruction. In this embodiment, a finer control output can be outputted to the outside than in the configuration shown in the first embodiment.

Effects of the Invention As described above, according to the present invention, a flexible and powerful control signal can be output in synchronization with the execution cycle of the processor without significantly impairing the versatility of the processor. In the example, the output field was used to control peripheral devices, but it can also be used for interrupt signals to external devices, recognition of specific routines, labels, etc., and is useful for checking and debugging the operation of programs, processors, and peripheral devices. is also a useful and powerful tool.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a processor in the first embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining its operation,
FIG. 3 is a block diagram showing an example of the system configuration, and FIG. 4 is a block diagram of a processor in a second embodiment of the present invention. 3...°°・Instruction field, 4, 37...
Output field, 36...Micro instruction field, 11゜12.13...Output register, 1
4.15...Indication terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3

Claims (1)

[Claims] A processor that is formed on the same semiconductor substrate and processes a series of processes from reading an instruction to executing it in a pipeline by dividing it into one phase or multiple phases, and is a part of the field of the read instruction. Or a data processor comprising means for outputting a part of the field of an instruction to be executed to the outside in synchronization with a predetermined phase of the processing stage.