JP2902861B2 - Buffer device with trace function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer with a trace function which is applied to study RAS (reliability: availability, availability: serviceability: serviceability) for a personal computer or control computer using a microprocessor. Related to the device.

[0002]

2. Description of the Related Art A microprocessor has 8 bits, 16 bits.
There are 32 bits and 32 bits. For these microprocessors, program debugging and bug investigation are performed.

[0003] In this investigation, the result of execution of an instruction issued from the CPU and the result of access to the memory, such as read / write, is accumulated in the trace memory in real time, and the result of the CPU access accumulated in the trace memory after the trigger is established. Is performed by reading out.

As a development support tool for such a debug, for example, an in-circuit emulator (in cir
cuit emulator: ICE) is used. This IC
E operates the CPU on the ICE side in the user system, and sequentially tracks and monitors the execution contents of the CPU with the ICE software. In the ICE, the execution of the CPU is stopped under certain conditions, the contents of the memory are changed, and the execution of I / O is controlled by intervening the software of the ICE. It has the function of grasping whether there is, and whether the function is sufficiently satisfied.

When this ICE is actually used, as shown in FIG. 2, the adapter 2 of the ICE main body 1 is connected to the CPU socket 4 of the processing device 3 having the CPU mounted thereon, and
An analyzer 5 such as a probe box, a memory, or a personal computer is connected to the main body 1. This ICE is, for example, Intel 386D
X, 486DX and Motorola 68000 series.

These ICEs provide an abundant function, language processing such as a compiler and an assembler, and an integrated development environment such as a man-machine interface, and are very useful for software developers.

However, bugs that occur after the development of the user system, such as insufficient reading margin of hardware, errors that occur rarely due to processing timing, and discrepancies in stack push and pop operations, are actually caused by the operation of the user system. Often happens during. For this reason,
It is difficult to analyze such a bug with the ICE attached. In order to analyze a bug with respect to multiple CPUs, DMAs, etc., an ICE must be connected to each CPU. Moreover, ICE is expensive.

[0008]

As described above, it is difficult to analyze a bug that occurs after the development of the user system with the ICE attached, and it is difficult to analyze multiple CPUs for each CPU. ICE must be connected.

Therefore, the present invention makes it possible to analyze a bug that occurs after the development of a user system by using a normally existing bus buffer without adding new hardware, and also for a multi-CPU or the like. An object of the present invention is to provide a buffer device with a trace function that can be applied.

[0010]

SUMMARY OF THE INVENTION The present invention relates to a buffer device connected between a CPU and a multi-bus or the like in a computer.

A trace memory and at least the CPU
The access issued from the server is saved as a history in the trace memory, and the occurrence of a predetermined condition set in advance is detected.
And a trace control means for controlling the start and stop of saving of the history.

[0012]

With such a means, it is connected between a CPU of a computer and a multi-bus or the like.
The access issued from the CPU is saved as a history in the trace memory. In this case, saving of the access of the CPU to the trace memory is performed under a predetermined condition set in advance.
On the basis of this, start and stop control is performed by the trace control means.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a buffer device 10 with a trace function. The buffer device 10 functions as a bus buffer, and has a bus arbitration logic and a bus buffer. That is, for example, Intel Corporation 38
The 6DX and 486DX classes often use a multi-bus or common memory, which requires arbitration logic and a bus buffer.

The buffer device 10 utilizes such a bus buffer, and is constituted by an ASIC (Application Specific Integrated Circuit), for example, a gate array. And this buffer device 10 is a C
It is connected between the PU and the multibus, I / O bus, system bus, and shared memory bus. Note that in FIG.
It is connected between U and the multibus.

The buffer device 10 includes an address bus 11 having a serial port, a status bus 12
And a data bus 13 are provided.
Among them, the address bus 11 is connected to the address bus 14 from the CPU, the status bus 12 is connected to the status bus 15 from the CPU, and the data bus 13 is connected to the data bus 16 from the CPU.

A one-way buffer 17 is connected to the address bus 11, a bidirectional buffer 18 is connected to the data bus 13, and connected to an address bus 19 and a data bus 20 on the multi-bus side, respectively. The trace logic 21 and the register 2 are connected to these buses 11, 12, and 13.
2 and the trace memory 23 are connected. The trace logic 21 has the following functions.

That is, an interface function for setting a start / stop trigger condition for saving the history in the trace memory 23 and a condition for reading the content of the history in the register 22.

In accordance with the conditions set in the register 22, accesses issued from the CPU, for example, instruction execution cycles, code fetches, memory read / writes, etc., are saved in the trace memory 23 as histories and matched with the trigger conditions. It has a trace control function that sometimes stops saving the history.

With this configuration, when a start / stop trigger condition for saving the access history and a condition for reading the history content are issued from the CPU, these conditions are set in the register 22 by the trace logic 21.

In this state, when accesses from the CPU, for example, code fetch, memory, I / O read / write, etc. are issued, these accesses are input to the trace logic 21 through the status bus 15. The trace logic 21 performs these accesses sequentially in the trace memory 2.
3 and at this time, the addresses and data on the address bus 14 and the data bus 16 are monitored and stored in the trace memory 23. The address and the data are transmitted to the multi-bus side through the one-way buffer 17 and the two-way buffer 18, respectively.

When the access from the CPU is stored in the trace memory 23, for example, when the execution state of the program matches the stop trigger condition set in the register 22, the trace logic 21 stores the access history. Stop tracing.

When the CPU issues a command to read the history contents, the command is input to the trace memory 23 through the trace logic 21 and the CPU enters the state in this state.
Reads history contents from the trace logic 21.

As described above, in the above-described embodiment, the connection is made between the CPU and the multi-bus in the computer.
The access issued from the CPU is saved in the trace memory 23 as a history, and the save in the trace memory 23 is controlled to start and stop by the trace logic 21. Therefore, the history of the access saved in the trace memory 23 is read. This enables analysis of a bug that occurs after the development of the user system. In addition, the analysis of this bug can be performed using the existing bus buffer without adding new hardware. Further, by using a large-scale ASIC, the present invention can be applied to a multi-CPU or the like. And multi CP
Each CPU of U can be provided with an access history tracing function.
The analysis is facilitated by obtaining sample data. Further, the trigger condition set in the register 22 can be changed, and the history of the trace memory 23 can be read arbitrarily by the CPU. Note that the present invention is not limited to the above-described embodiment, and may be modified without departing from the scope of the invention.

[0025]

As described above in detail, according to the present invention, analysis of a bug occurring after the development of a user system can be performed without adding new hardware by using a normally existing bus buffer. In addition, a buffer device with a trace function that can be applied to a multi-CPU or the like can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a buffer device with a trace function according to the present invention.

FIG. 2 is a configuration diagram of a conventional device.

[Explanation of symbols]

10: buffer device with trace function, 17: one-way buffer, 18: bidirectional buffer, 21: trace logic, 22: register, 23: trace memory.

Claims (1)

(57) [Claims] 1. A buffer device connected between a CPU and a multi-bus or the like in a computer, wherein a trace memory and at least an access issued from the CPU are saved as a history in the trace memory, and are set in advance. A buffer device with a trace function, comprising: trace control means for detecting the occurrence of a predetermined condition and controlling start and stop of the history saving.