JP2001249823A - Microcomputer development assisting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer development assisting device at low cost, with high debugging efficiency, with a real time trace function and capable of checking whether or not a program exactly runs. SOLUTION: A trace memory 18 capable of tracing all bus cycles and a FIFO buffer memory 19 for external trace memory are embedded in an emulation chip 1 with a processor 11, data to be stored in an external trace memory 7 is stored in the buffer memory 19 due to an asynchronously generated event. The data written as trace data is stored in the external trace memory 7 at intervals of the asynchronously generated events.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for supporting development of a microprocessor having a debugging function such as an in-circuit emulator (ICE).

[0002]

2. Description of the Related Art In a microcomputer development support apparatus, in order to verify the execution result of a program in a microcomputer, the apparatus has a function equivalent to that of the microcomputer and has a function of accessing an internal RAM, I / O and the like. An emulator that can check the status from outside is used.

This emulator operates on a system to be developed by a user, accesses an operation / peripheral circuit, and saves the execution result in a trace memory to support user debugging. Things.

In a microcomputer development support device using an ICE (In-Circuit Emulator) having a real-time trace function for storing the state of the bus in a memory in real time, the bus speed increases with the speed of the MPU. Having a trace memory on a board external to a semiconductor device provided with an MPU is not enough, and the trace memory may be built in the semiconductor device.

However, in order to incorporate the trace memory, the trace memory capacity is limited due to manufacturing problems and cost problems, and the trace memory capacity required for the debug system cannot be incorporated. There is a problem of inefficiency.

Japanese Unexamined Patent Publication No. Hei 8-161191 discloses that, even when a high-speed MPU is the target, a state is embedded in an embedded chip in the target device so that sufficient debugging can be performed. Proposed in-circuit emulator with a debug unit that has a trace function for analysis, a non-break debug function that performs real-time on-chip debug resources in all states without stopping the target MPU, and an off-chip monitor memory access interface function Have been.

With the above configuration, a certain speed-up is possible, but since the trace memory is off-chip,
As described in the above-mentioned publication, there is a problem that the speed can be increased only up to about 100 MHz.

Japanese Patent Application Laid-Open No. 8-63368 discloses that
An emulator has been proposed which enables high-speed response by realizing high-speed microcomputer real-time emulation and real-time tracing by using a signal on the emulator side that is not required for the operation of the user system. That is, this publication proposes an emulator and a microcomputer that can emulate by a microcomputer on a user system and create trace data by an external simulation means to enable high-speed operation.

In the above method, since the trace data is generated by the simulation means,
When a microprocessor executes a program, it is possible to find a problem in the program, but there is a problem that it is not possible to accurately diagnose a hardware failure of an actual semiconductor device.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a real-time tracing function with low cost and high debugging efficiency.
An object of the present invention is to provide a microcomputer development support device capable of checking whether a program is running correctly.

[0011]

According to the present invention, an external trace memory buffer memory is incorporated in a semiconductor device having a processor, and data to be stored in the external trace memory is stored in the buffer using an asynchronously generated event. The data stored in the memory and written as trace data is stored in an external trace memory at an event interval that occurs asynchronously.

As described above, the present invention incorporates a trace memory for storing program data addresses, program data and various status signals in order to check whether the program is running correctly. Separately, it has a small-capacity external trace memory buffer memory for tracing data stored in the trace memory in response to an event that occurs asynchronously. By using the time of an event interval that occurs asynchronously and providing a function of sequentially storing in a large-capacity trace memory configured outside the semiconductor device, real-time processing with low cost and high debugging efficiency is realized. A microcomputer development support device having a trace function can be provided.

Further, the present invention can be configured such that data stored in the buffer memory for the external trace memory is output to the outside as serial data via a parallel / serial conversion circuit.

Further, according to the present invention, when the buffer memory for the external trace memory becomes full and the buffer memory cannot be made in time, the status signal is outputted and notified.

According to the above configuration, if the average value of the throughput of the data stored in the buffer memory for the external trace memory is large and the output to the outside cannot be made in time, it is considered that a fault such as overrun has occurred. By outputting a status signal to notify the user, it is possible to know whether the information on which the trace is performed is valid or invalid.

Further, according to the present invention, a trace memory capable of tracing all bus cycles may be further provided in a semiconductor device having a processor.

As described above, the use of two trace memories, a large-capacity external trace memory and a built-in trace memory capable of tracing all bus cycles, makes it possible to eliminate asynchronous data defects and detailed program traces.
Correspondence and simultaneous analysis are possible, and debugging efficiency can be increased.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

Eva chip (target) 1 in FIG.
Is the processor 1 of the microprocessor development support device.
1, a memory 12 and a peripheral circuit 13 which are targets to be debugged.

The feature of the evaluation chip 1 is that, apart from the device to be debugged, the trace event run control circuit 17, the trace memory 18, the FIFO buffer memory 19 for the external trace memory, and the interface for interfacing with the outside of the evaluation chip 1 are provided. Parallel / Serial (P /
S) Conversion circuits 20 and 21 are built in. The trace memory 18 stores program data addresses, program data, and various status signals. The buffer memory 19 stores data stored in an external large-capacity trace memory 7 in response to an asynchronous event. Is used to temporarily store

Next, the function of each block will be described. The processor 11 is a processor such as a CPU or a DSP to be debugged, and is connected to the memory 12 via an address bus 14, a data bus 15, a status bus 16, and the like. .

The peripheral circuit 13 is also a user system to be debugged. The user configures a circuit and is built in the evaluation chip 1, and the processor 1 and the buses 14, 15 and
16 are connected.

Trace event run control circuit 17
Is for controlling the processor 11 to run and stop the program and for controlling the address output to the trace memory 18 and the writing / reading via the control bus a1.

Further, the trace event run control circuit 17 controls writing to the FIFO buffer memory 19 for the external trace memory through the control bus a2.

Then, debugger software for microcomputer development support runs on the host computer 4, and
An instruction for a debugging operation is output to the emulator control circuit 3 mainly through the control bus f1, and various data of registers and memories of the system to be debugged and trace data from the trace memory 18 and the external trace memory 7 are transmitted through the bus f1. It has a function of acquiring data and performing disassembly display and analysis of trace data.

An instruction for a debugging operation from the debugger software on the host computer 4 is sent to the parallel / serial conversion circuit 2 of the evaluation chip 1 through the emulator control circuit 3.
0, and enters the trace event run control circuit 17 through the control data bus c1. Then, a program run and stop control of the processor and a trace control as a condition for storing in the trace memory 18 and a trace control as a condition for storing in the FIFO buffer memory 19 for the external trace memory are performed.

The data bus b1 is connected to the host computer 4
When the contents of the trace memory 18 are read in response to a request from the CPU, data is transferred via the bus b1, the bus c1, the bus d1, and the f1.

The status bus b2 is a status output signal for notifying an abnormality when the FIFO buffer memory 19 for the trace memory cannot keep up.

Each time data is written to the trace buffer FIFO buffer memory 19, the data bus g1 outputs the write data to the parallel / serial conversion circuit 2.
1, the data is output to the outside of the evaluation chip 1, the data is further output from the bus h1 to the serial / parallel conversion circuit 5 and the external trace memory control circuit 6 through the i1 and j1 buses, and is sequentially stored in the large-capacity external trace memory 7. Will be.

The bus j1 is connected to the external trace memory 7
And a signal for controlling read and write operations.

When it is desired to read the data of the external trace memory 7 from the host computer 4, an address and a signal for reading the external trace memory 7 to the bus j1 by the control signal from the bus k1 through the emulator control circuit 3. A read signal is output, and data is read from the external trace memory 7 via the bus e1.

The feature of this embodiment described above is that a small-capacity FIFO for external trace memory is provided in the evaluation chip 1.
The buffer memory 19 is built in, and data written as trace data is transferred to the large-capacity external trace memory 7 while running a program, that is, during trace execution.

As another feature, the trace memory 18 is built in the evaluation chip 1 and has a function of storing a normal real-time trace, that is, all bus cycles in the trace memory 18.

An operation example of the present invention will be described with reference to the flow of a program shown in FIG. FIG. 2 simply shows the time flow of program execution.

When the program is executing main,
The subroutine A is entered by an asynchronous event A such as an interrupt or DMA, and the subroutine B is entered by an asynchronous event B such as an interrupt or DMA.

In a conventional real-time trace memory, the data stored in the trace memory built in the semiconductor device has, for example, the following uses.

A) With the program address information at a certain point as a trigger condition, all bus cycles before and after that are stored in the trace memory. b) Only the data access at the specific address is stored in the trace memory.

For example, if the bus cycle time of the processor to be debugged is 5 nsec (200M
Hz), T1 of FIG. 2 is 1 msec, T2 is 9 msec, and it is assumed that the built-in trace memory has 1 k addresses. Become. In the case of b), even if only specific data accesses in the subroutines A and B by the asynchronous events A and B are stored in the trace memory, the average number of asynchronous events is one.
Assuming that it occurs every 0 msec, only 1000 asynchronous events, that is, 10 sec of data access, can be stored in the trace memory.

For example, when a problem occurs at a rate of about once every 5 minutes, the trace memory is insufficient in time, and debugging is difficult.

Further, regarding the case b), 5 seconds
Data can be traced, and even if you find faulty data, in order to analyze the program and proceed with detailed debugging, it is more efficient to have all bus cycles, in which case the asynchronous error Using the event as a trigger condition, the asynchronous event is fetched into the trace memory in the mode of tracing all the bus cycles of a).

At this time, in the mode a), since the asynchronous event can be expected only once even if it enters, if the malfunction occurs in the situation of the combination of the asynchronous events A and B, it is very difficult to debug. is there.

On the other hand, in the example of FIG. 1 which is the embodiment of the present invention, the asynchronous events A and B shown in FIG. 2 are transmitted via the external trace memory FIFO buffer memory 19 and the parallel / serial conversion I / F 21. Finally, it is stored in a large-capacity external trace memory 7.

There are two types of asynchronous events, A and B. Each time an event occurs, it is stored in the FIFO buffer memory 19 for the external trace memory. The output is output to the outside of the evaluation chip 1 and stored in the external trace memory 7.

This output data is output to the outside using the time of the asynchronous event interval.

Even when a plurality of asynchronous events occur consecutively, serial output can be performed without any problem by providing the FIFO buffer memory 19 with a certain capacity.

The write signal, data generation, and address generation to the external trace memory 7 are generated by the serial / parallel conversion circuit 5 and the external trace memory control circuit 6.

On the other hand, the built-in trace memory 18 is a function for analyzing programs in all cycles and performing detailed debugging. The asynchronous event in which an error has occurred and the detailed trace of the program are executed once. Can be traced at the same time, so that errors can be easily found and debugging efficiency is improved.

After the trace data is acquired during the program running, the information of the internal register of the processor 11, the information of the memory 12, and the information of the memory 12 are transmitted through the emulator control circuit 3 by the instruction from the debugger program running on the host computer 4. The information of the peripheral circuit 13 is obtained and the trace memory 18 and the external trace memory 7
Debugging can be performed by collecting trace information, further analyzing and disassembling analysis, disassembly, and the like on the host computer 4 and displaying the information on the host computer.

FIGS. 3 and 4 show examples of the trace information.

It is considered effective to store the data stored in the external trace memory 7 together with the address of the memory before the data is processed in the subroutine due to the occurrence of the asynchronous event, the data after the processing, and the like. .

For example, the address and data as input data from the A / D converter which is a part of the function of the peripheral circuit to the DSP processor, which is often used in the signal processing program, etc. /
There are address and data information that are output data to the A converter.

If the external trace memory 7 is composed of a large-capacity memory and the memory has 1M addresses, assuming that asynchronous events occur every 10 msec on average, 100,000 asynchronous events, ie, 1
Information for data access of 0000 sec (about 166 minutes) can be stored in the external trace memory 7, and the faulty portion of the asynchronous event can be specified at a rate of about once every five minutes even if a fault occurs. .

Further, the program is re-run to the internal trace memory 18 with the data or address at which a defect occurs as a trigger condition, and as shown in FIG. 4, the program address, program data, data address, various data, read / write By storing various statuses such as time information and the like in the trace memory, it is possible to simultaneously analyze the malfunction of asynchronous data and the detailed trace of the program in association with each other.

[0054]

As described above, according to the present invention, since the FIFO buffer memory for the external trace memory is built-in, even if a high-speed MPU having a high-speed bus cycle is to be debugged, the real-time trace function can be performed without any problem. Can be used for debugging.

Also, due to the limitation of the capacity of the built-in trace memory, that is, due to manufacturing problems and cost problems, the trace memory capacity required for the debug system cannot be built in, resulting in poor debugging efficiency. , The constraint time of the interval that can be stored in the FIFO buffer memory for the external trace memory (the average value of the throughput of the data stored in the trace memory <the serial I
/ F throughput), but by providing a large-capacity external trace memory, debugging efficiency is improved.

Further, the external trace memory FIF
If the average value of the throughput of the data stored in the O buffer memory trace memory is large and the output to the outside cannot be made in time, a status signal is output from the trace memory block to notify that a failure such as overrun has occurred. It is possible to know whether the traced information is valid or invalid.

Further, since a relatively small capacity FIFO buffer memory for external trace memory is sufficient, the manufacturing cost of the evaluation chip is low.

Further, by using two trace memories of an external large-capacity trace memory and a built-in trace memory capable of tracing all bus cycles, a defect of asynchronous data and a detailed trace of a program can be associated with each other. In addition, analysis can be performed simultaneously, and debugging efficiency can be increased.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a temporal flow of program execution.

FIG. 3 is a schematic diagram illustrating an example of trace information.

FIG. 4 is a schematic diagram illustrating an example of trace information.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 evaluation chip 3 emulator control circuit 4 host computer 7 external trace memory 11 processor 12 memory 13 peripheral circuit 18 trace memory 19 FIFO buffer memory for external trace

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B042 GA13 GA33 GC03 HH30 LA18 MA04 MA08 MC03 MC07 MC08 MC09 MC31 5B048 AA12 BB02 DD04 DD10 5B062 AA08 CC02 EE05 EE09 JJ07 JJ08

Claims (4)

[Claims] An external trace memory buffer memory built in a semiconductor device having a processor, wherein data to be stored in the external trace memory is stored in the buffer memory by an event that occurs asynchronously;
A microcomputer development support apparatus, wherein the data written as trace data is stored in an external trace memory at an event interval that occurs asynchronously. 2. The microcomputer development support apparatus according to claim 1, wherein data stored in the buffer memory for external trace memory is output to the outside as serial data via a parallel / serial conversion circuit. 3. The microcomputer according to claim 1, wherein when the buffer memory for the external trace memory becomes full and the buffer memory cannot keep up, a status signal is output and notified. Development support equipment. 4. The microcomputer development supporting apparatus according to claim 1, further comprising a trace memory capable of tracing all bus cycles in a semiconductor device having a processor.