JP4084912B2 - Microprocessor system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer and an emulation system for system debugging in the microcomputer.
[0002]
[Prior art]
In developing a microprocessor (microcomputer) application device, an in-circuit emulator is used for debugging the application system and performing detailed evaluation of the system. The in-circuit emulator is connected between the parent computer for software development and the target system under development, and functions as a debugger while acting as a function of the microprocessor (target processor) included in the target system. Assist detailed system debugging. In such an emulator, the end of the cable extended from the main unit can be connected to the target system via a plug such as a socket for the target processor, and various data and status signals can be transmitted in real time during emulation. Various debugging functions such as a real-time trace function for sampling and storing it in a trace memory unit and a break function for substantially stopping the emulation operation are provided.
[0003]
In addition, even though it is a real chip, it has a function for tracing the execution state of software in real time, and an on-chip debug function that enables data read / write to the internal RAM (random access memory) for debugging. A provided microcomputer is provided. Here, the actual chip refers to a CPU that is actually mounted on the user system, and is distinguished from an emulation chip configured to be able to output necessary information for emulation.
[0004]
An example of a document describing the operation of the emulator is “All about microcomputer development (pages 78 to 95)” issued by Denpa Shimbun on June 20, 1989.
[0005]
[Problems to be solved by the invention]
Depending on the user system, a plurality of CPUs (central processing units) may be mounted in order to improve the processing capability. In conventional emulation, one emulator is basically required for each CPU. For example, in a user system equipped with two CPUs, two emulators are basically required. It is said.
[0006]
However, even if two emulators are connected to a user system on which two CPUs are mounted, since the two CPUs are not synchronized with each other, emulation cannot be executed simultaneously. In other words, even if two emulators are connected to the user system, the execution of the target program is stopped in the other emulator during one emulation, or the other CPU socket is actually running during one emulation. I was trying to wear a tip.
[0007]
As described above, in the emulation of a user system equipped with two CPUs, even if two emulators are connected, they must be emulated separately, which hinders the improvement of the development efficiency of the user system. .
[0008]
An object of the present invention is to provide a technique for improving the development efficiency of a user system.
[0009]
Another object of the present invention is to provide a technique for enabling simultaneous execution of a target program in emulation of a user system having a plurality of CPUs.
[0010]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, when a break condition is satisfied during execution of the user program, stack processing for transition to break mode is performed, and transition to user mode is performed by executing a return instruction for returning from break mode in break mode A central processing unit that performs the unstacking process, and after the unstacking, asserts a fault signal for causing the central processing unit to transition to the instruction waiting state, and in the instruction waiting state of the central processing unit, When the release request signal is asserted, the microprocessor includes a control means for releasing the instruction waiting state of the central processing unit.
[0013]
According to the above means, the control means asserts a fault signal, and in the instruction waiting state of the central processing unit, the instruction waiting state release request signal is asserted, whereby the central processing unit waits for an instruction. Is released. This synchronizes the different microprocessors and improves the development efficiency of the user system by parallelizing the emulation.
[0014]
In addition, when a break condition is satisfied during execution of the user program, stack processing is performed to enter the break mode, and the user enters the user mode by executing a return instruction for returning from the break mode in the break mode. If the state of the determination flag stored in the determination flag storage means and the determination flag storage means for storing the determination flag of the upper and lower relations indicates higher order, First control means for asserting an instruction waiting state release request signal output to the outside after the unstack processing, and when the state of the determination flag stored in the determination flag storage means indicates a lower order, after the unstacking Assert a fault signal for transitioning the central processing unit to the instruction waiting state. And, in the instruction waiting state of the central processing unit, by the release request signal is asserted, configuring the microprocessor and a second control means for canceling the instruction waiting state of the central processing unit.
[0015]
According to the above means, the second control means asserts a fault signal and waits for an instruction of the central processing unit by asserting a release request signal for the instruction waiting state in an instruction waiting state of the central processing unit. Release the state. This synchronizes the different microprocessors and improves the development efficiency of the user system by parallelizing the emulation.
[0016]
At this time, in response to a bus request or a bus release request from the outside, a bus controller that asserts a fault signal for causing the central processing unit to transition to an instruction execution waiting state, a fault signal from the bus controller, and the fault control A gate circuit may be provided that obtains a logical sum with a fault signal from the circuit and supplies it to the central processing unit.
[0017]
An emulation system is configured including such a microprocessor and an emulator body.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 5 shows an overall configuration example of an emulation system according to the present invention.
[0019]
As shown in FIG. 5, the emulation system includes a first emulation processor 511 and a second emulation processor 512, an emulator main body 52, and a control computer 53 mounted on the user system 51, although not particularly limited.
[0020]
The user system 51 has two CPU sockets, each with a CPU. The first emulation processor 511 and the second emulation processor 512 basically have functions equivalent to those of an actual chip originally mounted on the user system 51 and are configured to be capable of outputting internal bus information externally. Chip.
[0021]
Both the first emulation processor 511 and the second emulation processor 512 have an on-chip debugging function that enables debugging with the chip mounted on the system board. In particular, the first emulation processor 511 is connected to the emulator main body 52 via a connector 513 provided in the vicinity thereof and a cable 524 coupled thereto, whereby debugging by the on-chip debugging function is performed. ing. The external terminal of the second emulation processor 512 is coupled to the user system via the CPU socket of the user system 51 and coupled to the emulator main body 52 via the cable 525. Thereby, the emulation information of the second emulation processor 512 can be collected in the emulator main body 52. Although the control computer 53 is not particularly limited, it is a personal computer and is connected to the emulator main body 52 via the cable 516 so that various control information and collected data related to emulation can be exchanged with the emulator main body 52. It is possible.
[0022]
FIG. 1 shows a configuration example of the emulator main body 52.
[0023]
As shown in FIG. 1, the emulator main body 52 has an in-circuit emulation (ICE) function and an on-chip debug function as different emulation functions, although not particularly limited. The ICE function is realized by the ICE function block. The ICE function block includes a control CPU 11, a break circuit 12, a trace circuit 13, a monitor circuit 14, a firmware RAM (random access memory) 15, and a performance circuit 16. The on-chip debugging function is realized by the control CPU 11 and the on-chip controller 17.
[0024]
The control CPU 11 is coupled to the break circuit 12, the trace circuit 13, the monitor circuit 14, the firmware RAM 15, the performance circuit 16, and the on-chip controller 17 via the control bus 23, and can exchange various information with them. Is done. The second emulation processor 512 is coupled to the break circuit 12, the trace circuit 13, the monitor circuit 14, the firmware RAM 15, and the performance circuit 16 via the emulation bus 24, and stores various information in the emulation operation of the second emulation processor 512. Collection is possible. The on-chip controller 17 is coupled to the first emulation processor 511 via the signal line 25, and can exchange various information according to a predetermined communication protocol described later.
[0025]
The break circuit 12 monitors the state of the emulation bus 24 and breaks the emulation operation when the state reaches a preset state. The trace circuit 13 sequentially traces and stores data, addresses, and control information given to the emulation bus 24. The monitor circuit 14 is provided to enable the emulation bus 24 to be monitored from the control computer 53 via the interface 21. The firmware RAM 15 is provided for storing a program executed by the second emulation processor 512. The performance circuit 16 is provided for measuring the performance of the second emulation processor 512 based on the trace information, for example, measuring the execution time.
[0026]
The on-chip controller 17 is a block that enables on-chip debugging of the first emulation processor 511 under the control of the control CPU 11, and is configured as follows.
[0027]
FIG. 2 shows a configuration example of the on-chip controller 17.
[0028]
As shown in FIG. 2, the on-chip controller 17 includes a JTAG controller 170 for outputting various signals in the JTAG, a bus controller 176, and a clock generation circuit 177. The JTAG controller 170 includes buffers 171 to 174 and a register 175 for outputting various signals in JTAG. The clock generation circuit 177 includes an oscillator for generating a clock signal having a basic frequency, and a frequency dividing circuit for generating a clock signal having a frequency different from the original frequency by appropriately dividing the generated clock. . The clock signal output from the clock generation circuit 177 is transmitted to the first emulation processor 511 as TCK through the buffer 174. The output data TDo is transmitted to the bus controller 176 via the buffer 171, and a signal TDi for serially inputting a command and data to the test logic, a signal TMS for controlling the test operation, and a clock signal TCK supplied to the test logic A reset signal TRST for initializing the controller is output via the buffers 172 and 173 and the register 175, respectively. The bus controller 176 enables the exchange of signals between the buffers 171, 172, 173 and the register 175 and the control bus 23.
[0029]
Although not particularly limited, the first emulation processor 511 and the second emulation processor 512 have the same configuration.
[0030]
FIG. 3 shows a configuration example of the first emulation processor 511 (512).
[0031]
As illustrated in FIG. 3, the first emulation processor 511 (512) includes a CPU 213, a RAM 212, a serial debug interface 211, a peripheral module 215, and an emulation bus controller 216.
[0032]
When a predetermined program is executed by the CPU 213, the RAM 212 functions as a work area for the arithmetic processing. The serial debug interface 211 is connected to the on-chip controller 17 in the emulator main body 52 to enable serial data exchange.
[0033]
A bus controller 214 is provided, and wait control between the CPU 213 and the peripheral module 215 and wait control between the CPU 213 and the external module are performed. Although not particularly limited, the peripheral module 215 enables serial communication with an external device, a timer for time measurement, and data transfer between devices without intervention of the CPU 213. Includes direct memory access controllers.
[0034]
The serial debug interface 211D includes a communication module 211A, a firmware RAM 211B, a break circuit 211C, and a trace buffer 211D. The communication module 211A performs communication for on-chip debugging with an external device. Various programs executed by the CPU 213 are held in the firmware RAM 211B. The break circuit 211C determines whether or not a preset break condition is satisfied. The trace buffer 211D traces the program execution state in the CPU 213.
[0035]
The emulation controller 216 is coupled to the internal bus 218 and the emulation bus 24 and performs various controls relating to emulation. Although not particularly limited, the emulation controller 216 includes an upper / lower register 216A, a break stack register 216B, a break control circuit 216C, and a fault control circuit 216D. The upper / lower register 216A holds flag information for determining whether the emulation processor including the upper / lower register 216A is higher or lower in relation to other emulation processors. Although not particularly limited, in FIG. 1, the emulation processor 511 coupled to the emulation bus 24 is the upper level, and the emulation processor 512 coupled to the on-chip controller 17 is the lower level. The difference between the upper level and the lower level is greatly different in a state after completion of unstacking by execution of a return instruction from the break mode to the user mode. This will be described in detail later.
[0036]
When the break condition is satisfied and the state of the CPU 213 shifts from the user mode to the break mode, the break stack register 216B holds the values of the registers (EXR, CCR), the program counter (PC), and the like at that time.
[0037]
The break control circuit 216C performs input / output control of the break control signal. The break control signal includes a break interrupt request signal and a break acknowledge signal. The break interrupt is made low active, and when it is activated, a break interrupt to the CPU 213 is performed by the break control circuit 216C. Break processing is performed by this break interrupt, and the values of the registers (EXR, CCR) and program counter (PC) at that time are held in the break stack register 216B. When the CPU 213 shifts to the break mode due to the break interrupt, the break control circuit 216C sets the break acknowledge signal to the low level, indicating that the break mode has been entered. The break acknowledge signal is at a low level during the break mode, and is set to a high level after the return from break (RTB) instruction is completed. In other words, the break mode is canceled by executing a dedicated return (RTB) instruction, thereby transitioning from the break mode to the user mode.
[0038]
The bus controller 214 outputs a first fault signal FLT1, and the emulation controller 216 outputs a second fault signal FLT2. The OR logic of the first fault signal FLT1 and the second fault signal FLT2 is obtained by the OR gate 217, and the OR logic is transmitted to the CPU 213.
[0039]
The first fault signal FLT1 is issued when there is a bus request from the outside of the microprocessor or a bus release request from another bus master to the bus controller 214, and the bus right is to be released as a result of the bus right arbitration. , And asserted high by the bus controller 214. When the first fault signal FLT1 is asserted to a high level, the CPU 213 can execute an instruction while maintaining the internal state (a value of a program counter or the like) when the first fault FLT1 is asserted to a high level. Stopped (fault condition). As a result, the bus is released from the CPU 213.
[0040]
Also, the second fault signal FLT2 is an upper / lower register. 216A It is controlled by the fault control circuit 216D according to the flag state. That is, when the flag state of the upper / lower register 216 is set to the low level and the emulation processor is set to the lower level, the fault control circuit 216D executes the second fault signal after the CPU 213 executes the return instruction from the break mode. FLT2 is asserted high. As a result, in the CPU 213, the execution of the instruction is stopped (fault state) while maintaining the internal state (the value of the program counter or the like), as in the case where the first fault FLT1 is asserted to the high level. This fault state is maintained until the second fault signal FLT2 is negated to the low level by asserting the fault release request signal supplied from the outside of the emulation controller 216 to the low level. That is, when the fault release request signal given from the outside of the emulation controller 216 is asserted to the low level, the fault control circuit 216D negates the second fault signal FLT2 to the low level. As a result, the fault state of the CPU 213 is released. Such a control function in the fault control circuit 216D corresponds to the second control means in the present invention.
[0041]
On the other hand, when the flag state of the upper / lower register 216A is set to the high level and the emulation processor is set to the upper level, the fault control circuit 216D externally outputs the signal without asserting the second fault signal FLT2. In contrast, a fault release request signal for another CPU is asserted. This control function in the fault control circuit 216D corresponds to the first control means in the present invention.
[0042]
FIG. 4 shows a configuration example of the communication module 211A.
[0043]
As shown in FIG. 4, the communication module 211A includes a JTAG-compatible TAP controller 211A-1, an input register 211A-2, and an output register 211A-3. A clock signal TCK supplied to the test logic, a reset signal TRST for initializing the controller, and a signal TMS for controlling the test operation are input to the TAP controller 211A-1. The TAP controller 211-A1 analyzes an input command and performs input / output control based on the analysis. The input register 211A-2 and the output register 211A-3 are not particularly limited, but are 32-bit shift registers, which respectively shift the signals TDi and TDo captured in the serial format.
[0044]
Next, the return from the break mode to the user mode will be described in detail.
[0045]
FIG. 6 shows a procedure from the break mode to the return to the user mode in the first emulation processor 511 and the second emulation processor 512. FIG. 7 shows the operation timing of the main part in that case.
[0046]
The first emulation processor 511 is a lower level processor, and the second emulation processor 512 is an upper level processor.
[0047]
In the first emulation processor 511, an unstack such as a program counter (PC) is executed by executing a return from break mode (RTB) instruction during a period in which a program held in the firmware RAM 211B is being executed. (S711, S721). In this unstack, the flag state of the upper / lower register 216 is checked. Since the first emulation processor 511 is a lower level processor, the flag state of the upper / lower register 216 is at a low level. As a result, the second fault signal FLT2 is asserted to a high level, and the CPU 213 in the first emulation processor 511 enters a fault (waiting for the next instruction) state. That is, despite the unstacking of the program counter (PC) or the like in step S712, the first instruction execution waiting state in the user mode is set. This state continues until a fault release request is made from the second emulation processor 512, which is a higher-level processor.
[0048]
On the other hand, in the second emulation processor 512, the program counter (PC) is executed by executing the return from break mode (RTB) instruction during the period in which the program held in the firmware RAM 15 (see FIG. 1) is being executed. ) And the like are performed (S721, S722). In this unstack, the flag state of the upper / lower register 216 is checked. Since the second emulation processor 512 is an upper level processor, the flag state of the upper / lower register 216 is set to the high level. As a result, the emulation controller 216 asserts the fault release request signal to a low level, thereby making a request to release the fault state of the first emulation processor 511 (S723). After this cancellation request, the second emulation processor 512 shifts to execution of the user program.
[0049]
When the low level fault release request signal is transmitted to the first emulation processor 511, the first emulation processor 511 negates the second fault signal FLT2 to the low level by the fault control circuit 216D in the emulation controller 216. Is done. As a result, the fault state is released, and the CPU 213 starts executing the user program.
[0050]
According to the above example, the following effects can be obtained.
[0051]
(1) After the first emulation processor 511 at the lower level executes a return from break mode (RTB) instruction, the fault state is entered, and a fault release request (S723) is made from the second emulation processor 512 at the higher level. Thus, the first emulation processor 511 and the second emulation processor 512 are synchronized with each other by releasing the fault state of the first emulation processor 511. That is, even if asynchronous processing is performed in the break mode, the first emulation processor 511 and the second emulation processor 512 are synchronized at the time of starting execution of the user program after returning from the break mode. Therefore, the first emulation processor 511 and the second emulation processor 512 can be executed and emulated at the same time, so that the development efficiency of the user program can be improved.
[0052]
(2) One emulator main body 52 is sufficient, and there is no need to prepare separately as an ICE emulator and an on-chip debugging emulator.
[0053]
Another configuration example will be described.
[0054]
As shown in FIG. 8, the on-chip debugging emulator main body 85 and the emulator main body 86 may be configured separately. The emulator main body 85 for on-chip debugging basically includes the on-chip controller 17, the control CPU 11, the interface 21, and the like in FIG. 1, but the break circuit 12, the trace circuit 13, the monitor circuit 14, the farm RAM 15, ICE function implementation blocks such as the performance circuit 16 are not included. The emulator main body 86 includes ICE function implementation blocks such as the break circuit 12, the trace circuit 13, the monitor circuit 14, the firmware RAM 15, the performance circuit 16, the control CPU 11, and the interface 21 in FIG. Not included. A control computer 81 is connected to the lower microprocessor-side emulator 85, and a control computer 82 is connected to the upper microprocessor-side emulator 86.
[0055]
Further, as shown in FIG. 9, the two microprocessors 511 and 512 may perform emulation via the emulation bus. In this case, the emulator main bodies 85 and 86 include ICE function implementation blocks such as the break circuit 12, the trace circuit 13, the monitor circuit 14, the firmware RAM 15, the performance circuit 16, the control CPU 11, and the interface 21 in FIG.
[0056]
As shown in FIG. 10, two microprocessors shown in FIG. 3 may be provided in one microprocessor package. Even in such a case, the present invention can be applied. In this case, the emulator main body 52 is provided with an ICE function realizing block corresponding to two microprocessors.
[0057]
Furthermore, as shown in FIG. 11, when two microprocessors are provided in one microprocessor package, the serial debug interface can be used to exchange signals with the emulator main body. . In this case, the emulator main body 52 is provided with two on-chip controllers 17 and the like.
[0058]
As shown in FIG. 12, the connection relationship between the first emulation processor 511, the second emulation processor 512, and the emulator main body 512 may be switched. That is, the control circuit 18 is provided, and the control circuit 18 controls which of the first emulation processor 511 and the second emulation processor 512 the emulation bus 24 is connected to. A selector (SEL) 19 is provided, and the on-chip controller 17 is selectively connected to the first emulation processor 511 and the first emulation processor 512. The operation of the selector 19 is controlled by the control circuit 18. When data exchange between the first emulation processor 511 and the emulation bus 24 is enabled under the control of the control circuit 18, the second emulation processor 512 is disconnected from the emulation bus 24. At this time, the second emulation processor 512 is coupled to the on-chip controller 17 via the selector 19 under the control of the control circuit 18, thereby enabling on-chip debugging in the second emulation processor 512. Similarly, when data exchange between the second emulation processor 512 and the emulation bus 24 is enabled under the control of the control circuit 18, the first emulation processor 511 is disconnected from the emulation bus 24. At this time, the first emulation processor 511 is coupled to the on-chip controller 17 via the selector 19 under the control of the control circuit 18, thereby enabling on-chip debugging in the first emulation processor 511.
[0059]
The present invention can be applied even in the case of having three or more microprocessors. That is, by setting one of the three or more microprocessors at the upper level and setting all the other microprocessors at the lower level, the same operation and effect as in the above example can be obtained.
[0060]
Further, the fault state release request signal may be generated from the control CPU 11. FIG. 13 shows a configuration example in that case. In this case, after all of the three microprocessors 511, 512 and 513 are faulted, the fault release request signal supplied from the control CPU 11 to the three microprocessors 511, 512 and 513 is asserted. be able to. As a result, the three microprocessors 511, 512, and 513 are simultaneously released from the fault state, and the user program can be synchronously executed. FIG. 14 shows a specific configuration in this case. An on-chip controller 141 for enabling on-chip debugging of the third emulation processor 513 is provided. The fault release request signal is generated not by the individual emulation processors 511, 512, 513 but by the control CPU 11.
[0061]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0062]
In the above description, the case where the invention made mainly by the present inventor is applied to the microprocessor which is the field of use behind it can be widely applied to various data processing apparatuses.
[0063]
The present invention can be applied on condition that at least a CPU is included.
[0064]
【The invention's effect】
That is, after unstacking, a fault signal for transitioning the central processing unit to the instruction waiting state is asserted, and the instruction waiting state release request signal is asserted in the central processing unit instruction waiting state. And a control means for releasing the instruction waiting state of the processing unit, so that in the instruction waiting state of the central processing unit, the instruction waiting state release request signal is asserted and the central processing unit The instruction wait state is released. Thereby, it is possible to synchronize different microprocessors and improve the development efficiency of the user system by parallelizing the emulation.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an emulator main body in an emulation system according to the present invention.
FIG. 2 is a block diagram illustrating a configuration example of an on-chip controller 17 included in the emulator main body.
FIG. 3 is a block diagram illustrating a configuration example of an emulation processor used in the emulation system.
FIG. 4 is a block diagram illustrating a configuration example of a communication module included in the emulation processor.
FIG. 5 is an explanatory diagram of an overall configuration example of the emulation system.
FIG. 6 is a flowchart from the break mode to the return to the user mode in the emulation processor.
FIG. 7 is a timing chart from the break mode to the return to the user mode in the emulation processor.
FIG. 8 is an explanatory diagram of another configuration example of the emulation system.
FIG. 9 is an explanatory diagram of another configuration example of the emulation system.
FIG. 10 is an explanatory diagram of another configuration example of the emulation system.
FIG. 11 is an explanatory diagram of another configuration example of the emulation system.
FIG. 12 is a block diagram illustrating a configuration example of an emulator main body in another configuration example of the emulation system.
FIG. 13 is an explanatory diagram of another configuration example of the emulation system.
FIG. 14 is a block diagram illustrating a configuration example of an emulator main body in another configuration example of the emulation system.
[Explanation of symbols]
11 Control CPU
12 Break circuit
13 Trace circuit
14 Monitor circuit
15 Farm RAM
16 Performance circuit
17 On-chip controller
18 Control circuit
19 Selector
21 Interface
23 Control bus
24 emulation bus
211 Serial debug interface
211A Communication module
211B Farm RAM
211C break circuit
211D Trace buffer
212 RAM
213 CPU
214 Bus controller
215 Peripheral module
216 emulation controller
216A High / low register
216B Break stack register
216C break control circuit
216D Fault control circuit
217 or gate
511 First emulation processor
512 Second emulation processor

Claims (5)

A microprocessor system in which first and second microprocessors each capable of executing on-chip debugging are mounted in one package,
The first microprocessor comprises a first and a central processing unit capable of executing a user program, a first break control circuit for break control to determine that the break condition is satisfied, which is set in advance ,
The second microprocessor includes a second central processing unit capable of executing a user program, and a second break control circuit that performs break control by determining that a preset break condition is satisfied. ,
The first break control circuit and the second break control circuit can output a control signal indicating the break mode when the break condition is satisfied and the break mode is entered ,
The first microprocessor and the second microprocessor are in an instruction waiting state when one of the microprocessors returns from the break mode, and when the other microprocessor returns from the break mode, the other microprocessor The instruction waiting state of one of the microprocessors is canceled in response to a predetermined signal output from the microprocessor, thereby enabling synchronization processing at the start of user program execution after returning from the break mode. A microprocessor system characterized by that. It said first and second microprocessors when a transition to the break mode, the microprocessor system of claim 1, wherein executing a predetermined program stored in the memory. The microprocessor system can be connected to one emulator,
3. The microprocessor system according to claim 2 , wherein the emulator can control an emulation operation when the break mode is entered. 4. The microprocessor according to claim 3, wherein the first and second central processing units can perform a return process for shifting to the user mode by executing a predetermined instruction. system. The first and second central processing units unstack the value of the program counter held when shifting to the break mode when a return instruction is executed upon return from break mode. The microprocessor system according to claim 4 .

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