JP2004094451A - On-chip jtag interface circuit and system lsi - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To debug without operating a processor in an on-chip JTAG realizing on-chip debugging and a system LSI applying it. <P>SOLUTION: This on-chip JTAG interface circuit is provided with a JTAG interface means for performing data communication by a debugger outside the system LSI and a serial signal input/output, a bus control means for generating a first control signal of data bus in compliance with an instruction input from the debugger through the JTAG interface means and controlling the data bus, and a bus selecting means for selectively changing over between a second control signal of the data bus input from a processor and the first control signal and connecting it to the data bus. Either one of the processor or the debugger controls the data bus to be connected to a processing unit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an on-chip JTAG interface circuit for realizing on-chip debugging and a system LSI using the same.
[0002]
[Prior art]
As one of the debugging techniques for a system LSI including a processor, a technique called on-chip debugging in which a processor is provided with a debugging function using IEEE1149.1 is used. On-chip debugging using IEEE1149.1 is described, for example, in "Basics and Application of JTAG Testing" (CQ Publishing Company).
[0003]
FIG. 11 is a configuration diagram of a conventional on-chip JTAG interface circuit for realizing on-chip debugging using IEEE1149.1. The conventional on-chip JTAG interface circuit 1 has input / output ports for serial signals TDI, TMS, TDO, and TCK compliant with IEEE1149.1 (TRST is optional). The TAP controller 2 controls a shift operation of each internal register while performing a state transition according to a TMS signal input for selecting a test mode. The instruction register (IR) 3 is composed of a shift register and a latch, and inputs or outputs an instruction one bit at a time in response to a shift instruction from the TAP controller 2 and latches the input instruction in response to an update instruction from the TAP controller 2. .
[0004]
The instruction decoding unit 4 decodes the instruction input to the instruction register 3 and controls each unit to execute the instruction. The processor control register 6 is one of data registers (DR), and is composed of a shift register and a latch, like the instruction register 3. The processor control register 6 determines the operation mode and status of the processor 5 to be debugged from the TAP controller 2 and the instruction decode unit 4. Operate according to instructions. The scan register 7 is one of data registers (DR), and is formed by serially connecting cells each composed of a 1-bit shift register and a latch in correspondence with an input / output terminal of the processor 5. The scan register 7 inputs the data input from the TDI to the input terminal of the processor 5 and outputs the state of the output terminal of the processor 5 from the TDO according to an instruction from the TAP controller 2 and the instruction decoding unit 4.
[0005]
As the instructions to be set in the instruction register 3, two TEST1 instructions and TEST2 instructions are prepared as private instructions. The TEST1 instruction controls the operation of the processor 5 by selecting the processor control register 6 as the data register (DR) and setting the operation mode in the processor control register 6 from TDI. The TEST2 instruction selects the scan register 7 as the data register (DR), inputs data input from the TDI to the processor 5, and outputs data output from the processor 5 from the TDO.
[0006]
Next, an operation for reading the content of an arbitrary address in a certain target memory will be described. First, the processor control register 6 is set to the hold state by the TEST1 instruction, and the execution of the processor 5 is stopped. Next, the processor control register 6 is set to a mode in which the instruction is taken in from the outside by the TEST1 instruction. Next, a memory load instruction of the processor 5 is set to a portion corresponding to the data bus in the scan register 7 by a TEST2 instruction. Then, the processor control register 6 is set to step execution by the TEST1 instruction, and the processor 5 is caused to execute step execution. As a result, the contents of the target memory are loaded into the internal register of the processor 5 specified by the memory load instruction.
[0007]
Next, the processor control register 6 is set to a mode in which the instruction is taken in from the outside by the TEST1 instruction. Next, a store memory instruction of the processor 5 is set in a portion corresponding to the data bus in the scan register 7 by a TEST2 instruction. Then, the processor control register 6 is set to step execution by the TEST1 instruction, and the processor main body 5 is caused to execute step execution. As a result, the content previously loaded into the internal register is set in a portion of the scan register 7 corresponding to the data bus. Then, the scan path is shifted by the TEST2 instruction, and data is serially extracted from TDO.
[0008]
By operating in this way, the conventional on-chip JTAG interface circuit 1 can read the contents of the target memory using the serial signal input / output terminal, and can perform debugging.
[0009]
[Problems to be solved by the invention]
The conventional on-chip JTAG interface circuit reads a target memory by causing a processor to execute a load instruction. For this reason, for example, when a large amount of data such as image data is read, a large amount of instructions must be executed by a processor, and there is a problem that it takes a long time to read.
In the conventional on-chip JTAG interface circuit, since the processor always operates during debugging, in a system LSI that is becoming more complicated in recent years, whether the cause of the illegal operation is the processor or the other processing blocks connected to the processor There is a problem that it is difficult to determine the cause of the existence.
[0010]
The present invention has been made to solve the above problems, and has as its object to enable debugging without operating a processor.
[0011]
[Means for Solving the Problems]
An on-chip JTAG interface circuit according to the present invention includes a processor, a processing unit that performs an arbitrary process, and a data bus, wherein the processor controls the data bus to communicate with the processing unit. ,
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
Bus control means for generating a first control signal for the data bus according to an instruction input from the debugger through the JTAG interface means and controlling the data bus;
A second control signal for the data bus input from the processor, and a bus selection unit for selectively switching between the first control signal and the data bus to connect to the data bus;
One of the processor and the debugger controls the data bus to enable communication with the processing unit.
[0012]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means may input reset information of the processing unit from the debugger through the serial signal input / output and generate a first reset signal according to the reset information. Generate
A reset selection unit configured to selectively switch between a second reset signal and the first reset signal of the processing unit input from the processor and output to the processing unit.
[0013]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means receives an interrupt signal or an error notification signal output from the processing unit, and outputs the interrupt signal or error notification from the debugger through the serial signal input / output. The state of the signal can be read.
[0014]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means inputs stop factor information from the debugger through the serial signal input / output,
A stop signal generating unit that generates a stop signal for stopping all of the processing units from the interrupt signal or the error notification signal and the stop factor information,
The stop signal is output to all of the processing units.
[0015]
Further, the on-chip JTAG interface circuit according to the present invention includes a processor, a processing unit for performing an arbitrary process, a data bus, and one processing block among a plurality of processing blocks including the processor and the processing unit. An arbitration circuit for selecting and permitting use of the data bus.
The processor and the processing unit can control the data bus to access an internal or external memory of the system LSI;
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
Bus control means for generating a control signal for the data bus in accordance with an instruction input from the debugger through the JTAG interface means and controlling the data bus;
The debugger controls the data bus to enable communication with the memory.
[0016]
Further, an on-chip JTAG interface circuit according to the present invention provides a system LSI including a processor, one or more processing units for performing arbitrary processing, a system bus, a dedicated processor, a data bus, and an arbitration circuit. ,
The arbitration circuit selects one processing block from a plurality of processing blocks including the dedicated processor and the processing unit and permits use of the data bus,
The host processor communicates with the processing unit by controlling the system bus,
The dedicated processor and the processing unit are capable of controlling the data bus to access an internal or external memory of the system LSI;
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
First bus control means for generating a first control signal for the system bus according to an instruction input from the debugger through the JTAG interface means;
Bus selection means for selectively switching between the second control signal of the system bus input from the host processor and the first control signal and connecting to the system bus;
Second bus control means for generating a control signal for the data bus in accordance with an instruction input from the debugger through the JTAG interface means and controlling the data bus,
Either the host processor or the debugger controls the system bus to enable communication with the processing unit,
The debugger controls the data bus to enable communication with the memory.
[0017]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means may input reset information of the processing unit from the debugger through the serial signal input / output and generate a first reset signal according to the reset information. Generate
A reset selection unit that selectively switches between the second reset signal and the first reset signal of the processing unit input from the host processor and outputs the signal to the processing unit.
[0018]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means receives an interrupt signal or an error notification signal output from the processing unit, and outputs the interrupt signal or error notification from the debugger through the serial signal input / output. Signal information can be read.
[0019]
Also, in the on-chip JTAG interface circuit according to the present invention, the JTAG interface means inputs stop factor information from the debugger through the serial signal input / output,
A stop signal generating unit that generates a stop signal for stopping all of the processing units from the interrupt signal or the error notification signal and the stop factor information,
Outputting the stop signal to the processing unit;
[0020]
Also, a system LSI according to the present invention includes an on-chip JTAG interface circuit according to any one of claims 1 to 9, a processor, a processing unit for performing any processing, an on-chip JTAG interface circuit, a processor, And a bus for inputting and outputting signals to and from the processing unit.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a system LSI including an on-chip JTAG interface circuit according to the first embodiment of the present invention. The debugger 11 is a verification environment outside the system LSI in which a verifier directly operates, and includes, for example, a PC and a board. The debugger 11 performs data communication with the on-chip JTAG interface circuit 14 in the system LSI 10 by serial signal input / output conforming to the IEEE1149.1 standard.
[0022]
The on-chip JTAG interface circuit 14 controls the system bus 13 in accordance with a command input from the debugger 11 through serial signal input / output, and switches the system bus signal so that the host processor 12 can also control the system bus 13. The dedicated processing units 15 and 16 are processing blocks for performing a specific process, and each have a plurality of bus registers that can be read and written from the system bus 13. The bus registers include a register for controlling activation and deactivation of the dedicated processing units 15 and 16 and a register for storing processing results of the dedicated processing units 15 and 16. The bus register can be read or written from the system bus 13. Thereby, the dedicated processing units 15 and 16 can be started or stopped, and the processing results of the dedicated processing units 15 and 16 can be read.
[0023]
The on-chip JTAG interface circuit 14 receives a reset signal of the dedicated processing units 15 and 16 from the host processor 12, selects one of the reset information specified by the debugger 11, and resets the reset signal of the dedicated processing units 15 and 16. Output as 19 and 20.
[0024]
The dedicated processing unit 15 outputs an error notification signal 17 to the host processor 12 via the on-chip JTAG interface circuit 14. The dedicated processing unit 16 also outputs an interrupt signal 18 to the host processor 12 via the on-chip JTAG interface circuit 14.
The dedicated processing units 15 and 16 are stopped while retaining the internal state by the stop signal 37 from the on-chip JTAG interface circuit 14, and the bus register can be read from the system bus 13 in the stopped state.
[0025]
The commands input from the debugger 11 to the on-chip JTAG interface circuit 14 include a system bus write command for writing via the system bus 13, a system bus read command for reading via the system bus 13, and dedicated processing units 15 and 16. An individual reset instruction for controlling each reset state, an interrupt / error status read instruction for reading the interrupt signal 18 and the error notification signal 17 output from the dedicated processing units 15 and 16, and a stop factor setting instruction for controlling generation of the stop signal 37 are provided. is there.
[0026]
FIG. 2 shows the internal configuration of the on-chip JTAG interface circuit 14. The on-chip JTAG interface circuit 14 includes a JTAG interface unit 21, a system bus interface 33 serving as a bus control unit, a bus selection unit 34, a reset selection unit 35 for selecting a reset signal depending on whether the debug mode signal 32 is a normal operation or a debug operation, and a stop. It comprises a stop signal generating means 36 for outputting a signal 37.
[0027]
The JTAG interface means 21 communicates with the debugger 11 through signal input / output conforming to the IEEE1149.1 standard, and instructs the system bus interface 33 with an instruction input from the debugger 11.
The JTAG interface means 21 includes registers 22 to 29 each including a shift register and a latch, a TAP controller for controlling the shift operation of the registers 22 to 29 in accordance with a TMS signal input, and an instruction decoding unit (not shown). I have.
[0028]
The registers 22 to 29 include an instruction register (IR) 22 for holding an instruction input from the debugger 11, an IM read address register 23 for holding a read address, an IM read data register 24 for holding read data, a write address and It comprises an IM write register 25 for holding write data, an IM status register 26 for holding the operation end of the system bus interface 33, an interrupt / error status register 27, an individual reset register 28, and a stop cause register 29.
[0029]
The system bus interface 33 generates a system bus signal 31 according to an instruction from the JTAG interface unit 21. The debug mode signal 32 is a signal that is input from outside and indicates a normal operation or a debug operation. The bus selecting means 34 connects the system bus signal 30 of the host processor 12 to the system bus 13 when the debug mode signal 32 is a normal operation, and connects the system bus signal of the system bus interface 33 when the debug mode signal 32 is a debug operation. 31 is connected to the system bus 13.
[0030]
Next, the operation will be described first when a system bus write instruction is executed.
FIG. 3 shows input / output signals of the JTAG interface means 21 when the debugger 11 executes a system bus write instruction, and state transitions according to the IEEE1149.1 standard. First, the debugger 11 sets a system bus write instruction in the instruction register (IR) 22. If the content of the instruction register (IR) 22 is a system bus write instruction, the JTAG interface means 21 switches the data register (DR) to be controlled next to the IM write register 25. Next, the debugger 11 sets the write address and the write data in the IM write register 25. Thereafter, the JTAG interface means 21 switches the data register (DR) to be controlled next to the IM status register 26, and the debugger 11 repeats reading the IM status register 26 until the read operation is completed.
[0031]
On the other hand, the JTAG interface unit 21 instructs the system bus interface 33 to perform the write operation and the contents of the IM write register 25. Then, the system bus interface 33 controls the system bus 13 to write the write data of the IM write register 25 to the bus register indicated by the write address of the IM write register 25, and outputs an operation end signal to the JTAG interface means 21. The JTAG interface unit 21 stores information indicating the end of the operation in the IM status register 26. Then, the debugger 11 obtains information of the operation end by reading the IM status register 26.
[0032]
Next, a case where a system bus read instruction is executed will be described.
FIG. 4 shows input / output signals of the JTAG interface unit 21 when the debugger 11 executes a system bus read instruction, and state transitions according to the IEEE1149.1 standard. First, the debugger 11 sets a system bus read instruction in the instruction register (IR) 22. If the content of the instruction register (IR) 22 is a system bus read instruction, the JTAG interface means 21 switches the data register (DR) to be controlled next to the IM read address register 23. Next, the debugger 11 sets the read address in the IM read address register 23. Thereafter, the JTAG interface means 21 switches the data register (DR) to be controlled next to the IM status register 26, and the debugger 11 repeats the read operation of the data register (DR) twice each time until the read operation is completed.
[0033]
During this time, the JTAG interface means 21 controls the IM status register 26 and the IM read data register 24 to be read alternately. On the other hand, the JTAG interface unit 21 instructs the system bus interface 33 to perform a read operation and the contents of the IM read address register 23. Then, the system bus interface 33 reads the data of the bus register indicated by the read address of the IM read address register 23 by controlling the system bus 13, and outputs an operation end signal and read data to the JTAG interface means 21. The JTAG interface means 21 stores information indicating the end of operation in the IM status register 26 and stores read data in the IM read data register 24. Then, the debugger 11 acquires operation completion information and read data by reading the IM status register 26 and the IM read data register 24.
[0034]
Next, a case where an individual reset instruction is executed will be described.
When the individual reset instruction from the debugger 11 is set in the instruction register (IR) 22, the JTAG interface means 21 switches the data register (DR) to be controlled next to the individual reset register 28, and the debug information from the debugger 11 resets each dedicated processing unit. Is set in the individual reset register 28. The reset selection means 35 processes the reset signal 39 input from the host processor 12 when the debug mode signal 32 indicates the normal operation, and the contents of the individual reset register 28 when the debug mode signal 32 indicates the debug operation, Output as reset signals 19 and 20 of the unit.
[0035]
Next, a case where an interrupt / error status read instruction is executed will be described.
The interrupt / error status register 27 stores an interrupt signal or an error notification signal 38 (collecting 17 to 18 in FIG. 1 as a multi-bit signal) input from the dedicated processing units 15 and 16. Then, when the interrupt / error status read instruction is set in the instruction register (IR) 22 from the debugger 11, the JTAG interface means 21 switches the data register (DR) to be controlled next to the interrupt / error status register 27, and the debugger 11 / Read the error status register 27.
[0036]
Next, a case where a stop cause setting instruction is executed will be described.
When a stop cause setting instruction from the debugger 11 is set in the instruction register (IR) 22, the JTAG interface unit 21 switches the data register (DR) to be controlled next to the stop cause register 29, and the debugger 11 switches to the stop cause register 29. Write the stop factor information to The stop factor information is information indicating whether each bit of the interrupt signal or the error notification signal 38 is valid or invalid. When a valid signal is input and the debug mode signal 32 indicates a debug operation, the stop factor information is displayed. The signal generation means 36 outputs a stop signal 37 for stopping the operation of all dedicated processing units.
[0037]
With this operation, the debugger 11 can directly control the activation of the dedicated processing unit, read the processing result, control the reset, monitor the interrupt signal or the error notification signal, and perform debugging without operating the processor. it can.
[0038]
Further, by outputting the stop signal 37 corresponding to the interrupt signal or the error notification signal, debugging can be performed while maintaining the state of the signal at the time of occurrence of the error or the interrupt of the designated processing block.
[0039]
Embodiment 2 FIG.
FIG. 5 is a configuration diagram of a system LSI including an on-chip JTAG interface circuit according to the second embodiment of the present invention. The debugger 41 is a verification environment outside the system LSI 40 in which a verifier directly operates, and includes, for example, a PC and a board. The debugger 41 performs data communication with the on-chip JTAG interface circuit 43 in the system LSI 40 by serial signal input / output conforming to the IEEE1149.1 standard.
[0040]
The on-chip JTAG interface circuit 43 is a processing block that accesses the data bus 46 in accordance with an instruction input from the debugger 41. The processor 42 is a processing block that accesses the memory 45 via the data bus 46 and executes arbitrary processing. The dedicated processing units 47 and 48 are processing blocks that access the memory 45 via the data bus 46 and perform a specific process.
[0041]
The arbitration circuit 44 inputs a bus use request signal from the processor 42, the dedicated processing units 47 and 48, and the on-chip JTAG interface circuit 43, and if the data bus 46 is in an unused state, causes the data bus 46 to be used next. One processing block is selected, a bus use permission signal is output to the processing block, and the data bus 46 is used. In the present embodiment, a mechanism of a memory interface that mediates between the memory 45 and the data bus 46 is omitted for simplification.
[0042]
FIG. 6 shows an internal configuration diagram of the on-chip JTAG interface circuit 43. The on-chip JTAG interface circuit 43 includes a JTAG interface means 51 and a data bus interface 52 which is a bus control means. The JTAG interface means 51 communicates with the debugger 41 by signal input / output conforming to the IEEE1149.1 standard, and instructs the data bus interface 52 with an instruction input from the debugger 41.
[0043]
The data bus interface 52 controls the data bus 46 in accordance with an instruction from the JTAG interface means 51 and outputs a result to the JTAG interface means 51. The JTAG interface means 51 includes an instruction register (IR) 54 for holding an instruction input from the debugger 41, an FM read address register 55 for holding a read address, an FM read data register 56 for holding read data, a write address and A TAP controller and an instruction decoding unit which include an FM write register 57 for holding write data and an FM status register 58 for holding the end of operation of the data bus interface 52, and which control shift operations of the registers 54 to 58 in accordance with a TMS signal input (Not shown).
[0044]
Next, the operation when the data bus write instruction is executed from the debugger 41 will be described. First, the debugger 41 sets a data bus write instruction in the instruction register (IR) 54. If the instruction in the instruction register (IR) 54 is a data bus write instruction, the JTAG interface means 51 switches the data register (DR) to be controlled next to the FM write register 57. Next, the debugger 41 sets the write address and the write data in the FM write register 57.
Thereafter, the JTAG interface unit 51 switches the data register (DR) to be controlled next to the FM status register 58, and the debugger 41 repeats reading of the FM status register 58 until the read operation is completed.
[0045]
On the other hand, the JTAG interface unit 51 instructs the data bus interface 52 to perform the write operation and the contents of the FM write register 57. Then, the data bus interface 52 controls the data bus 46 to write the write data of the FM write register 57 to the memory cell indicated by the write address of the FM write register 57, and outputs an operation end signal to the JTAG interface means 51. The JTAG interface means 51 stores information indicating the end of the operation in the FM status register 58. Then, the debugger obtains information of the operation end by reading the FM status register 58.
[0046]
Next, the operation when the data bus read instruction is executed from the debugger 41 will be described. First, the debugger 41 sets a data bus read instruction in the instruction register (IR) 54. If the instruction in the instruction register (IR) 54 is a data bus read instruction, the JTAG interface means 51 switches the data register (DR) to be controlled next to the FM read address register 55. Next, the debugger 41 sets the read address in the FM read address register 55.
[0047]
Thereafter, the JTAG interface unit 51 switches the data register (DR) to be controlled next to the FM status register 58, and the debugger 41 repeats the read operation of the data register (DR) twice each time until the read operation ends. During this time, the JTAG interface means 51 controls the FM status register 58 and the FM read data register 56 to be read alternately.
[0048]
On the other hand, the JTAG interface means 51 instructs the data bus interface 52 to perform a read operation and the contents of the FM read address register 55. Then, the data bus interface 52 controls the data bus 46 to read the data of the memory cell indicated by the read address of the FM read address register 55, and outputs an operation end signal and read data to the JTAG interface means 51. The JTAG interface means 51 stores information indicating the end of the operation in the FM status register 58, and stores the read data in the FM read data register 56. Then, the debugger obtains operation completion information and read data by reading the FM status register 58 and the FM read data register 56.
[0049]
With this operation, the debugger 41 can access the memory 45 and perform debugging without operating the processor 42.
[0050]
Embodiment 3 FIG.
FIG. 7 is a configuration diagram of a system LSI including an on-chip JTAG interface circuit according to the third embodiment of the present invention. The debugger 61 is a verification environment outside the system LSI 60 in which a verifier directly operates, and includes, for example, a PC and a board. The debugger 61 performs data communication with the on-chip JTAG interface circuit 63 in the system LSI 60 by serial signal input / output conforming to the IEEE1149.1 standard.
[0051]
The on-chip JTAG interface circuit 63 controls the data bus 69 or the system bus 70 in accordance with a command input from the debugger 61 through a serial signal input / output, and switches the system bus signal so that the host processor 62 can control the system bus 70. . The dedicated processing units 66 and 67 are processing blocks that access the memory 68 via the data bus 69 and perform a specific process, and have a plurality of bus registers that can be read and written from the system bus 70. The bus registers include a register for controlling activation and deactivation of the dedicated processing units 66 and 67, a register for storing processing results of the dedicated processing units 66 and 67, and the like. Thereby, the dedicated processing units 66 and 67 can be started or stopped, and the processing results of the dedicated processing units 66 and 67 can be read.
[0052]
The dedicated processor 65 is a processing block for accessing the memory 68 via the data bus 69 and executing arbitrary processing. The dedicated processor 65 includes a plurality of bus registers readable and writable from the system bus 70 like the dedicated processing units 66 and 67. Have. The arbitration circuit 64 receives a bus use request signal from the dedicated processor 65, the dedicated processing units 66 and 67, and the on-chip JTAG interface circuit 63, and if the data bus 69 is not used, uses the data bus 69 next. One of the processing blocks to be selected is selected, a bus use permission signal is output to the processing block, and the data bus 69 is used. The arbitration circuit 64 has a plurality of bus registers readable and writable from the system bus 69 similarly to the dedicated processing units 66 and 67. In the present embodiment, a mechanism of a memory interface that mediates between the memory 68 and the data bus 69 is omitted for simplification.
[0053]
The host processor 62 outputs a reset signal of the dedicated processing units 66 and 67, the dedicated processor 65, and the arbitration circuit 64 to the on-chip JTAG interface circuit 63. The on-chip JTAG interface circuit 63 switches either the reset information instructed from the debugger 61 or the reset signal input from the host processor 62 and outputs it to the dedicated processing units 66 and 67, the dedicated processor 65, and the arbitration circuit 64. I do.
[0054]
Further, the dedicated processing units 66 and 67, the dedicated processor 65, and the arbitration circuit 64 output an interrupt signal or an error notification signal. The interrupt signal or the error notification signal is output to the host processor 62 or the debugger 61 via the on-chip JTAG interface circuit 63.
[0055]
FIG. 8 shows the internal configuration of the on-chip JTAG interface circuit 63. The on-chip JTAG interface circuit 63 includes a JTAG interface unit 81, a system bus interface 83 as a first bus control unit, a bus selection unit 84, a data bus interface 82 as a second bus control unit, a reset selection unit 85, and a stop signal. And generating means 86.
[0056]
The JTAG interface means 81 communicates with the debugger 61 by signal input / output conforming to the IEEE1149.1 standard, and instructs an instruction input from the debugger 61 to the system bus interface 83 or the data bus interface 82. The system bus interface 83 generates a system bus signal 90 according to an instruction from the JTAG interface means 81. The debug mode signal 95 is a signal indicating whether the operation is a normal operation or a debug operation. The bus selecting means 84 connects the system bus signal 71 from the host processor to the system bus 70 when the debug mode signal 95 is normal operation, and connects the system bus signal of the system bus interface 83 when the debug mode signal 95 is debug operation. 90 is connected to the system bus 70.
[0057]
The data bus interface 82 controls the data bus 69 in accordance with an instruction from the JTAG interface means 81 and outputs a result to the JTAG interface means 81.
[0058]
FIG. 9 shows the registers in the JTAG interface means 81. The instruction register (IR) 101 is a register that holds an instruction input from the debugger 61. The IM read address register 102 is a register that holds a read address of the system bus 70. The IM read data register 103 is a register that holds read data of the system bus 70. The IM write register 104 is a register that holds a write address and write data of the system bus 70. The IM status register 105 is a register that holds the end of the operation of the system bus interface 83.
[0059]
The interrupt / error status register 106 is a register that holds the state of the interrupt signal or the error notification signal 94 input from each processing block. The individual reset register 107 is a register that holds reset information input from the debugger 61. The stop cause register 108 is a register for holding stop cause information input from the debugger. The FM read address register 109 is a register for holding a read address of the data bus 69. The FM read data register 110 is a register that holds read data of the data bus 69. The FM write register 111 is a register that holds a write address and write data of the data bus 69. The FM status register 112 is a register that holds the end of the operation of the data bus interface 82.
[0060]
In FIG. 8, the JTAG interface unit 81 includes a TAP controller (not shown) for controlling the shift operation of the registers 101 to 112 in accordance with the input of the TMS signal, and an instruction decoding unit.
[0061]
The reset selection means 85 selects the content of the individual reset register 107 or the reset signal 92 input from the host processor by using the debug mode signal 95 and outputs it as the reset signal 91.
[0062]
The stop signal generating means 86 generates and outputs a stop signal 93 from the contents of the stop cause register 108, the error notification signal and the interrupt signal 94 input from each processing block.
[0063]
FIG. 10 describes the instructions in the instruction register (IR) and the data register (DR) corresponding to each instruction. A double-headed arrow in FIG. 10 indicates that two data registers (DR) are toggled for use. The operation of each instruction is the same as that described in the second and third embodiments, and will not be described.
[0064]
With this configuration, it is possible to control the activation of the dedicated processing unit, read the processing result, reset control, and monitor the interrupt signal or error notification signal from the debugger via the system bus without operating the host processor. In addition, it is possible to access the internal memory from the debugger via the data bus without operating the dedicated processor.
[0065]
In addition, by outputting a stop signal corresponding to an interrupt signal or an error notification signal, debugging can be performed while maintaining the state of a signal at the time of occurrence of an error or an interrupt in a designated processing block.
[0066]
In the first to third embodiments, the on-chip JTAG interface circuit for realizing on-chip debugging using the IEEE1149.1 standard has been described. However, the present invention is not limited to the one using the IEEE1149.1 standard.
[0067]
Although only two dedicated processing units are described in the first to third embodiments, debugging can be performed in a similar manner even when two or more dedicated processing units exist in the system LSI.
[0068]
In the second and third embodiments, the memory is a built-in memory. However, debugging can be performed in the same manner when a memory is connected outside the system LSI.
[0069]
Further, the bus protocol of the system bus according to the first and third embodiments is not particularly limited as long as it can be controlled from only one processing block, and can take an arbitrary method.
[0070]
The bus protocol of the data buses of the second and third embodiments is not particularly limited as long as it can be controlled from a plurality of processing blocks, and can take any method.
[0071]
As for the registers in the JTAG interface means 31 of the first to third embodiments, a bus control register such as a byte enable can be added as appropriate according to the protocol of the system bus and the data bus.
[0072]
【The invention's effect】
As described above, according to the on-chip JTAG interface circuit of the present invention, the debugger can control the system bus or the data bus without operating the processor to access the memory and the register inside the system LSI. Has the effect of shortening the time required for access compared to the conventional method of performing access by operating the software, and also eliminates the need to create software for making the processor access, and has the effect of facilitating debugging. is there.
[0073]
Further, since the on-chip JTAG interface circuit of the present invention can control the reset of each processing block from the debugger, the same reset control is performed by the host processor when debugging is performed by operating only some of the processing blocks. There is no need to create software for performing the above operations, which has the effect of facilitating debugging work.
[0074]
In addition, the on-chip JTAG interface circuit of the present invention can monitor the interrupt and error states of each processing block from the debugger, so that there is no need to create software for causing the host processor to perform the same monitoring. This has the effect of facilitating debugging work.
[0075]
In addition, the on-chip JTAG interface circuit of the present invention can stop a processing block by a designated interrupt signal or error signal. It is possible to refer to the state of the register and the like from the debugger, which has an effect of facilitating debugging work such as analysis of an error cause.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a system LSI according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of an on-chip JTAG interface circuit according to the first embodiment of the present invention.
FIG. 3 is a timing chart showing a write operation of the on-chip JTAG interface circuit according to the first embodiment of the present invention.
FIG. 4 is a timing chart showing a read operation of the on-chip JTAG interface circuit according to the first embodiment of the present invention.
FIG. 5 is a block diagram illustrating a schematic configuration of a system LSI according to a second embodiment of the present invention.
FIG. 6 is a block diagram illustrating a schematic configuration of an on-chip JTAG interface circuit according to a second embodiment of the present invention.
FIG. 7 is a block diagram illustrating a schematic configuration of a system LSI according to a third embodiment of the present invention.
FIG. 8 is a block diagram illustrating a schematic configuration of an on-chip JTAG interface circuit according to a third embodiment of the present invention.
FIG. 9 is a diagram showing a register configuration of a JTAG interface unit according to Embodiment 3 of the present invention.
FIG. 10 is a diagram showing a relationship between an IR instruction and a data register (DR) according to the third embodiment of the present invention.
FIG. 11 is a block diagram showing a schematic configuration of a conventional on-chip JTAG interface circuit.
[Explanation of symbols]
1, 14, 43, 63 On-chip JTAG interface circuit,
2 TAP controller
3 Instruction register (IR)
4 instruction decoding unit,
5 processors,
6 Processor control register
7 scan registers,
10, 40, 60 system LSI,
11, 41, 61 debugger,
12, 62 host processor,
13, 70 system bus,
15, 16, 47, 48, 66, 67 dedicated processing unit,
21,51,81 JTAG interface means
33, 83 system bus interface,
34, 84 bus selection means,
35, 85 reset selection means,
36, 86 stop signal generating means
42 processors,
44, 64 arbitration circuit,
45, 68 memory,
46, 69 data bus
52 data bus interface,
65 dedicated processor,
82 data bus interface,

Claims (10)

A system LSI that includes a processor, a processing unit that performs an arbitrary process, and a data bus, wherein the processor communicates with the processing unit by controlling the data bus;
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
Bus control means for generating a first control signal for the data bus according to an instruction input from the debugger through the JTAG interface means and controlling the data bus;
A second control signal for the data bus input from the processor, and a bus selection unit for selectively switching between the first control signal and the data bus to connect to the data bus;
An on-chip JTAG interface circuit, wherein one of the processor and the debugger controls the data bus to enable communication with the processing unit. The JTAG interface means receives reset information of the processing unit from the debugger through the serial signal input / output and generates a first reset signal according to the reset information.
2. The on-state according to claim 1, further comprising: reset selection means for selectively switching between the second reset signal and the first reset signal of the processing unit input from the processor and outputting to the processing unit. Chip JTAG interface circuit. The JTAG interface means may receive an interrupt signal or an error notification signal output from the processing unit, and read the state of the interrupt signal or the error notification signal from the debugger through the serial signal input / output. The on-chip JTAG interface circuit according to claim 1. The JTAG interface means inputs stop factor information from the debugger through the serial signal input / output,
A stop signal generating unit that generates a stop signal for stopping all of the processing units from the interrupt signal or the error notification signal and the stop factor information,
The on-chip JTAG interface circuit according to claim 3, wherein the stop signal is output to all of the processing units. A processor, a processing unit for performing any processing, a data bus, and an arbitration circuit for selecting one processing block from a plurality of processing blocks including the processor and the processing unit and permitting use of the data bus; In a system LSI including
The processor and the processing unit can control the data bus to access an internal or external memory of the system LSI;
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
Bus control means for generating a control signal for the data bus in accordance with an instruction input from the debugger through the JTAG interface means and controlling the data bus;
An on-chip JTAG interface circuit, wherein the debugger controls the data bus to enable communication with the memory. In a system LSI including a host processor, one or more processing units for performing arbitrary processing, a system bus, a dedicated processor, a data bus, and an arbitration circuit,
The arbitration circuit selects one processing block from a plurality of processing blocks including the dedicated processor and the processing unit and permits use of the data bus,
The host processor communicates with the processing unit by controlling the system bus,
The dedicated processor and the processing unit are capable of controlling the data bus to access an internal or external memory of the system LSI;
JTAG interface means for performing data communication with a debugger external to the system LSI by serial signal input / output,
First bus control means for generating a first control signal for the system bus according to an instruction input from the debugger through the JTAG interface means;
Bus selection means for selectively switching between the second control signal of the system bus input from the host processor and the first control signal and connecting to the system bus;
Second bus control means for generating a control signal for the data bus in accordance with an instruction input from the debugger through the JTAG interface means and controlling the data bus,
Either the host processor or the debugger controls the system bus to enable communication with the processing unit,
An on-chip JTAG interface circuit, wherein the debugger controls the data bus to enable communication with the memory. The JTAG interface means receives reset information of the processing unit from the debugger through the serial signal input / output and generates a first reset signal according to the reset information.
7. The apparatus according to claim 6, further comprising reset selection means for selectively switching between a second reset signal and said first reset signal of said processing unit input from said host processor and outputting to said processing unit. On-chip JTAG interface circuit. The JTAG interface means may receive an interrupt signal or an error notification signal output from the processing unit, and read out the information of the interrupt signal or the error notification signal from the debugger through the serial signal input / output. The on-chip JTAG interface circuit according to claim 6. The JTAG interface means inputs stop factor information from the debugger through the serial signal input / output,
A stop signal generating unit that generates a stop signal for stopping all of the processing units from the interrupt signal or the error notification signal and the stop factor information,
The on-chip JTAG interface circuit according to claim 8, wherein the stop signal is output to the processing unit. An on-chip JTAG interface circuit according to any one of claims 1 to 9, a processor, a processing unit for performing arbitrary processing, an on-chip JTAG interface circuit, a processor, and input and output of signals to and from the processing unit. A system LSI including a bus.

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