JPH0815387A - Microcomputer test circuit - Google Patents

Abstract

PURPOSE:To obtain a microcomputor test circuit in which the I/O port function at a multifunction block can be tested using a same test program by switching the external system bus function and the I/O port function based on a control signal for a plurality of multipurpose blocks. CONSTITUTION:When a test is started by a microcomputor 1, multipurpose blocks 8, 9 exhibit external system bus function and I/O port function, respectively. Address and data are then communicated between an address bus 3 and a data bus 4 through the switching circuit 12 and an allocation switching control circuit 10 for external system bus based on the test program of a test unit 2 thus testing the I/O port function of the block 9. A data for setting the alteration of address is also written into a bus selection register 11 through the circuits 12, 10 and the bus 4 according to same test program. The circuit 10 takes in the data and changes allocation of the address and data on the bus from block 8 to block 9 in order to switch the function thus testing the I/O port function of the block 8 through a bus switching circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides an input / output port function and an external system bus function of a microcomputer such as a single-chip microcomputer (hereinafter referred to as "microcomputer") used for appliances for consumer use, home appliances, industrial use, etc. The present invention relates to a microcomputer test circuit that tests a combined block that is also used.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a conventional microcomputer test circuit. In the figure, 1 is a microcomputer to be tested, 2 is an LSI tester as a test device for performing the test of the microcomputer 1, 3 is an address bus of the microcomputer 1, and 4 is a data bus. Reference numeral 5 is a dual-purpose block arranged in the microcomputer 1 having both an input / output port function and an external system bus function, and 6 is a dual-purpose block 5 in which the dual-purpose block 5 is inserted according to the mode of the microcomputer 1. It is an external system bus switching circuit that switches from the output port function to the external system bus function. Here, the external system bus refers to an address / data bus with an external IC or an address / data bus with the LSI tester 2 at the time of testing, and the external system bus switching circuit 6 is, for example, The dual-purpose block 5 has an external system bus function in the test mode or the microprocessor mode, and has an input / output port function in the single chip mode. Reference numeral 7 is an input / output port block arranged in the microcomputer 1 and having only an input / output port function.

Next, the operation will be described. Here, FIG.
Is a dual-purpose block 5 of the microcomputer 1 configured as shown in FIG.
3 is a flowchart showing a flow of processing when testing the I / O port block 7. When the test starts, the microcomputer 1 enters the test mode in step ST1, and the dual-purpose block 5 functions as an external system bus. As a result, the address and data from the LSI tester 2 which is executing the test program are transferred between the address bus 3 and the data bus 4 of the microcomputer 1 via the external system bus switching circuit 6 of the dual-purpose block 5. As a result of the exchange, the input / output port function of the input / output port block 7 can be tested. However, as it is, it is impossible to test the input / output port function of the dual-purpose block 5. Therefore, in step ST2, the test is temporarily stopped, and in addition to the test of the input / output port function of the input / output port block 7, a test program dedicated to the input / output port function test of the shared block 5 is prepared. Then, in step ST3, the microcomputer 1 is put into the test mode again, and the test program is written in the internal memory (not shown) of the microcomputer 1 from the dual-purpose block 5 having the external system bus function. After that, in step ST4,
The mode of the microcomputer 1 is changed from the test mode to the single chip mode. As a result, the dual-purpose block 5 is switched from the external system bus function to the I / O port function, and the test of the I / O port function of the dual-purpose block 6 operates the test program written in the internal memory of the microcomputer 1 in step ST5. Is carried out.

[0004]

Since the conventional microcomputer test circuit is constructed as described above, in order to test the input / output port function of the dual-purpose block 5, the input / output port block 7 must be tested. It is necessary to prepare a test program separately from the ones to be executed in different modes, and since the test program operates in the internal memory of the microcomputer 1, its contents are output to the outside of the microcomputer 1. In addition, it is difficult to debug the test program, and if the external system bus function of the dual-purpose block 5 is defective, the test cannot be performed.

The inventions set forth in claims 1 to 3 were made in order to solve the above problems, and the input / output of the dual-purpose block can be performed by the same test program without changing the mode of the microcomputer. It is an object of the present invention to obtain a microcomputer test circuit capable of testing a port function and enabling debugging of a test program on an LSI tester.

The invention according to claim 4 further comprises:
Another objective is to obtain a microcomputer test circuit that can be tested even if a problem occurs in the external system bus function of the dual-purpose block.

[0007]

According to a first aspect of the present invention, there is provided a microcomputer test circuit having a plurality of dual-purpose blocks capable of switching between an external system bus function and an input / output port function. The external system bus allocation switching control circuit for controlling the switching of the allocation of the function of 1) on the basis of the input control signal is provided.

According to the second aspect of the present invention, the microcomputer test circuit uses the data set in the external system bus selection register as a control signal for the external system bus allocation switching control circuit.

Further, in the microcomputer test circuit according to the third aspect of the present invention, the input voltage input to the external input terminal is used as the control signal of the external system bus allocation switching control circuit.

According to a fourth aspect of the present invention, in a microcomputer test circuit, a logical operation result of an input voltage input to an external input terminal and a reset signal of the microcomputer is controlled by an external system bus allocation switching control circuit. It is a signal.

[0011]

In the external system bus allocation switching control circuit according to the first aspect of the present invention, the allocation of the function in which a plurality of shared blocks serve as the external system bus function or the input / output port function is allocated based on the control signal given. By switching, it is possible to test the input / output port function of the shared block with the same test program without changing the mode of the microcomputer, and to realize a microcomputer test circuit that can be debugged by an LSI tester.

The external system bus allocation switching control circuit according to the second aspect of the present invention switches the allocation of the function of each dual-purpose block based on the data set in the external system bus selection register, thereby enabling the dual-purpose block. Enables to programmatically change the allocation of functions that become external system bus functions or I / O port functions.

Further, the external system bus allocation switching control circuit in the invention according to claim 3 switches the allocation of the function of the dual-purpose block based on the level of the input voltage of the external input terminal, and thereby the hardware of the microcomputer test circuit is switched. Simplify the hardware configuration.

Further, the external system bus allocation switching control circuit in the invention according to claim 4 switches the allocation of the function of the shared block based on the logical operation result of the input voltage of the external input terminal and the reset signal, Even if a failure occurs in the external system bus function of one shared block, it is possible to perform a test in another shared block.

[0015]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claims 1 and 2. In the figure, 1 is a microcomputer, 2
Is an LSI tester, 3 is an address bus, and 4 is a data bus, which are the same as or equivalent to those of the conventional one denoted by the same reference numeral in FIG. A plurality of (8 in the illustrated case) 8 and 9 are arranged in the microcomputer 1, and each is a dual-purpose block having both an input / output port function and an external system bus function. 1
Reference numeral 0 denotes an external system bus allocation switching control circuit for controlling the switching of allocation of the functions of these dual-purpose blocks 8 to 9 as the external system bus function or the input / output port function, based on a control signal supplied thereto. It is an external system bus selection register in which data serving as a control signal for controlling the switching of the function allocation by the external system bus allocation switching control circuit 10 is stored. The external system bus switching circuits 12 and 13 are arranged in the dual-purpose block 8 or 9 and switch the dual-purpose block 8 or 9 from the input / output port function to the external system bus function according to the mode of the microcomputer 1. The operation is performed only in the shared block 8 or 9 to which the address / data of the external system bus is allocated by the external system bus allocation switching control circuit 10.

Next, the operation will be described. Here, FIG.
Is a dual-purpose block 8 of the microcomputer 1 configured as shown in FIG.
11 is a flowchart showing a flow of processing when testing 9 and 9. In the microcomputer 1, the external system bus allocation switching control circuit 10 normally allocates the external system bus function to the dual function block 8 and the input / output port function to the dual function block 9. Therefore, in step ST11, when the microcomputer 1 enters the test mode and the test starts, the dual-purpose block 8 is switched to the external system bus function, and the dual-purpose block 9 is switched to the input / output port function. By this, LS
Addresses and data based on the test program from the I tester 2 are transferred from the external system bus switching circuit 12 of the shared block 8 to the address bus 3 and the data bus 4 of the microcomputer 1 via the external system bus allocation switching control circuit 10. And the input / output port function of the dual-purpose block 9 is tested.

On the other hand, when the test of the input / output port function of the dual-purpose block 8 is carried out, in step ST12, the microcomputer 1 is kept in the test mode, and the microcomputer 1 is tested by the external system bus selection register 11 by the test program. Specify the address of and send the setting data to change its contents. At this time, since the dual-purpose block 8 has an external system bus function, its setting data is transferred from the external system bus switching circuit 12 of the dual-purpose block 8 to the address of the data bus 4 via the external system bus allocation switching control circuit 10. It is written in the designated external system bus selection register 11 and its contents are changed. Here, for example, the external system bus selection register 11 is composed of 8 bits, and the setting data when the dual function block 8 is assigned to the input / output port function and the dual function block 9 is assigned to the external system bus function is "0".
3 ", the external system bus selection register 1
The content of 1 is changed to "03".

The external system bus allocation switching control circuit 10 fetches the contents of the external system bus selection register 11 in step ST13, and since it is "03", it also serves as the allocation of the address / data of the external system bus. The block 8 is changed to the combined block 9. As a result, the dual-purpose block 8 is switched from the external system bus function to the input / output port function, and the dual-purpose block 9 is switched from the input / output port function to the external system bus function. Therefore, in the same way as in the case of the test of the input / output port function of the dual-purpose block 9 in step ST11, the dual-purpose block is passed through the external system bus switching circuit 13 of the dual-purpose block 9 having the external system bus function. Eight I / O port function tests are performed.

As described above, according to the first embodiment, the allocation of the functions of the dual-purpose block serving as the external system bus function and the input / output port function is programmably changed by rewriting the external system bus selection register 11, and the microcomputer 1 It is possible to test the input / output port functions of the dual-purpose blocks 8 and 9 with the same test program while the mode of No. 2 is set to the test mode, and the contents of the test program are also output to the LSI tester 2. It will be easy.

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing an essential part of an embodiment of the invention described in claim 3. In this embodiment 2, the allocation of functions of the shared blocks 8 and 9 in the external system bus allocation switching control circuit 10 is externally It is controlled not by the setting data of the system bus selection register 11 but by the level of the input voltage of the external input terminal. In the figure, 14 is its external input terminal, and 15 is a buffer for transmitting the input voltage input to this external input terminal 14 to the external system bus allocation switching control circuit 10. The other parts are given the same reference numerals as the corresponding parts in FIG. 1 and their explanations are omitted.

Next, the operation will be described. Here, FIG.
4 is a flow chart showing the flow of processing when testing a dual-purpose block of the microcomputer 1 configured as shown in FIG. Since the basic operation is the same as that of the first embodiment shown in FIG. 2, the description thereof will be omitted here. When carrying out the test of the input / output port function of the dual-purpose block 8, the microcomputer 1 is in the test mode, and the dual-purpose block 8 is set to the external system bus function, and step ST
At 22, the test program temporarily sets a wait state for waiting for input to the external input terminal 14. At that time, the input voltage of the external input terminal 14 is set to a high level (for example, 5
V) to a low level (0 V, for example), the change in the level of the input voltage is used as a control signal in the buffer 1
External system bus allocation switching control circuit 1 via 5
It is transmitted to 0. The external system bus allocation switching control circuit 10 takes in the level of the input voltage of the external input terminal 14 in step ST23, and since it is at the low level (0 V), it also serves as the allocation of the address / data of the external system bus. The block 8 is changed to the combined block 9. As a result, in step ST23, the dual-purpose block 8 is switched from the external system bus function to the input / output port function, and the dual-purpose block 9 is switched from the input / output port function to the external system bus function.
The test of the input / output port function of the dual-purpose block 8 is carried out in the same manner as in the above case.

As described above, according to the second embodiment, even if the hardware such as the external system bus selection register 11 is not separately provided, the input / output of the dual-purpose blocks 8 and 9 depends on the level of the input voltage to the external input terminal 14. The output port function can be tested by the same test program while the microcomputer 1 is in the test mode, and the test program can be easily debugged.

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a configuration diagram showing a main part of an embodiment of the invention described in claim 4, and corresponding parts are denoted by the same reference numerals as those in FIG. 3 and their description is omitted. In the figure, 16 is a reset terminal to which the reset signal of the microcomputer 1 is input, and 17 is a logical operation of the signal input to the reset terminal 16 and the input voltage of the external input terminal 14 from the buffer 15 (this In case of NAND logic operation),
It is a logic circuit that inputs the calculation result to the external system bus allocation switching control circuit 10 as a control signal.

Next, the operation will be described. Here, the microcomputer test circuit according to the third embodiment is based on the level of the input signal of the external input terminal 14 described in the second embodiment.
The allocation of the address / data of the external system bus by the external system bus allocation switching control circuit 10 can be determined when the reset of the microcomputer 1 is released. FIG. 6 is a time chart showing the relationship of the signals of the respective parts at that time. For example, when the reset signal input to the reset terminal 16 changes from low level to high level and the reset of the microcomputer 1 is released, if the level of the input voltage of the external input terminal 14 is high level as shown in the figure, The control signal output from the logic circuit 17 based on the NAND logic becomes low level. The external system bus allocation switching control circuit 10 which receives the control signal output from the logic circuit 17 changes the shared block 8 from the external system bus function to the input / output port function and the shared block 9 in the same manner as in the second embodiment. Switch from the I / O port function to the external system bus function.

As described above, according to the third embodiment, since the allocation of the external system bus can be determined when the reset of the microcomputer 1 is released, even if there is a shared block having a defect in the external system bus function, other It is possible to perform a test using the dual-purpose block.

[0026]

As described above, according to the first aspect of the invention, a plurality of combined blocks capable of switching between the external system bus function and the input / output port function are prepared, and the external system bus allocation switching control circuit is provided. Is configured to control the switching of the allocation of the functions of these dual-purpose blocks based on the control signal, so that a plurality of I / O port functions including the dual-purpose blocks can be tested by the same test program by the microcomputer. It is possible to carry out without changing the mode of, the number of test programs can be reduced, and the debugging of the test programs is facilitated, so that the load of the test program development can be reduced. There is an effect that a microcomputer test circuit can be obtained.

According to the second aspect of the invention, the external system bus allocation switching control circuit controls switching of allocation of the function of the shared block based on the data set in the external system bus selection register. Since it is configured as above, the allocation of the dual-purpose block to be the external system bus function or the input / output port function can be changed in a programmable manner, and the external input terminal for inputting the control signal is not required, so there is a margin in the number of terminals. Even if there is not, there is an effect that it can be implemented.

According to the third aspect of the present invention, the external system bus allocation switching control circuit controls the switching of the allocation of the function of the shared block based on the level of the input voltage of the external input terminal. Because I did
Since there is no need to separately provide hardware such as an external system bus selection register, the hardware configuration can be simplified.

According to the invention of claim 4, the external system bus allocation switching control circuit switches the allocation of the function of the shared block based on the logical operation result of the input voltage of the external input terminal and the reset signal. Since the configuration is such that control is performed, even if a failure occurs in the external system bus function of one shared block, it is possible to switch to another shared block for testing and be effective during failure analysis.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a microcomputer test circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow of the above embodiment.

FIG. 3 is a configuration diagram showing a microcomputer test circuit according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a processing flow of the above embodiment.

FIG. 5 is a configuration diagram showing a microcomputer test circuit according to a third embodiment of the present invention.

FIG. 6 is a time chart for explaining the operation of the above embodiment.

FIG. 7 is a configuration diagram showing a conventional microcomputer test circuit.

FIG. 8 is a flowchart showing the flow of the processing.

[Explanation of symbols]

1 microcomputer, 2 test equipment (LSI tester), 8,
9 dual-purpose block, 10 external system bus allocation switching control circuit, 11 external system bus selection register, 14 external input terminal, 17 logic circuit.

Claims (4)

[Claims] 1. A function of a dual-purpose block having both an external system bus function and an input / output port function is switched according to a mode of a microcomputer, and in the test mode, the external system bus function is selected to be used as an external test device. In a microcomputer test circuit that conducts a test by sending and receiving addresses / data between the plurality of shared blocks, each shared block is provided with an external system bus function or an input / output port function based on a control signal. A microcomputer test circuit, which is provided with an external system bus allocation switching control circuit for controlling switching of allocation of functions to be used. 2. The microcomputer test circuit according to claim 1, further comprising an external system bus selection register in which data as a control signal to the external system bus allocation switching control circuit is set. 3. The microcomputer test circuit according to claim 1, wherein the control signal to the external system bus allocation switching control circuit is an input voltage from an external input terminal. 4. The control signal to the external system bus allocation switching control circuit is a result of logical operation of an input voltage from the external input terminal and a reset signal of the microcomputer by a logic circuit. The microcomputer test circuit according to claim 3.