JP2935710B2 - Test equipment for processor integrated circuit devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a processor integrated circuit device such as a one-chip microcomputer and a digital signal processor (hereinafter referred to as DSP).

2. Description of the Related Art Conventionally, in a processor integrated circuit including a read-only memory (hereinafter, referred to as a ROM) for storing instruction data and operation data, such as a one-chip microcomputer or a DSP, the number of external terminals is large. Therefore, the address bus and the data bus are not connected to the external connection terminals of the integrated circuit, and input / output to / from the address bus and the data bus from outside cannot be performed. Such a processor integrated circuit has, as external terminals, a serial port for communicating with a peripheral device such as a sensor, and a parallel port for communicating with another processor, and a program for controlling the operation of the processor. Instruction data and operation data are generally stored in a built-in ROM.

The following two methods can be considered as a method of testing the chip of the processor integrated circuit.

(1) An external signal close to actual use is created, and a test is performed by executing an application program stored in the ROM. For example, in the case of a processor integrated circuit that performs data processing on a signal from a sensor, a signal actually output from the sensor is created in a simulated manner and input to the processor integrated circuit, and data processing is performed. The test is performed by monitoring whether data processing is performed.

(2) A test program is previously written in a free area of the internal ROM, and the test is executed by executing the test program.

[Problems to be Solved by the Invention] However, since the LSI has many internal buses and operates with internal ROM and RAM like a DSP, an LSI in which these buses are not output to the outside is tested in a normal state. It is extremely difficult. Therefore, a test mode is provided, and a DSP test is performed by switching to the test mode. At this time, it is not possible to see both the state of the signal for setting the data address and the signal for setting the instruction for the DSP in which the data address and the instruction address are separated only by outputting the data bus and the address bus. However, there is a problem that the test is incomplete.

An object of the present invention is to provide a test apparatus that can perform an operation test of a required circuit portion and observe a signal generated on each bus even when a plurality of buses are provided separately as in the above-described DSP. It is in.

[Means for Solving the Problems] A test apparatus for a processor integrated circuit device according to the present invention provides a digital signal processing apparatus in which instructions and data are fetched via different buses, and inputs a signal of each bus to a common input signal during a test. A circuit leading to the output port is provided.

[Embodiment] In the DSP shown in FIG. 1, a program counter which is an address generation unit for instruction fetch, a bus (PC bus) 2 therefor, and an address generation unit 3 for data fetch and therefor Bus (ADDR bus) 4 is completely separated.

In the circuit device shown in FIG. 1, when the test signal is at the L level, the circuit is in the normal operation mode. When the test signal is at the H level, the device is in the test mode. In the test mode, according to which one of the select1 signal and the select2 signal is 1 or 0, as shown in Table 1, a selection is made to output any one of the program counter, the ADDR bus, and the data input bus.

The function circuit 5 transmits and receives input / output signals between the I / O cell 6 and the DSP processing unit 6 in a normal operation mode other than the test mode.

Reference numerals 10 to 19 denote 3-state buffers, respectively. The buffer 10 connects the function circuit 5 and the I / O cell 6 via the buffer 11 by a test signal in the normal operation mode. Buffer 12 is I / O by test signal in test mode
The cell 6 and the PC bus 2 are connected via a buffer 20. Buffers 13 and 14 are connected to PC bus 2 and buffer 11 in test mode.
To the input side of. The buffer 15 connects between the data input bus 21 and the input side of the buffer 11 in the test mode and the selection mode 1. The buffer 16 connects the PC bus 2 and the instruction decoder 30 in the test mode. The buffer 17 connects the program counter 1 and the PC bus 2 in the test mode.

The buffer 18 stores the program counter 1 in the normal operation mode.
And the PC bus 2 are connected.

31 to 36 are AND gates, 37 is an OR gate, and 40 to 43 are inverters. Clock control circuits 45 and 46 output an input signal in synchronization with a clock signal CLK. 47 is a data output buffer.

In the circuit of FIG. 1, the test signal test is one test
It is applied via a signal pin (not shown).

 Next, the operation will be described.

In test mode (test signal = 'H'), clock signal
When clk = “L”, the AND gate 34 generates an output 1 and the buffer 12 is enabled, and the input to the I / O pad 50 of the I / O cell 2 is transmitted through the buffer 12 and the PC bus 2 to the instruction decoder 30.
Therefore, an externally applied instruction is executed.

In the test mode, when the select1 signal is “H” and the clock clk = “H”, the buffers 11, 13, and 15 are enabled, and the signals of the data input bus 21 are changed to the buffers 15, 13, 11
Is output to the I / O pad 50 via the.

When the clock clk signal is 'H' and the select1 signal is 'L', the buffers 14 and 13 are enabled, the buffer 15 is disabled, and the signal on the PC bus 2 is
It is output to the I / O pad 50 via 3.

In addition, test signal is 'H', clock clk is 'H', select2
AND gate 3 when signal is 'H' and select1 signal is 'L'
5 is enabled, the buffer 19 is enabled, and the buffer 14 is enabled, so that the signal of the ADDR bus 4 is transmitted to the I / O through the buffer 19, the PC bus 2, and the buffers 14, 13 and 11.
Output to O pad 50. When the select2 signal becomes "L" in the above, the AND gate 35 and the buffer 19 are disabled (inactive), while the AND gate 36 and the buffer 17 are enabled, respectively, and the output signal of the program counter 1 Applied to the PC bus 2 via
Further, the data is output to the I / O pad 50 via the buffers 14, 13, and 11.

Similarly, when the clock clk = “H”, the signals of the data input bus 21, the program counter 1, and the ADDR bus 4 are output by switching the mode selection signal. Since the signal of the data input bus 21 can take in the output of the data output bus 48 via the latch 46, the signals of all the buses are output to the I / O pad 50 and can be externally observed.

Here, select1 and select2 signals are 2 bits of internal register
By using, the output from any of the buses can be switched during the test by the given command and output to the I / O pad 50 without increasing the number of pins dedicated to the test mode switching.

As shown in FIG. 2, when the clock signal clk is H according to H or L, any one of the data input bus, the program counter and the ADDR bus is selected from the I / O pad 50.
Select and output with 1, select2.

When testing the above DSP, it is necessary to be able to output all the various buses in real time.
Outputting these buses directly becomes difficult in terms of layout as the number of buses increases. Therefore, the present invention solves the above-mentioned problem by sharing one bus in the test mode.

[Effects of the Invention] As described above in detail, according to the present invention, a test circuit of a processor integrated circuit such as a DSP can output signals of all buses inside the processor from one I / O pad. As a result, tests such as DSP can be completely realized in real time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a relationship between a clock signal and I / O. 1 ... program counter, 2 ... PC bus, 3 ... address generation unit, 4 ... ADDR bus, 5 ... function circuit, 6 ... DSP processing unit, 10-19 ... buffer, 20 ... buffer, 21 ... data input bus, 30 ... instruction decoder,
31-36 ... and gate, 37 ... or gate, 40-43 ...
… Inverter, 45, 46, 47… Latch, 48… Data output buffer.

Claims (2)

(57) [Claims] 1. A digital signal processor in which instructions and data are fetched through separate buses is provided with a circuit for guiding a signal of each bus to a common input / output port during a test. Test equipment for processor integrated circuit devices. 2. A test apparatus for a processor integrated circuit device according to claim 1, wherein said circuit for guiding a signal of each bus to a common input / output port at the time of a test comprises: An input / output control means for causing a bus signal to be output to the outside via the input / output port in a time-division manner; and A testing device for a processor integrated circuit device, comprising: selecting means for selecting one of the buses; and signal transmission control means for transmitting a signal of the bus selected by the selecting means to the input / output port. .