JP3074978B2 - Emulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation of an in-circuit emulator for a semiconductor integrated circuit for a specific application (hereinafter, referred to as a cell-based ASIC) which incorporates an arbitrary number of blocks having a specific function in which a mask layout is prepared in advance. More specifically, a first semiconductor integrated circuit (hereinafter, referred to as a CPU macro chip) having a plurality of central processing unit functions and a second semiconductor integrated circuit having a plurality of peripheral circuit functions are provided. The present invention relates to an emulation board having a circuit (hereinafter, referred to as a peripheral macro chip) and enabling connection between both macro chip terminals.

[0002]

2. Description of the Related Art Conventionally, an application-specific semiconductor integrated circuit (hereinafter referred to as an ASIC), particularly a cell-based ASIC, has a central processing unit function as well as a logic circuit block arbitrarily designed by a user on a single semiconductor substrate. Block (hereinafter, CPU
Macros) and peripheral circuit function blocks (hereinafter, referred to as peripheral macros) are built in, so that a user system can be configured. Therefore, a conventional ASIC emulation board will be described with reference to FIG.

FIG. 12 is a block diagram of an emulation board showing an example of the related art. As shown in FIG. 12, a conventional emulation board 10 includes a trace circuit 20.
And the CPU of the central processing unit (CPU) used by the user
An evaluation chip 30, a peripheral IC 40 and a memory 50 are provided, and various buses 32 to 3 are provided therebetween.
4 for connection. Hereinafter, each circuit will be described.

First, a trace circuit 20 receives data from a personal computer or the like via an external interface bus 21 and outputs a control signal based on the data to a trace bus 31. Further, the data obtained through the trace bus 31 is output to the outside through the external interface bus 21.

Next, the CPU evaluation chip 3
Numeral 0 denotes an emulation CPU chip having a built-in circuit that enables a CPU operation in addition to a CPU function. The chip 30 outputs an operation state at the time of instruction execution to the trace bus 31 as a status signal.
The internal bus information of the fetch address bus information for transmitting the memory storage address of the instruction read by U and the fetch data bus information for transmitting the instruction code of the read instruction is output to the outside via the trace bus 31. Moreover, CP
The U evaluation chip 30 is connected to the status bus 32
And the peripheral IC 40 and the memory 50 via the control bus 33 and the address data bus 34.
Note that these buses 32 to 34 are formed on the emulation board 10 by printed wiring or the like.

The status bus 32 transmits an instruction execution cycle of the CPU, a signal indicating a memory space to be accessed by the CPU by an instruction, and an operation state signal of the peripheral IC 40.
Control signals such as a read signal, a write signal, and a chip select signal for C40 are transmitted. Similarly, address data bus 34 transmits an address signal and a data signal for accessing memory 50 and peripheral IC 40.

Next, the peripheral IC 40 is a standard IC having various peripheral circuit functions. It operates by setting data via an address data bus 34 based on a control signal on a control bus 33. Further, a status signal indicating the operation state is always output on the status bus 32. Further, the memory 50 stores a program executed by the CPU evaluation chip 30.

Hereinafter, the operation of the emulation board 10 having such a configuration will be described.

First, an emulation start operation will be described. It is assumed that the trace circuit 20 is connected to a personal computer via the external interface bus 21 in advance. The peripheral IC 40 outputs the specific data indicating the stop state on the status bus 32 in the stop state, and the memory 50 stores a program for activating the peripheral IC 40 after confirming that the peripheral IC 40 is in the stop state. It is assumed that

Next, control data for instructing emulation start is input to the trace circuit 20 from a personal computer. The trace circuit 20 outputs a control signal for causing the CPU evaluation chip 30 to start program execution based on the control data. Therefore,
The CPU evaluation chip 30 outputs an address signal and a control signal according to the control signal, and reads and interprets the instruction code of the program stored in the memory 50 to start the execution operation of the program.

Subsequently, the CPU evaluation chip 30 sequentially executes the program, fetches the data on the status bus 32, and confirms that the peripheral IC 40 is in a stopped state. Next, data for activating the peripheral IC 40 is output onto the address data bus 34, and a control signal is output to the peripheral IC 40 to set data. Thus, the peripheral IC 40 starts operating based on the setting data.

Next, the CPU evaluation chip 3
The trace operation of the program execution of 0 will be described.
Control data instructing a trace operation of the instruction execution of the CPU from the personal computer is input to the trace circuit 20. Thus, the trace circuit 20 outputs the internal fetch address bus information output from the CPU evaluation chip 30 to the personal computer via the external interface bus 21 on the trace bus 31.
Therefore, the operator of the personal computer is
It is possible to obtain the address information of the program currently being executed by the U evaluation chip 30.

Similarly, by outputting the internal fetch data bus information output by the CPU evaluation chip 30 to the personal computer via the external interface bus 21, the CPU evaluation chip 30 executes the program currently being executed. It is possible to obtain instruction code information. That is, the operator can know from the address information and the instruction code information which part of the program the CPU is currently executing.

As described above, the emulation board 10 enables the emulation operation of the user's ASIC system, and also allows the CPU to know which instruction is currently being executed. It is possible to verify the operation of the system.

A typical example of such an ASIC emulation device is a rapid prototyping machine (RPM). The RPM is a kind of a programmable logic array integrated circuit, and uses a large number of arbitrarily programmable field programmable gate arrays (FPGAs) to program the FPGAs based on circuit connection information. Is realized. However, since this RPM uses an FPGA that emphasizes versatility with respect to the circuit configuration, real-time performance is poor and the price is high.

The RPM is a component adapter (a commercially available standard CPU IC) for the CPU IC and peripheral ICs.
And another board on which peripheral ICs and the like are mounted). Therefore, when configuring an emulation device for a cell-based ASIC by RPM, it is necessary to individually create component adapters for various combinations of the CPU macro and the peripheral macro.

[0017]

The above-mentioned conventional ASI
The C emulation board has a specific CPU evaluation chip and a specific peripheral IC, and cannot easily cope with each system configuration by combining various CPU functions and various peripheral circuit functions. It is necessary to create an individual emulation board according to the system configuration of the above, and there is a disadvantage that the period, the man-hour, and the cost are increased.

Further, since the user system cannot be easily changed by the above-described configuration, if the user system is to be changed, there is a drawback that the verification work of software and birdware when a user develops an application device is delayed.

An object of the present invention is to provide an emulation board capable of reducing such a period and man-hours, reducing costs and improving versatility to speed up a verification operation.

[0020]

An emulation device according to the present invention comprises a central processing unit macro chip comprising a plurality of blocks having a central processing unit function and a peripheral macro chip comprising a plurality of blocks having a peripheral circuit function. , and trace circuit for generating a first and a second selection signal for selecting each block of said-out Motozu the data from an external central processing unit microchip and the peripheral macro chip, the central processing unit microchip and The surrounding mac
A connection block for connecting the blocks of the chip, and a memory connected to the connection block ,
The central processing unit macro chip includes a selection circuit for selecting an internal arbitrary block by the first selection signal,
The peripheral macro chip includes a selection circuit for selecting any block within the second selection signal, the connection
A block is connected to a terminal of the central processing unit macro chip.
A first input / output terminal connected to the peripheral macro chip;
And a second input / output terminal connected to the terminal
The first input / output terminal and the second input / output terminal
Are connected by wiring . In addition, the emulation device of the present invention has a plurality of central processing unit functions.
Central processing unit macro chip consisting of blocks and peripheral circuits
Peripheral macro chip consisting of multiple blocks with
And a central processing unit (MAC) based on external data.
Block and peripheral macro chip.
To generate first and second selection signals for selection.
Source circuit, the central processing unit macro chip, and the
A connection for connecting each block of the peripheral macro chip
A connection block, and a memory connected to the connection block.
Wherein the central processing unit macro chip has an internal arbitrary
A selection circuit for selecting a block by the first selection signal
And the peripheral macro chip is an internal arbitrary block.
Is selected by the second selection signal.
The connection block is externally provided via the trace circuit.
Consists of a programmable gate array that can be set,
The mode signal, clock signal and data from the trace circuit
Data specified by the programmable gate array
So that the input / output terminals can be connected arbitrarily.
Be composed.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an emulation board showing a first embodiment of the present invention. As shown in FIG. 1, the emulation board 100 of the present embodiment includes a CPU macro 12 of a plurality of CPU evaluation chips.
By selecting an arbitrary combination from the CPU macro chip 120 incorporating the peripheral macros 1 and 122 and the peripheral macro chip 160 incorporating the peripheral macros 161 and 162 of a plurality of peripheral functions, it is possible to easily cope with various user systems. Is what you do. That is, the emulation board 100 of the present embodiment includes a trace circuit 110, a CPU macro chip 120 containing CPU macros 121 and 122 used by the user, and a peripheral macro chip 160 also containing peripheral macros 161 and 162. The memory 50, the CPU macro chip 120, the peripheral macro chip 1
Buses 123, 131, 132 between the memory 60 and the memory 50
And a jumper block 130 having input / output terminals 140 and 150 built-in.

FIG. 2 is a diagram showing selection designation of a CPU macro chip and peripheral macro chips in FIG. As shown in FIG. 2, here, the macros of the CPU macro chip 120 and the peripheral macro chip 160 are selected by the selection signals 111 and 112 from the trace circuit 110.

Hereinafter, each circuit will be described with reference to FIGS. First, the trace circuit 110 outputs a selection signal 111 to the CPU macro chip 120 based on data input via the external interface bus 21,
The selection signal 112 for the peripheral macro chip 160 is output. As described above, in the present embodiment, the selection signals 111 and 11
2 is different from the conventional example. The bus 31 is the same as in the conventional example.

Next, the CPU macro chip 120 is a CPU
The macro is composed of a macro 121 and a CPU macro 122, selects one macro based on the selection signal 111, and outputs an input / output signal of the selected macro via the bus 123. The bus 123 includes an address data bus, a control bus, and a status bus. For example, as shown in FIG. 2 described above, when the selection signal 111 is “1”, the CPU macro 121 is selected, and when the selection signal 111 is “0”, the CPU macro 122 is selected.

The jumper block 130 includes an input / output terminal 140 and an input / output terminal 150. The input / output terminal 140 includes a plurality of terminals, and each signal terminal of the bus 123 is individually connected. On the other hand, the input / output terminal 150
Is composed of a plurality of terminals, and the signal terminals of the bus 131 and the bus 132 are individually connected. The bus 131 is composed of an address data bus, a control bus and a status bus, while the bus 132 is composed of an address data bus and a control bus.

Further, the peripheral macro chip 160 includes a peripheral macro 161 and a peripheral macro 162, selects one of the peripheral macros based on the selection signal 112, and outputs an input / output signal of the selected peripheral macro to the bus 131.
For example, as shown in FIG. 2, when the selection signal 112 is “1”, the peripheral macro 161 is selected, and when the selection signal 112 is “0”, the peripheral macro 162 is selected.

However, regarding the address data buses of the bus 131 and the bus 132, when the CPU accesses the normal memory 50 and the peripheral macro chip 160, it may be shared because the access is performed based on a specific address or an individual control signal. It is possible.

The emulation operation of the emulation board 100 in this embodiment is basically the same as that of the conventional example, except for the selection operation of the CPU macro chip 120 and the peripheral macro chip 160 and the connection of the jumper block 130. Therefore, referring to FIGS. 3 to 7 below, the CPU macro chip 120, the peripheral macro chip 16
The detailed configuration of the 0 and the jumper block 130 and the like and the respective selection operations will be described.

FIG. 3 is a configuration diagram of the CPU macro chip shown in FIG. As shown in FIG. 3, the CPU macro chip 120 includes a CPU macro 121 and a CPU macro 122.
And selection circuits 310, 320, 330, and 340. First, the selection circuit 310 connects the status bus of the bus 123 to the status bus 311 or the status bus 312 based on the selection signal 111. The selection circuit 320 connects the control bus of the bus 123 to the control bus 321 or 322 based on the selection signal 111. Further, the selection circuit 330 changes the address data bus of the bus 123 to the address data bus 331 or the address data bus 3 based on the selection signal 111.
32.

On the other hand, the selection circuit 340 connects the trace bus 31 to the trace bus 341 or the trace bus 342 based on the selection signal 111. Since the selection circuit 340 has the same configuration as the selection circuit 330 described above, the description is omitted.

FIGS. 4A to 4C are block diagrams of the selection circuit shown in FIG. Here, a 1-bit configuration is shown for convenience. As shown in FIG. 4A, the selection circuit 310 includes AND circuits 410 and 411 and an inverter 4
12. That is, the selection signal 111
Is "1", the output of the inverter 412 becomes "0",
An input signal from the bus 123 of the AND circuit 410 is output as a 1-bit status signal on the status bus 311.

Further, as shown in FIG.
20 is an AND circuit 420, 421 and an OR circuit 423
And an inverter 424. in this case,
When the selection signal 111 is “1”, the OR circuit 420 outputs a 1-bit signal of the control bus 321. on the other hand,
Since the output of the inverter 424 is “0”, the output of the AND circuit 421 is “0”. Therefore, the output signal of the OR circuit 423 to the bus 123 is transmitted to the control bus 32
This is a 1-bit signal.

Next, as shown in FIG. 4C, the selection circuit 330 includes two-way transfer gates 430 and 431,
Inverters 432, 433, and 434 are provided. In this case, when the selection signal 111 is “1”, the output of the inverter 433 becomes “0”, so that the transfer gate 430 becomes conductive. Conversely, the output of the inverter 432 becomes “0” and the output of the inverter 434 becomes “1”, so that the transfer gate 431 is turned off. Therefore, the 1-bit signal of the bidirectional address data bus 331 becomes the 1-bit signal of the address data bus of the bus 123.

The selection circuit 340 outputs the selection signal 111
Is "1", the 1-bit signal on the trace bus 341 and the 1-bit signal on the trace bus 31 are connected. When the selection signal 111 is “0”, the 1-bit signal on the trace bus 342 and the 1-bit signal on the trace bus 31 are connected.

Next, the selection circuits 310, 320,
The selection operation of the CPU macro chip 120 using 330 and 340 will be described assuming that the selection signal 111 is “1”. That is, since the selection signal 111 is “1”, the selection circuit 310 connects the status bus of the bus 123 to the stator bus 311, and the selection circuit 320
3 is connected to the control bus 321, and the selection circuit 330 connects the address data bus of the bus 123 to the address data bus 331, and the selection circuit 340 is connected.
Connects the trace bus 31 to the trace bus 341.
Therefore, when the selection signal 111 is “1”, the CPU macro 121 is selected, and the internal bus is connected to the input / output terminal 140 via the bus 123. The internal trace bus is connected to the trace circuit 110 via the trace bus 31. The above is the selection operation of the CPU macro chip 120.

FIG. 5 is a configuration diagram of the peripheral macro chip shown in FIG. As shown in FIG.
Is the peripheral macro 161, the peripheral macro 162, and the selection circuit 5
10, 520 and 530. Selection circuit 5
10 connects the address data bus of the bus 131 to the address data bus 511 or 512 based on the selection signal 112. The selection circuit 520 connects the stator bus of the bus 131 to the stator bus 521 or the stator bus 522 based on the selection signal 112. Further, the selection circuit 530 connects the control bus of the bus 131 to the control bus 531 or the control bus 532 based on the selection signal 112.

FIGS. 6A to 6C are block diagrams of the selection circuit shown in FIG. Here, a 1-bit configuration is shown for convenience. First, as shown in FIG.
The selection circuit 510 includes bidirectional transfer gates 610 and 6
11 and inverters 612, 613, and 614. When the selection signal 112 is “1”, the inverter 6
Since the output of No. 12 becomes "0", the transfer gate 610 is turned on. Further, since the output of the inverter 614 becomes “0” and the output of the inverter 613 becomes “1”, the transfer gate 611 is turned off. Accordingly, one of the bidirectional address data buses 511
The bit signal is connected to the 1-bit signal of the address data bus of the bus 131.

As shown in FIG. 6B, the selection circuit 520 includes AND circuits 620 and 621 and an OR circuit 62.
3 and an inverter 622. When the selection signal 112 is “1”, the AND circuit 620 outputs a 1-bit signal of the status bus 521. Further, since the output of the inverter 622 is “0”, the output of the AND circuit 621 is “0”. Therefore, the output signal of the OR circuit 623 becomes a 1-bit signal of the status bus 521, and is connected to the 1-bit status signal of the bus 131.

Further, as shown in FIG. 6C, the selection circuit 530 includes AND circuits 630 and 631 and an inverter 6
32. Again, the selection signal 112
Is "1", the output of the inverter 632 is "0", so that the input signal from the bus 131 of the AND circuit 630 is output as a 1-bit control signal of the control bus 531.

Next, the selection operation of the peripheral macro chip 160 will be described assuming that the selection signal 112 is "1". That is, since the selection signal 112 is “1”, the selection circuit 510 connects the address data bus of the bus 131 to the address data bus 511, and the selection circuit 520 connects the status bus of the bus 131 to the status bus 521, and selects The circuit 530 connects the control bus of the bus 131 to the control bus 531. Accordingly, when the selection signal becomes “1”, the peripheral macro 161 is selected, and the internal bus is connected to the input / output terminal 1 via the bus 131.
50. The above is the operation of selecting the peripheral macro chip 160.

FIG. 7 is a diagram showing connections between jumper block terminals in FIG. As shown in FIG. 7, the jumper block 130 includes input / output terminals 140 and 150,
This is a wiring block for connecting the bus 123 and the buses 131 and 132. Accordingly, signals corresponding to the address data bus, the stator bus, and the control bus are output to the input / output terminal 140 and the input / output terminal 150, and these signal terminals are connected by wiring such as wrapping.

In short, the present embodiment is versatile because an emulation board can be configured by selecting a CPU macro and a peripheral macro necessary for a system configuration from a CPU macro chip and a peripheral macro chip by designating a selection signal. Therefore, one kind of emulation board can support various combinations of CPU macros and peripheral macros. Even if the system configuration is changed in the middle, it is possible to easily cope with the changed system configuration only by specifying the CPU macro and the peripheral macro by the selection signal and changing the wiring of the jumper block.

The circuit configuration and semiconductor process of each CPU macro and peripheral macro in the above-described CPU macro chip and peripheral macro chip can be made exactly the same as those of the actual product. Electrical characteristics between the circuit and the actual semiconductor integrated circuit can be made the same, and real-time performance can be improved.

FIG. 8 is a block diagram of an emulation board showing a second embodiment of the present invention. As shown in FIG. 8, the present embodiment incorporates a storage element capable of externally setting the jumper block 130 in the above-described first embodiment of FIG. 1, and connects input / output terminals based on data of the storage element. It is constituted by a programmable logic array integrated circuit (programmable gate array) 820 that can be specified. Such a programmable gate array 820
By setting data from the outside, the terminals of the CPU macro chip 120 and the peripheral macro chip 160 can be connected. However, the connection between the CPU macro and the peripheral macro requires the connection of the input terminal, the output terminal, and the input / output terminal.
The connection of the input terminal, output terminal, and input / output terminal using 0 will be described below.

The emulation board 100 of the present embodiment shown in FIG. 8 is different from the first embodiment in that a trace circuit 810 is provided.
And the mode signal 811, the clock signal 812, the data signal 813, and the programmable gate array 820, the description of other identical components will be omitted. The trace circuit 810 selects the selection signals 111 and 11
2, a mode signal 811, a clock signal 812, and a data signal 813 are output based on data set via the external interface bus 21. These signals 8
Programmable gate array 8 for inputting 11 to 813
20 connects the bus 131 and the bus 123 to the bus 132 and the bus 123. Here, the programmable gate array 820 is not special, and a general FPGA or the like in recent years may be used.

FIG. 9 is a block diagram of the programmable gate array shown in FIG. As shown in FIG. 9, the programmable gate array 820 is provided with a mode signal 8 for convenience.
11 is described as 3 bits. This programmable gate array 820 has input / output terminals 901, 903, 90
4 and the control terminal 902 and the SRAM 910
912, input / output blocks 920, 930, 940,
And a combination circuit block 950.

First, the SRAMs 910 to 912 output the clock signal 812 when the mode signals 905 to 907 are "1".
Fetches and stores data signal 813 in synchronization with the rising edge of. The stored values are output signals 915 to 917, respectively.
Is output as The combinational circuit block 950 includes AND circuits 953 and 954, an OR circuit 952 and an inverter 951. This block 95
0 outputs to the input / output block 920 by combining the outputs of the input / output blocks 930 and 940.

On the other hand, the input / output block 920 comprises an output buffer 921, an input buffer 922, and an AND circuit 923. The output buffer 921 outputs an input signal to the input / output terminal 901 when the output of the logic circuit 923 is “1”. The input / output block 930 includes an output buffer 932, an input buffer 931 and an AND circuit 9
The output buffer 932 outputs an input signal when the output of the AND circuit 933 is “1”. Similarly, the input / output block 940 includes an output buffer 942, an input buffer 941, and an AND circuit 943.
An input signal is output at the time of 1 ". Hereinafter, the connection operation between the terminals of the programmable gate array 820 will be described. Here, for convenience, the input / output terminal 901 is focused on, and the input / output terminal 901 is easily replaced with the input / output terminal 903 and the input / output terminal 903. Input / output terminal 9
The connection to the connection 04 will be described with reference to FIGS. 10 and 11.

FIG. 10 is a timing chart of the mode setting of the programmable gate array in FIG. 9, and FIG. 11 is a diagram showing the connection of the input / output terminals to the SRAM set values in FIG. As shown in FIGS. 10 and 11, the mode setting operation and the terminal connection operation of the programmable gate array 820 will be described here. In particular, the input / output terminal 901 is connected to each of the input signals of the bus 131 in FIG.
Bit terminal, an input / output terminal 903 and an output terminal 90
Reference numeral 4 denotes a 1-bit terminal for an output signal of the bus 123 in FIG.

First, the input / output terminal 901 and the input / output terminal 90
Regarding the connection of No. 3, the connection in the case where the input / output terminal 901 becomes the input terminal will be described. At this time, it is assumed that the control signal "1" is input to the control signal terminal 902. The SRAMs 910 to 912 synchronize the data signal 813 with the rising edge of the clock signal 812 when the mode signals 905 to 907 are “1” as shown in FIG.
Capture and store. Therefore, the SRAMs 910 to 912
Are set to “1, 1, 0”, respectively, and the output signals 915 to 9
17 is "1, 1, 0".

However, since the control signal is "1", the output of the inverter 951 becomes "0". Therefore, the output of the AND circuit 923 becomes “0”, and the output buffer 921 turns off. Also, the control signal is “
Since the output signal 916 is "1" at "1", the output of the AND circuit 933 becomes "1" and the input / output buffer 932 is turned on, so that the input / output terminal 901 becomes an input terminal and the input / output terminal 903 becomes Connected as output terminal.

Next, connection when the input / output terminal 901 is an output terminal will be described. At this time, it is assumed that the control signal “0” has been input to the control signal terminal 902. Since the SRAM setting operation and the setting value are the same as those described above, the description will be omitted. In this case, since the control signal is “0”, the output of the inverter 951 becomes “1”. Also, the output signal 915
Is “1”, the output of the AND circuit 923 is “1”.
And the output buffer 921 is turned on. Moreover, since the control signal is “0”, the AND circuit 933 is used.
Is "0", and the input / output buffer 932 is turned off. Therefore, the input / output terminal 901 becomes an output terminal, and the input / output terminal 903 is connected as an input terminal.

Next, the connection when the input / output terminal 901 becomes the input / output terminal will be described. Note that the SRAM setting operation, set value and input operation, and output operation are the same as those described above, and a description thereof will be omitted. First, the input / output terminal 901
Is a composite operation of the operations of the input terminal and the output terminal described above. That is, the input / output direction is switched by a control signal, thereby operating as an input / output terminal. Therefore, the input / output terminal 901 is connected to the input / output terminal 903 as an input / output terminal.

The input / output terminals 901 and 904
Are connected to the input / output terminal 901 and the input / output terminal 90.
The description is omitted because it is the same as the connection of No. 3.

Next, as shown in FIG.
By changing 0 to 912 to “1, 0, 1”, the input / output terminal 901 is connected to the output terminal 904, and operates as an input terminal, an output terminal, and an input / output terminal based on a control signal. That is, any input / output terminal can be connected to any input / output terminal based on the set value in the SRAM, and the input / output direction can be switched by a control signal.

In short, in this embodiment, the programmable gate array 820 only sets data in the SRAM and
Bus 123 between PU macro chip and peripheral macro chip
Since any terminals of the bus 131 and the bus 132 can be connected, the terminal is versatile and the connection terminals can be easily changed. Note that the programmable gate array 820 has a TTL
It is also possible to realize by a logic element such as.

[0058]

As described above, the emulation device of the present invention comprises a trace circuit for generating a plurality of selection signals, a CPU macro chip having a plurality of CPU macros, and a peripheral macro chip having a plurality of peripheral macros. , C
A connection block having a first input / output terminal connected to a terminal of the PU macro chip and a second input / output terminal connected to a terminal of a peripheral macro chip; By selecting an arbitrary CPU macro and selecting an arbitrary peripheral macro in a peripheral macro chip by a second selection signal, while connecting a first input / output terminal and a second input / output terminal in a connection block, (1) A single type of board can be adapted to various user systems, and the effect of reducing the time, man-hours, and cost of creating a board can be obtained.

Also, according to the present invention, a connection block is constituted by a programmable gate array for designating connection of input / output terminals based on the storage contents of a storage element which can be set from the outside, so that a mode signal, a clock signal, and a data signal can be obtained. Based on this, specific contents are stored in the storage elements of the programmable gate array based on which the input / output terminals can be arbitrarily connected, so that the versatility can be improved.

Therefore, according to the present invention, an emulation board capable of flexibly coping with various user system configurations of a cell-based ASIC can be configured, and at the same time, a change in the system configuration can be easily coped with by the same emulation board. It is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of an emulation board showing a first embodiment of the present invention.

FIG. 2 is a diagram showing selection designation of a central processing unit macro chip and peripheral macro chips in FIG. 1;

FIG. 3 is a configuration diagram of a central processing unit macro chip shown in FIG. 1;

FIG. 4 is a diagram illustrating three selection circuits shown in FIG. 3;

FIG. 5 is a configuration diagram of a peripheral macro chip shown in FIG. 1;

FIG. 6 is a diagram illustrating three selection circuits shown in FIG. 5;

FIG. 7 is a diagram illustrating connection between terminals of a jumper block in FIG. 1;

FIG. 8 is a block diagram of an emulation board showing a second embodiment of the present invention.

9 is a circuit diagram of the programmable gate array shown in FIG.

10 is a mode setting timing chart of the programmable gate array in FIG. 9;

FIG. 11 is a diagram illustrating connection of input / output terminals with respect to an SRAM set value in FIG. 9;

FIG. 12 is a block diagram of an emulation board showing an example of the related art.

[Explanation of symbols]

Reference Signs List 50 memory 100 emulation board 110,810 trace circuit 111,112 selection signal 120 central processing unit macro chip 121,122 central processing unit macro 130 jumper block 140,150 input / output terminal 160 peripheral macro chip 161,162 peripheral macro 310,320, 330, 340, 510, 520, 5
30 selection circuit 820 programmable gate array 910-912 SRAM 920, 930, 940 input / output block 950 combination circuit block

Claims (2)

(57) [Claims] A central processing unit macro chip including a plurality of blocks having a central processing unit function; a peripheral macro chip including a plurality of blocks having a peripheral circuit function;
And trace circuit for generating a first and a second selection signal for selecting the blocks of said central processing unit microchip and the peripheral macro tip-out Motozu the data from the outside, the central processing unit microchip and the Surrounding Ma
A connection block for connecting the blocks of the black chip; and a memory connected to the connection block , wherein the central processing unit macro chip selects any internal block by the first selection signal. Circuit, wherein the peripheral macro chip includes a selection circuit for selecting an internal arbitrary block by the second selection signal ,
A connection block is located at an end of the central processing unit macro chip.
A first input / output terminal connected to the
And a second input / output terminal connected to the terminal of the
Both the first input / output terminal and the second input / output
An emulation device characterized in that terminals are connected by wiring . 2. A plurality of blocks having a central processing unit function.
Central processing unit macro chip with peripheral circuits and peripheral circuit functions
A peripheral macro chip composed of a plurality of blocks having
The central processing unit macro chip based on external data
And select each block of the peripheral macro chip
For generating first and second selection signals for
And the central processing unit macro chip and the peripheral
Connection block for connecting each block of the black chip
And a memory connected to the connection block.
In addition, the central processing unit macro chip is provided with an arbitrary block inside.
A selection circuit for selecting a block by the first selection signal.
In addition, the peripheral macro chip precedes any internal block.
A selecting circuit for selecting the second selecting signal;
Connection block is externally set via the trace circuit
And a programmable gate array.
Mode signal, clock signal and data from source circuit
Signals specific to the programmable gate array
It is characterized by storing the contents and connecting the input / output terminals arbitrarily
Emulation device to.