JPH03167682A - Microcomputer - Google Patents

Abstract

PURPOSE:To omit a combination circuit of basic logic gate cells of users at connection secured between a CPU core and a peripheral function block by providing an address/data dividing circuit of a multiplexed bus into the CPU core. CONSTITUTION:When a CPU core 1 confirms the read of the external data on a CPU, the read cycle of an external bus interface is started. Then the higher and lower rank addresses are outputted to a higher rank address bus 4 and a multiplexed bus 5 respectively. At the same time, the address strobe signals 9 are simultaneously outputted to both buses. When an address/data dividing circuit 3 receives the signal 9, the circuit 3 latches the lower rank address value on the bus 5 and outputs it via a lower rank address bus 6. When the write of data is confirmed at the outside of the CPU, the write cycle of an external bus interface is started. Then the write data is outputted to the bus 5 together with a write signal 8 in the same way and written into the registers designated by the higher and lower rank addresses by means of a peripheral function macro 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microcomputer, and in particular, to a microcomputer, in particular a central processing unit (hereinafter referred to as CPU), a functional block including a variety of peripheral hardware, a memory block, and a user-defined circuit. A microcomputer is developed by connecting each layout data of the function 7 locks to be omitted on a computer.

[Conventional technology]

In recent years, with the progress of semiconductor technology, the field of application of microcomputers is rapidly expanding, and the requirements for each field of application are becoming increasingly diverse. A production system for designing and commercializing semiconductor integrated circuits such as microcomputers in a short period of time that completely satisfies user requirements has currently been developed as a gate array, and has already achieved great results.

Furthermore, a new method called the megacell method has been developed as a method having high functionality and high degree of integration. In this method, the layout information of each functional block such as the CPU, memory, timer, serial interface, etc. is registered as a library in the computer as a database called macro information, and the connection diagram of this macro information created by the user is used. The final mask information is created by connecting these macro information in a computer.

In a microcomputer developed based on the method described above, the CPU block interfaces with blocks outside the CPU such as memory blocks, peripheral device function blocks, and external devices (hereinafter referred to as external bus interface function). It has a function for Recently, however, this external bus interface function has often taken the form of a multiplexed bus in which addresses/data are controlled in a time-division manner. The reason for this is that CPUs that have recently been commercialized have adopted the form of a multi-breasted bus in order to reduce the bus width inside the chip in order to reduce the chip area, and to make effective use of external terminals. In many cases, the CPU blocks prepared by IC manufacturers for development using the megacell method described above are
This is because they are often developed based on a database of CPUs with architectures conventionally developed by C manufacturers.

The connection between a CPU block having a conventional multiplexed bus and a peripheral device usually involves a circuit that divides the address/data path using an address strobe signal.

Hereinafter, an example of the connection between a CPU block having a conventional multi-text bus and peripheral function blocks will be explained with reference to FIG.

FIG. 7 is a block diagram of a conventional microcomputer. In FIG. 7, the CPU block is called a CPU core 1, and the peripheral function block is called a peripheral function macro 2, and they are connected to each other. Other peripheral function blocks, memory blocks, and user circuit blocks constituting this microcomputer are not shown.

CP tJ core 1 has a separate upper address bus 4
, and a multi-block bussler that controls the lower address bus and data path in a time-division manner as an interface function. Also multi-breasted bus 5 is CP
Address strobe signal 9 and read signal 7 for use by dividing into address and data outside of U core 1
, and has an output terminal for a write signal 8. The address/data division circuit 3 is a circuit that divides the address/data on the multiplex bus 5. The address/data division circuit 3 is a circuit that divides the address/data on the multiplex bus 5, and latches the lower address outputted onto the multiplex bus 6 by the address strobe signal 9. It has the function of outputting the lower address.

The peripheral function macro 2 is a core that is accessed by a divided address/data bus: an upper address bus 4, a lower address bus 6, a data bus 5, a read signal 7, and a write signal 8, and is accessed from the CPU core 1 at a predetermined timing. accessed with

Furthermore, this peripheral function macro 2 has an address decoder built into the core, so there is no need to input chip select signals or the like from the outside.

As mentioned above, in conventional microcomputers, when the user connects the CPU core and peripheral function blocks prepared in advance by the IC manufacturer, the CPU core only has an address/data multiplex bus. When connecting a peripheral function macro having a separate bus, it was necessary for the user to design an address/data division circuit.

[Problem to be solved by the invention]

As mentioned above, in microcomputers designed using the conventional megacell method, when connecting the CPU core and peripheral function macros, it is necessary to include a circuit for dividing the address/data on the address/data multi-text bus. The user had to design it.

Therefore, even though the megacells of the CPU core and peripheral function macros are connected, the circuit designed by ESA is interposed between them, increasing the burden of circuit design on the user and creating a circuit diagram using a circuit diagram editor. There was a drawback that input was complicated.

In addition, when composing the layout data of each block in the microcomputer on a computer and automatically wiring it,
The address/data division circuit is included in a functional block designed by another user, and the address/data division circuit is placed far away from the CPU core and peripheral function macros on the chip, resulting in a problem with microcomputer operation. Problems may occur, and even if only the address/data division circuit is placed in a predetermined position, special data processing is required on the computer.

An object of the present invention is to provide a microcomputer that can be laid out without special data processing and that can be easily connected to peripheral function blocks having various interface function types. be.

[Means to solve the problem]

The microcomputer of the present invention is a microcomputer in which a CPU block having a central processing unit and a functional block having peripheral device functions are integrated on a single semiconductor substrate, wherein the cPU block is a multiplex block to which addresses and data are supplied. a base, circuit means connected to the multiplex bus and latching the address in response to a strobe signal from the central processing unit; a first circuit means for outputting the address latched by the circuit means to the functional block; and a second terminal for time-divisionally inputting and outputting data and addresses between the multiplex bus and the functional block.

〔Example〕

Next, a first embodiment of the present invention will be described using FIGS. 1, 2, and 3.

FIG. 1 is a block diagram of a t:me microcomputer illustrating a first embodiment of the present invention. Also in this embodiment, only the connection between the CPU core 1 and the peripheral function macro 2 is described. Peripheral function macro 2 has the same functions as the conventional example. Further, the CPU core 1 has the same functions as the conventional CPU core 1, but has an address/data division circuit 3 built into the CPU core 1. The functions and operations of each structural element are the same as those of the conventional example.

The CPU core 1 in this embodiment has three buses as external bus interface functions: an upper address bus 4, a multi-breasted bus that controls lower addresses and data in a time-sharing manner, and a lower address bus 6, which are used as peripheral function macros. There is no single address/data division circuit.

Next, the operation when reading data from the register in the peripheral function macro 2 from the CUP core 1 will be explained with reference to FIG. FIG. 2 is a timing diagram when the CPU core 1 reads the register in the peripheral function macro 2. When the CPU core 1 confirms data read from outside the CPU by executing an instruction, it starts a read cycle of the external bus interface.

In the read cycle of the CPU core 1, first the upper address is output to the upper address bus 4, the lower address is output to the multiplex bus 5, and the address strobe signal 9 is output.
output at the same time. When the address/data division circuit 3 receives the address strobe signal 9, it latches the lower address value on the multi-text bus 5 and directly outputs the latched address value to the lower address bus 6. After that, CPU core 1 outputs read signal 7 low.
active). When the peripheral function macro 2 receives the read signal 7, it outputs the contents of the register specified by the upper address and the lower address to the multiplex bussler.

Next, the operation when writing data from the CPU core 1 to the register in the peripheral function macro 2 will be explained using FIG. 3. Figure 3 shows a timing diagram when CPU core 1 writes data to the register in peripheral function macro 2.
This is what I did. CPU core 1 activates the CPU by executing instructions.
When data write to the outside is recognized, a write cycle of the external bus interface is started. In the write cycle of the CPU core 1, first, an upper address is output to the upper address bus 4, a lower address is output to the multi-text bus 5, and an address strobe signal 9 is output. Address/data division circuit 3 receives address strobe signal 9
When it receives, it latches the lower address on the multiplex bus 6 and outputs the latched address to the lower address bus 6. CPU core 1 then sends the write data to the multi-text bussler using write signal 8.
(low active). When the peripheral function macro 2 receives the write signal 8, it writes the write data on the multiplex bus into the register specified by the upper address and the lower address.

As explained above, in this embodiment, the interface operation of the peripheral function macro will be described in the case where the CPU core 1 has an upper address bus, a multiplex bus for lower addresses and data, and a lower address bus.・The bus router only has the function of a data path, but if other peripheral function macros etc. have a multi-text bus interface function, it functions as an address/data path and can be easily connected to C
Needless to say, it can be connected to PU Core 1. Therefore, whether the peripheral function block connected to the CPU core 1 is a multi-block address/data bus or a separate address/data bus, it can be easily connected to the CPU core 1 without any user circuitry. You will be able to connect with

Next, a second embodiment of the present invention will be explained using FIGS. 4, 5, and 6. FIG. 4 is a block diagram of a microcomputer in a second embodiment of the invention. In the microcomputer in this embodiment, a CPU core 1 and a peripheral function macro 2 are connected, as in the first embodiment. The CPU core 1 in this embodiment has an expanded data path width compared to the CPLI core 1 in the first embodiment, and all bits of the upper address bus, lower address bus, and data path are multiplexed. It is. Further, the peripheral function macro 2 and the address/data division circuit 3 built into the CPU core 1 also match the address bus width and data path width of the CPU core 1.

The CPU core 1 in this embodiment has an address bus 10 dedicated to addresses as an external bus interface function,
It has both types of buses, including a multiplex bus 5 that controls addresses and data in a time-division manner.

Next, the register access operation in the peripheral function macro 2 using the interface function of the CPU core 1 will be described. First, the operation when reading the data of the register in the peripheral function macro 2 from the CPU core 1 will be explained using FIG. FIG. 5 shows a timing diagram when the CUP core 1 reads the register in the peripheral function macro 2. When the CPU core l recognizes data read from outside the CPU by executing an instruction, it starts a read cycle of the external bus interface. In the read cycle of the CPU core 1, an address is first output to the multiplex bus 5, and at the same time, an address strobe signal 9 is output. Address/data division circuit 3 receives address strobe signal 9
When it receives, it latches the address value on the multiplex bus 5 and outputs the latched address value to the address bus 10. The CPU core 1 then outputs a read signal 7 (low active). When peripheral function macro 2 receives read signal 7, address bus 10
The contents of the register addressed by are output to the multi-text bus 5.

Next, the operation when writing data from the CPU core 1 to the register in the peripheral function macro 2 will be explained using FIG. FIG. 6 shows a timing diagram when the CPLJ core 1 writes data to a register in the peripheral function macro 2. By executing instructions, CPU core 1
When data write to the outside is recognized, a write cycle of the external bus interface is started. In the write cycle of CPU core 1, the address is first output to the multiplex I~ bus controller, and at the same time, the address strobe signal 9 is output.
Output. When the address/data division circuit 3 receives the address strobe signal 9, it latches the address value on the multi-text bus and outputs the latched address value to the address bus 10. And CPU core 1 is
Thereafter, the write data is output to the multiplex bus 5 and a write signal 8 (low active) is output. When the peripheral function macro 2 receives the write signal 8, it writes the data on the multi-text bus to the register designated by the address bus 10.

In this embodiment explained above, the multi-text
Although Basra only has the function of a data path,
It goes without saying that even if other peripheral function macros have a multi-text bus interface function, they can be easily connected to the CPU core 1. Therefore, C.P.
Peripheral function blocks connected to the U core 1 can be easily connected to the CPU core 1 without the intervention of user circuits, whether using an address/data multiplex bus or a separate address/data bus. ．． [Effects of the Invention] As described above, the microcomputer of the present invention uses C
By incorporating a multiplex bus address/data division circuit in the PU core, the CPU core and peripheral function blocks can be connected without intervening a user's basic logic gate cell combination circuit.

Furthermore, when automatically wiring the layout data of each macro in this microcomputer on a computer by synthesizing it, the address/data division circuit is built into the CPU core, so no special data processing is required. , the effect is that an optimized layout can be performed.

Furthermore, since this CPU core has an address-only bus and an address/data multiplex bus,
This has the advantage that peripheral function blocks with various interface function forms can be connected as is, and when multiple peripheral function blocks are connected, there is no need to add an address/data frequency divider circuit to each peripheral function block. There is also.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the first embodiment of the present invention, FIG. 2 is a timing chart when reading a peripheral function macro in the microcomputer shown in FIG. 1, and FIG. 3 is a diagram similar to the one shown in FIG. FIG. 4 is a block diagram for explaining the second embodiment of the present invention, and FIG. 5 shows peripheral functions in the microcomputer shown in FIG. 4. Timing chart diagram when reading a macro,
Figure 6 is a timing chart when writing the peripheral function macro in the microcomputer shown in Figure 4;
The figure is a block diagram of a conventional microcomputer. 1...CtJP core, 2...peripheral function macro, 3...
Address/data division circuit, 4... Upper address bus, 5... Multiplex bus, 6... Lower address bus, 7... Read signal line, 8... Write signal line, 9...・Address strobe signal line, 10...address bus.

Claims (1)

[Scope of Claims] 1. In a microcomputer in which a CPU block having a central processing unit and a functional block having peripheral device functions are integrated on a single semiconductor substrate, the CPU block is a multiplexer to which addresses and data are supplied. a second base, circuit means connected to the multiplex bus and latching the address in response to a strobe signal from the central processing unit, and a circuit means for outputting the address latched by the circuit means to the functional block. 1. A microcomputer comprising: one terminal; and a second terminal for time-divisionally inputting and outputting data and addresses between the multiplex bus and the functional blocks. 2. The microcomputer according to claim 1, wherein lower addresses are output to the multiplex bus, and upper addresses are output from a third terminal. 3. The microcomputer according to claim 1, wherein the address output to the multiplex bus includes both an upper address and a lower address.