JPH0462653A - Electronic computer and extension device module - Google Patents

Abstract

PURPOSE:To make a bus control means have an access to an extension device contained in an extension device module where a CPU is connected to an extension device junction means by securing in time division the functions as the address and data buses through a part of a system bus. CONSTITUTION:When a CPU 11 has an access to an extension memory 21, a bus control circuit 12 makes an SA bus 15 function in time division as the address and data buses 23 and 24. Meanwhile a bus control circuit 22 of an extension module 2 detects a fact that the CPU 11 has an access to the module by reference to the addresses set on the bus 15 and an address signal line 17 and then connects in time division both buses 23 and 24 connected to the memory 21 to the bus 15. The circuit 22 latches the addresses which are outputted to the bus 15 and the line 17 in a period when the bus 15 is used as an address bus and outputs these addresses to the bus 23 for a necessary period. The data on the bus 24 are transferred to the bus 15 in a data reading state and in a period when the bus 15 is used as a data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an electronic computer and an expansion device module, and particularly relates to an improvement in an electronic computer to which an expansion device such as an expansion memory can be connected.

(Prior Art) In recent years, many electronic computers such as personal computers and word processors have the ability to optionally connect an expansion device such as an expansion memory to the computer main body. For example, in a computer to which an expansion memory can be connected, as schematically shown in FIG. Ru. Since the expansion memory 51 and the main body circuit 41 need to be connected by an address bus 42, a data bus 43, and a memory control signal line (not shown) necessary for accessing the expansion memory 51, the connector 4
4 is provided with pins to which signal lines and memory control signal lines included in these buses are assigned. That is, the connector 44 connects at least the main circuit 41 and the expansion memory 5.
It is necessary to have the same number of pins as the number of signal lines required for connection with 1.

(Problems to be Solved by the Invention) In recent electronic computers, the bus widths of address buses and data buses have been expanded to a greater extent than before as memory capacities have increased and computer processing capabilities have improved. Therefore, the number of pins required for a connector for connecting expansion device modules such as expansion memory modules has increased considerably.

However, in small computers such as notebook computers where space saving and portability are important design requirements, connectors for connecting expansion device modules are not acceptable. Since the area occupied by the connector and the number of pins are very limited, the large number of pins required for the connector has been a major problem.

Furthermore, when the address bus width and data bus width are changed and expanded in order to increase the memory capacity, the number of signal lines increases, and the number of connector pins increases accordingly. In the case of the above-mentioned small-sized computer, the product design may have to be significantly revised in such a case, which is very inconvenient.

The present invention was made in view of the current situation, and
The purpose is to provide an electronic computer that can significantly reduce the number of connector pins for connecting an expansion device such as an expansion memory, and an expansion device module that can be connected to such a computer. It is in.

(Means for Solving the Problems) An electronic computer of the present invention includes a central processing unit, a bus control means connected to the central processing unit via a local bus, and at least an address bus and a data bus, the bus control means a system bus connected to the system bus, and an expansion device connection means connected to a portion of the system bus, the bus control means controlling the expansion device module in which the central processing unit is connected to the expansion device connection means. When accessing an expansion device, the part of the system bus is made to function as an address bus and a data bus in a time-sharing manner, thereby achieving the above object.

Further, an expansion device module of the present invention is an expansion device module connected to the computer, which is connected to the expansion device and the part of the system bus via the expansion device connection means, and is connected to the expansion device and the part of the system bus through the expansion device connection means, and is connected to the expansion device and the part of the system bus through the expansion device connection means. Expansion device bus control means connected to the expansion device via an address bus and an expansion device data bus, the control means controlling the -portion of the system bus when the central processing unit accesses the expansion device. The above object is achieved by comprising an expansion device bus control means that is functionally connected to the expansion device address bus and the expansion device data bus in a time-sharing manner.

(Example) The invention will now be described with reference to examples.

FIG. 1 schematically shows an embodiment of an electronic computer and an embodiment of an expansion device module of the present invention.

The electronic computer 1 includes a CPU (central processing unit) 11 and a bus control circuit 12. The bus control circuit 12 is realized using a gate array. Block 19 shows the usual memory and I10 device provided in electronic computer 1. The CPU 11 and the bus control 1 circuit 12 are connected via a local bus including an address bus 13 and a data bus 14. The local bus also includes control signal lines (not shown) such as memory control signal lines.
Includes mosquitoes. Bus control circuit 12, normal memory and I1
0 device 19 is a 16-bit wide SA bus 5.1
They are connected via a system bus including a 6-bit wide SD bus 6 and an address signal line 17. The system bus further includes control signal lines (not shown) such as memory control signal lines. The SD bus 6 is a normal data bus.

On the other hand, the SA bus 5 realizes different functions depending on the type of device accessed by the CPU 11, as will be described later. The address signal line 17 is for transmitting address bits exceeding 16 bits of the address output from the CPU 1l. If the number of address bits does not exceed 16 bits, the address signal line 17 is unnecessary.

The electronic computer l further includes a connector 18 for connecting an expansion memory.
The connector 18 is connected to the SA bus 5, the address signal line 17, and a control signal line (not shown).

The extended memory module 2, which includes an extended memory 21 and a bus control circuit 22, is connected to the computer 1 via a connector 18. The bus control circuit 22 is realized using a gate array, and uses the SA bus 5, address signal line 17, and control signal line (not shown) necessary for controlling the expansion memory 21 through the connector 18. Connected to the control signal line. The bus control circuit 22 and the expansion memory 21 are connected via an address bus 23, a data bus 24, and a control signal line (not shown).

In the embodiment shown in FIG. 1, the CPU II
The SA bus 5 and SD which are controlled by the bus control circuit 12 when accessing the normal memory and I10 device 19 and when accessing the extended memory 21
The functions of Babasu 6 are different. Note that the extended memory 21 includes C
A predetermined range within the address space of the PU 11 is allocated. Therefore, the bus control circuit 12
By examining specific bits of the address output from the CPU 1, it is possible to determine whether the CPU 1 accesses the extended memory 21 or not.

(1) When C and PUll access normal memory and I10 device 19 The bus control t1 circuit 12 causes the SA bus 5 to function as an address bus and the SD bus 6 to function as a data bus.

The timing of the operations of the SA bus 5 and the SD bus 6 in this case is shown in FIGS. 2A to 2C. Figure 2 (
In a) and FIG. 3(a), "T1" to "T4" indicate clock pulses or states within a machine cycle for memory reference.

On the other hand, the bus control circuit 22 in the extended memory module 2 refers to the address on the SA bus 5 and the address signal line 17, detects that the CPU II is not accessing the extended memory 21, and as a result, the address Bus 23 and data bus 24 are not operated.

(2) When the CPU 1 accesses the extended memory 21 The bus control circuit 12 causes the SA bus 5 to function as an address bus and a data bus in a time-sharing manner.

That is, as shown in FIGS. 3(a) and 3(b), the SA bus 5 is used to transfer the address output from the CPU II to the address bus 13 to the expansion memory module 2 in the first half of the machine cycle. It will be done. Also, SA Babasu 5
is functionally connected to the data bus 14 in the latter half of the same machine cycle and is used for transferring input/output data.

As shown in FIG. 3(C), the SD bus 6 is not used at all at this time.

On the other hand, the bus control circuit 22 in the expansion memory module 2 refers to the address on the SA bus 5 and the address signal line 17, detects that the CPU II is accessing the expansion memory module 2, and controls the expansion memory 21. The connected address bus 23 and data bus 24 are functionally connected to the SA bus 5 in a time-sharing manner. Specifically, the bus control circuit 22 latches the address output to the SA bus 5 and the address signal line 17 during the period when the SA bus 5 is used as an address bus, and holds the address for a necessary period. I left the bus 23.

During a period when the SA bus 5 is used as a data bus, data on the data bus 24 is transferred to the SA bus 5 by the bus control circuit 22 in the case of data reading. Further, in the case of data writing, data on the SA bus 5 is transferred to the data bus 24 by the bus control circuit 22.

Note that when the CPU II accesses the extended memory 21, the SD bus 6 can be made to function as an address bus and a data bus in a time-sharing manner instead of the SA bus 5.

(Effects of the Invention) According to the present invention, there is provided an electronic computer in which the number of connector pins for connecting an expansion device such as an expansion memory can be significantly reduced compared to the conventional one, and the computer can be connected to such a computer. An extended device module is provided.

Therefore, according to the present invention, it becomes easier to design a connector for a computer, and the entire computer can be more easily miniaturized than before. Furthermore, even if the bus widths of the address bus and data bus are changed in the direction of expansion, the design of each part of the computer, including the connector, needs to be revised less than in the past.

4.' Theory B Figure 1 is a block diagram schematically showing an embodiment of the electronic computer and an expansion device module of the present invention, and Figures 2 (a) to (C) show its implementation. In the example, SA when the CPU accesses normal memory and I10 device
Timing diagram showing Babasu SD Babasu operation, Figure 3 (
a) to (C) are timing diagrams showing the SA bus and SD bus operations when the CPU accesses the expansion memory in the embodiment, and FIG. 4 is a block diagram illustrating a conventional computer and expansion device module. It is.

l...Electronic computer, 11...CPU, 12...Bus control circuit, 13...Address bus, 14...Data bus, 15...SA bus 16...SD bus 1
7... Address signal line, 18... Connector, 19...
...Normal memory and I10 device, 2...Expansion memory module (extension device module), 21...
- Extension memo I7 (extension device), 22... bus control circuit, 23... address bus, 24... data bus.

that's all

Claims (1)

[Claims] 1. A central processing unit, a bus control means connected to the central processing unit via a local bus, a system bus including at least an address bus and a data bus and connected to the bus control means; an expansion device connection means connected to a portion of the system bus, the bus control means controlling the expansion device when the central processing unit accesses an expansion device in an expansion device module connected to the expansion device connection means; An electronic computer that uses a portion of the system bus to function as an address bus and a data bus in a time-sharing manner. 2. An expansion device module connected to the computer according to claim 1, wherein the expansion device module is connected to an expansion device and the part of the system bus via the expansion device connection means, and includes at least an expansion device address bus and the expansion device. expansion device bus control means connected to the expansion device via a data bus for the expansion device, the expansion device bus control means connecting the part of the system bus to the expansion device address bus and the expansion device address bus when the central processing unit accesses the expansion device; An expansion device module comprising expansion device bus control means functionally connected to the expansion device data bus in a time-sharing manner.