JP3362740B2 - Multi CPU system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip CPU having a general-purpose CPU having a WAIT function as a main CPU and an external memory access function via an I / O port. The present invention relates to a multi-CPU system in which a main CPU and a sub-CPU are connected to each other as data buses. 2. Description of the Related Art Conventionally, this type of system has a UA such as 8251 on a serial port for performing serial / parallel conversion of input / output data.
An RT LSI chip was used, and the main CPU always controlled the chip by a program. However, there has been a demand to improve the function of this LSI chip and to make the UART unit intelligent while keeping the control program the same as the conventional one.
Japanese Patent Application No. 58-91454 proposes to use a one-chip CPU such as 8051, 8031, 8751 or the like as a sub-CPU in place of the sub-CPU 51 and to prevent the sub-CPU and the main CPU from simultaneously accessing an external memory.
(Japanese Patent Publication No. 63-63940) and Japanese Patent Application No. 58-17777.
5, and Japanese Patent Application No. 60-39988 (Japanese Patent Application 2-150)
95). In Japanese Patent Application No. 58-91454, a common bus 40 is directly connected between a one-chip CPU, a general-purpose CPU, and an external memory as shown in FIG. The general-purpose CPU occupies the bus to perform data processing, and at the time of data transfer, the one-chip CPU issues a HOLD request to the general-purpose CPU to give up the bus to the general-purpose CPU, thereby causing the general-purpose CPU to abandon the bus.
U is configured to occupy the bus. Japanese Patent Application No. 58-177715 has a timing signal generator as shown in FIG. After the timing signal generator generates the WAIT signal, the bus connecting the general-purpose CPU and the RAM is disconnected so that the one-chip CPU cannot access the RAM so that the one-chip CPU does not access the RAM.
M was occupied. Also, Japanese Patent Application No. 60-39
988 (Japanese Patent Publication No. 2-15095) issues a DMA request signal immediately before the one-chip CPU accesses the RAM of the main CPU as shown in FIG. 5, and switches the bus in response to a DMA-enabled reply signal from the main CPU. A simple circuit. [0004] However, Japanese Patent Application No.
In 91454, the suspended general-purpose CPU
Since the LD is still applied, there is a disadvantage that the execution time is greatly reduced if the number of bytes of the data transfer is large, and Japanese Patent Application No. Sho 58-177715 has improved this disadvantage.
Has the disadvantage of requiring a large number of parts.
Japanese Patent Application No. 60-99988 (Japanese Patent Publication No. 2-15095)
An object of the present invention is to provide a system which does not cause a decrease in execution speed with a small number of components, but has a problem that software of a main CPU becomes special. That is, the main body of the access is a one-chip CPU, and the main CPU simply waits for the one-chip CPU to transmit the data written in the RAM. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to make it possible for a main CPU to use a one-chip CPU of a sub CPU of a communication interface as if it were a simple peripheral device without changing a general-purpose OS or the like. Multi C that can be
It is to provide a PU system. In the multi-CPU system of the present invention, the chip select signal / CS ("/" of / CS) for the sub CPU issued from the main CPU indicates that the CS signal has negative logic. A first AND gate for obtaining the logical product of the read control signal / IORD and outputting it to the sub CPU as a read / write identification signal, and a chip select signal / CS. A second AND gate for obtaining a logical product of the interrupt control signal / IOWR and a NOR gate for obtaining a NOR of two outputs of the first and second AND gates and outputting the result to the sub CPU as an interrupt signal / INTO , An inverter for inverting a write signal / WR issued from the sub CPU, and a logical AND of an output of the inverter and an output of the NOR gate to obtain a main CP And a NAND gate that outputs to U a WAIT request signal. The chip select signal / C issued by the main CPU
S, read control signal / INTO, write control signal / IOWR
Are read / write identification signals and interrupt signals / INTO
Is converted into a WAIT request signal by a logical product of the output of the sub CPU and the main CP.
Input to U. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a multi-CPU system 1 according to the present invention.
FIG. 2 is a circuit diagram of a signal converter 50 according to the embodiment of FIG. 1. In FIG. 1, a multi-CPU system according to the present embodiment includes a main CPU 10 composed of a known general-purpose CPU, for example, 8088 of Intel Corporation, a sub CPU 20 composed of a known one-chip CPU, for example, 8051 of Intel Corporation, a ROM and a RAM. An external memory 30, a bus 40 commonly connected between the main CPU 10, the sub CPU 20, and the external memory 30;
A signal conversion unit 50 is connected between the U10 and the sub CPU 20 and converts a signal between the two. In FIG. 2, a signal conversion unit 50 includes an AO terminal of the main CPU 10 and a port P34 of the sub CPU 20.
A signal line that is connected to
A first AND gate 51 having an input terminal connected to the / INTO and / CS terminals of the main CPU 10, and / IOWR /
Second AND gate 5 whose input terminal is connected to CS terminal
2. The inputs are connected to a NOR gate 53 to which the outputs of the first and second AND gates 51 and 52 are input and output to the / INTO port of the sub CPU 20, and a port P35 of the sub CPU 20 to which the / WR signal is output. Inverter 54
And the signal branched from the output of the NOR gate 53 and the output of the inverter 54,
It has a NAND gate 55 whose output is connected to the IT terminal. When the main CPU 10 reads the received data, / C
When S, / IORD is set to low, AND gate 5
1. Via the NOR gate 53, / INTO of the sub CPU 20
Is sent a "low". The sub CPU 20 confirms that the access has been made by interruption or polling, and confirms that the access is in a status because both the port P34 and the port P35 are "high".
At this time, the main CPU 10 remains stopped because the / WAIT terminal is “low”. When the sub CPU 20 executes the external memory write, the data buses P00 to P0
7, the status following the address is output, and the / WR signal becomes "low". This / WR signal is output from the inverter 5
4, the NAND gate 55 and the NOR gate 5
An AND operation is performed on the / INTO signal branched from 3 and the / WAIT of the main CPU 10 is set to the terminal “high”. The main CPU 10 reads data on the data bus, that is, data output from the sub CPU 20. When writing transmission data from the main CPU 10, the signals / CS,
/ IOWR signal is set to “low”, so that the sub C
/ INTO of PU20 becomes "low". Sub CPU2
0 indicates access in the same manner as in the case of reading received data, determines that data is to be written based on the signals of the ports P34 and P35, and sets the data buses P00 to P07.
Capture data from Thereafter, by changing the / WR signal of the port P36 to “high”, “low”, or “high”, the WAIT state of the main CPU 10 is released, and the write operation of the main CPU 10 ends. As described above, the present invention provides a main CP by providing a signal converter comprising a logic gate between a general-purpose main CPU and a one-chip sub CPU.
The U can control the sub CPU as if it were a mere peripheral device without changing software such as a general-purpose OS, which has the effect of improving functions of a communication system and the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system configuration diagram of one embodiment of a multi-CPU system of the present invention. FIG. 2 is a circuit diagram of a signal converter 50 of the embodiment of FIG. FIG. 3 is a diagram showing a first embodiment of a conventional multi-CPU system. FIG. 4 is a diagram showing a second embodiment of the conventional multi-CPU system. FIG. 5 is a diagram showing a third embodiment of the conventional multi-CPU system. [Description of Signs] 10 Main CPU 20 Sub CPU 30 External memory 40 Bus 50 Signal converter 51, 52 AND gate 53 NOR gate 54 Inverter 55 NAND gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (1)

(1) A general-purpose CPU having a WAIT function is defined as a main CPU, and a one-chip CPU having an external memory access function via an I / O port is defined as a sub CPU. In a multi-CPU system in which the data buses of both sub CPUs are mutually connected, a logical product of a chip select signal / CS and a read control signal / IORD for the sub CPU issued by the main CPU is obtained and read by the sub CPU. A first AND gate for outputting a write / write identification signal, a second AND gate for obtaining a logical product of the chip select signal / CS and a write control signal / IOWR, and the first and second AND gates A NOR gate for calculating the NOR of the two outputs of the above and outputting the result to the sub CPU as an interrupt signal / INTO; An inverter for inverting a write signal / WR issued from the sub CPU, and a NAND of an output of the inverter and an output of the NOR gate to obtain the NAND
And a NAND gate for outputting a WAIT request signal to the multi-CPU
system.