KR0170742B1 - Data transfer method using mbus - Google Patents

Abstract

The present invention relates to a data transfer method using an embus interface between a system bus of a medium computer system and an ambus used as a local bus of the medium computer. The present invention relates to a block read cycle of reading data in units of blocks from a shared memory to a local memory. Dividing a block write cycle of writing data in units of blocks from local memory to shared memory; Requesting a bus license for the embus and arbitrating the bus license; Indicating that the bus is busy after using the bus license and using the bus; A mode determination step of determining whether to perform data burning (data transmission mode), retransmission (retransmission mode), or process as an error (error mode); And transmitting data in block units in the data transmission mode and ending the transmission cycle, retransmitting data in block units in the retransmission mode, and ending the transmission cycle in the error mode.

According to the present invention, the logic of the peripheral is eliminated by integrating read and write state machines into one for the master and slave functions, so that the logic is simple and the ASIC can reduce power consumption and reduce cost.

Description

Data transmission method using Embus

1 shows a state machine of a conventional block mode MBUS read in master function.

2 shows a state machine of a conventional block mode MBUS write in the master function.

3 shows a state machine of conventional single mode MBUS read in slave function.

4 shows a state machine of a conventional single mode MBUS write in slave function.

5 shows a state machine of a conventional slave read and write.

6 is a block diagram of an interface device between an MBUS and a system bus that is used as a local bus in an input / output module of a medium computer system having a bus and having a shared memory structure.

7 shows a master MBUS state diagram for block mode read / write operations.

8 illustrates a slave MBUS state machine diagram for single mode read / write and slave read / write operations.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface, and more particularly, to a data transmission method using an embus for interfacing a system bus of a medium computer system and an ambus used as a local bus of the medium computer.

Embus (hereinafter referred to as MBUS) is a bus developed and used by SUN Microsystems (the name of a US computer company). It is a synchronous bus with multiple addresses and data multiplexed and 36 bits. By using an address of 64 gigabytes (64 GB) can be addressed. It has a 64-bit data bus and supports up to 128 bytes of block transfer as well as a single transfer and has a bandwidth of 320MB / sec.

In general, the MBUS interface device has a master / slave function, and the master function reads block mode and block mode write, and the slave function reads single mode, Single mode write, slave read and slave write functions are available.

In the conventional MBUS interface method and apparatus having a master / slave function, the block mode of the master MBUS function is divided into read and write state machines. FIG. 1 shows a state machine of conventional block mode MBUS read in master function, and FIG. 2 shows a state machine of conventional block mode MBUS write in master function.

In FIG. 1, the state Idle 100 is a state after the state machine is initialized, and is a standby state of the read state machine. State Addr 110 then latches the address at the beginning of the block read cycle, goes to state R3 120 for 32 byte reads, goes to state R1 140 for 16 bytes, and states R0 150 for 8 bytes. Transition to). The state Rr 160 is a state in which the retransmission is requested when the retransmission request is performed in the states R3 120, R2 130, R1 140, and R0 150. The state Err 170 is a state in which an error is processed when an error occurs in the states R3 120, R2 130, R1 140, and R0 150.

Similarly, in FIG. 2, the state Idle 200 is a state after the state machine is initialized and is a standby state for the operation of the write state machine. The state Addr 210 latches the address at the beginning of the block write cycle, goes to state W3 220 for 32 byte writes, goes to state W1 240 for 16 bytes, and states W0 250 for 8 bytes. Transition to). The state Rr 260 is a state in which the retransmission is performed when the retransmission request is performed in the states W3 120, W2 130, W1 140, and W0 150. The state Err 170 is a state in which an error is processed when an error occurs in the states W3 120, W2 130, W1 140, and W0 150.

If the transmission is properly performed in the read and sweep state machine, the process goes to the R0 (150) step or the W0 (250) step and goes to the Idle (100, 200) step, where one cycle of data reading and writing is completed. Since the MBUS is a synchronous bus, each state transition occurs in synchronization with a bus clock used in the synchronous bus.

Meanwhile, the conventional MBUS interface device having a slave function is used separately as a single mode read and write state machine for the slave MBUS function. 3 shows a state machine of conventional single mode MBUS read in slave function, and FIG. 4 shows a state machine of conventional single mode MBUS write in slave function. 5 shows a state machine of a conventional slave read and write.

In FIGS. 3, 4, and 5, the states Idle 300, 400, and 500 are states after the state machine is initialized and are in standby state for operation of the state machine. The MBUS timeout occurs when the error signal MERR_ and the retry signal MRTY_ that are generated during transmission are continuously enabled and the transmission ready signal MRDY_ is disabled. RR is a signal for requesting retransmission of data. State R is a state for performing a read, and state W is a state for performing a write. In addition, the state R / R is a state of retrying, and the state is a state in which Addr latches an address to perform a read or write.

As above, the block read and block write state machines are separately implemented for the master function, and the single state read / write and slave read / write functions are separately implemented for the slave function. This complexity, especially when implemented as an application specific semiconductor device (ASIC) has a problem that the chip size, the power consumption is expensive and expensive.

Therefore, the present invention was created to solve the above-described problems, and the read and write states for the master and slave functions to simplify the peripheral logic, to require a small power consumption when implementing the custom semiconductor device and to improve the data processing speed It is an object of the present invention to provide a data transmission method using an embus interface between a system bus of a medium computer system and an ambus used as a local bus of the medium computer.

In the medium computer system according to the present invention for achieving the above object, has a bus-based, shared memory structure, using the M bus of Sun Microsystems (US company name) as a local bus of the input / output module In the method of transferring data in a predetermined block unit from a system bus to a local memory or a local memory to a system bus using the local bus, the data is read in a predetermined block unit from the shared memory to the local memory through the system bus. Dividing a block read cycle and a block write cycle of writing data in a predetermined block unit from the local memory to the shared memory through a system bus; Requesting a bus license for the embus and arbitrating the bus license; Indicating that the bus is in use and using the bus when the bus license is obtained; A mode determination step of determining whether to transmit data (data transmission mode), retransmission (retransmission mode), or process as an error (error mode) by checking signals for controlling data transmission provided by Embus; And transmitting data in the predetermined block unit in the data transmission mode and ending the transmission cycle in the mode determination step, transmitting data in a predetermined block unit again in the retransmission mode, and immediately ending the transmission cycle in the error mode. It is done by

According to the present invention for achieving the above object, a medium-based computer system based on a bus and having a shared memory structure, and using an Embus of Sun Microsystems (US company name) as a local bus of this output module. The central processing unit (CPU) of the I / O module using the local bus to access data from the system bus or to the system bus (single mode cycle), or to access the internal register of the I / O module (slave cycle) After the CPU determines whether to start the single mode cycle or the slave cycle, indicating that an ambus is in use; In the case of the single mode cycle, single mode read or single mode write is performed, and if the cycle is normal by checking the state of the system bus and the embus, if the cycle is normal, the cycle is terminated and an error occurs and retransmission is attempted. Doing; And in the case of the slave cycle, writing or reading data to the register, checking a response signal, and ending the cycle.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 6 is a block diagram of an interface device between an MBUS and a system bus that is used as a local bus in an I / O module of a medium computer system having a bus-based and shared memory structure. 600 is composed of an MBUS interface device 610 and two system bus data buffers SDX (650, 660). The MBUS interface device 610 is composed of a master / slave MBUS state machine 620, a DMA state machine 640, and a MBIX 630 composed of a plurality of registers. The master / slave MBUS state machine 620 is responsible for the interface between the system bus and the MBUS, and is composed of a master MBUS state machine 670 and a slave MBUS state machine 680. The DMA state machine 640 is responsible for DMA operation, and the MBIX 630 includes one or more registers in which the central processing unit of the input / output module or the DMA controller records information about the DMA for DMA transfer. The SDX 650 and 660 contain a first-in, first-out (FIFO) memory, which is a data buffer, to process data in 64-bits, and to transfer data of 128 bits to a system bus using two SDXs.

The core of the present invention relates to the master MBUS state machine 670 and the slave MBUS state machine 680. The master MBUS state machine 670 operates when the MBUS interface device 610 acts as a master and transfers data between a local memory (not shown) of an input / output module and a shared memory (not shown) connected to a system bus. When transferring (this is called block mode read / write), it becomes a master and controls each transfer step. Typically, the data transfer is a direct memory access (DMA) transfer and a block transfer.

In addition, the slave MBUS state machine 680 transmits the data of the local memory (not shown) of the input / output module to the shared memory or vice versa when the central processing unit (not shown) of the input / output module transmits the data. Read / Tm) and become slaves to control each transfer step. In addition, when the central processing unit of the input / output module accesses the registers in the MBIX 630 for the integrated memory access transmission and the like (hereinafter referred to as slave read / write), it becomes a slave and controls the control.

An operation of the master MBUS state machine 670 and the slave MBUS state machine 680 will be described with reference to FIGS. 7 and 8. 7 shows a master MBUS state diagram for a block mode read / write operation. The state machine includes IDL 700, MBREQ 710, MBADR 720, BLKDO 730, BLKD 740, It consists of BLKRDY 750, ERROR 760, and END 770 states. First of all, the block cycle refers to the transfer of data to and from the system bus on the MBUS in block units (64 bytes) using the MBUS state machine. Block reading and writing are classified into a dir signal of the DMA state machine 640 so that dir = 1 is a write and dir = 0 is a read.

The IDL 700 state enables the signal MBR_, which requires MBUS to start a block cycle, and transitions to the MBREQ 710 state. If the MBR_ signal is not enabled, it remains in IDL 700 state.

The MBREQ 710 state enables the signal MBG_ to allow the use of the MBUS, indicating that the master has obtained the right to use the MBUS and transitioning to the MBADR 720 state.

The MBADR 720 state signals the start of a bus cycle by enabling a signal MAS_ indicating that MBUS is valid and a signal MBB_ indicating that MBUS is in use, and disabling the MBR_ signal. As shown in Table 1, the state of the signal MRDY_ indicating completion of data transmission preparation, the signal MRTY_ requesting retransmission of data, and the signal MERR_ indicating data transmission error are checked, and the ERROR 760 state is checked. Determine whether to go to, go to BLKD 740 state or to be in BLKDO 730 state.

The BLKD 740 transfers data four times by 16 bytes using a 3-bit counter. If the counter works properly, the BLKD 740 transitions to the BLKRDY 750 state. If the counter does not work properly, the BLKD 740 stays in the BLKD 740 state. .

In the ERROR (760) state, the bus cycle is executed, and when an error occurs in the BLKDO (730) state, the signal returns to the END (770) state.

In the END 770 state, the MBUS cycle ends and all signals are negated before returning to the IDL 700 state.

8 shows a slave MBUS state diagram for single mode read / write and slave read / write operations, wherein the state machine is in the state of IDLE 800, SLV 810, NORM 820, NORMRDY 830. It consists of.

Single-mode cycles are used when the I / O module's CPU wants to access 8 bytes of data directly on the system bus. The slave cycle can access the internal registers of the MBIX 640 and access the data size in 32 bits.

The IDLE 800 states that the MBUS interface device 610 performs a single mode cycle by reading the state of the signal with the slvCyl_ signal starting the slave cycle and the normalGo_ signal starting the single mode cycle in order to function as a slave. Decide whether to perform slave cycle. If the normalGo_ signal is asserted to perform a single mode cycle, it transitions to the NORM 820 state and enables a signal mas_ indicating that MBUS is valid. If the slvCyl_ signal is enabled and the slave cycle starts, the signal transitions to the SLV 810 state and enables the signal mas_ indicating that the MBUS is valid.

The SLV (81) state performs a slave cycle, sees a signal (mden) that has information distinguishing between read and write, that is, write operation is performed if mden = 1, read operation is performed if mden = 0, and MBUS After checking the response signal (M MRDY_) for use, it goes to the IDLE (800) state.

On the other hand, the NORM (820) state performs a single mode cycle, checks a signal (dir_) indicating single mode read / write information, proceeds with a read operation if dir = 0, a write operation if dir = 1, and a status of the system bus. If the cycle is normal by checking the MBUS state, the state transitions to the NORMRDY 830 state, and if an error occurs, the state transitions to the IDLE 800 state and retransmits.

The NORMRDY 830 state ends the cycle after confirming the bus response signal MRDY_ and transitions to the IDLE 800 state.

As described above, according to the present invention, the peripheral logic is eliminated by integrating the read and write state machines into one for the master and slave functions, so that the logic is simple, the small device can be used when implemented as a custom semiconductor device, and the power consumption is small and the cost is low. Can be reduced. It can also process data at high speeds, improving performance.

Claims (4)

In the medium computer system, which is based on the bus and has a shared memory structure, and uses the Embus of Sun Microsystems (US company name) as the local bus of the I / O module, the local bus is used to transfer the system bus to the local memory. Or a method of transferring data in a predetermined block unit from a local memory to a system bus, the method comprising: a block read cycle of reading data in a predetermined block unit from the shared memory to a local memory via the system bus, and a system bus from the local memory. Dividing a block write cycle of writing data to the shared memory by a predetermined block unit; Requesting a bus license for the embus and arbitrating the bus license; Indicating that the bus is in use and using the bus when the bus license is obtained; A mode determination step of determining whether to transmit data (data transmission mode), retransmission (retransmission mode), or process as an error (error mode) by checking signals for controlling data transmission provided by Embus; And transmitting data in the predetermined block unit in the data transmission mode and ending the transmission cycle in the mode determination step, transmitting data in a predetermined block unit again in the retransmission mode, and ending the transmission cycle in the error mode. Block data transmission method using an embus, characterized in that. The signal controlling the data transmission in the mode determination step is a signal (MRDY_) indicating the completion of data transmission ready, a signal (MRTY_) for requesting retransmission of data, a signal (MERR_) indicating a data transmission error. Block data transmission method using the Embus. The method of claim 1, wherein the data transmission in the data transmission mode uses an counter to transmit an amount of data corresponding to a predetermined block, and checks the operation of the counter to determine a next step transition. Block data transmission method using. The central processing unit (CPU) of the input / output module (CPU) of the input / output module is a medium-based computer system that uses a bus-based, shared memory structure, and uses an Ambus of Sun Microsystems (the US computer company name) as a local bus for the input / output module. A method of accessing data from or to a system bus using a local bus (single mode cycle) or accessing an internal register of the input / output module (slave cycle), wherein the central processing unit starts the single mode cycle. After determining whether or not to start the slave cycle, indicating that an embus is being used; In case of the single mode cycle, single mode read or single mode write is performed, and the cycle is normal by checking the status of the system bus and the embus, and the cycle is terminated after confirming the response signal. Attempting; And in case of the slave cycle, writing or reading data to the register, checking a response signal, and ending the cycle.