JPH04170661A - Microprocessor system - Google Patents

Abstract

PURPOSE:To connect a host processor having different bit width to a miroprocessor by providing the microprocessor with the 1st and 2nd bidirectional buffers, an external output terminal and a changeover circuit. CONSTITUTION:The 1st bidirectional buffer 61 acts so as to connect the pre scribed W bits of the host processor 70 to the lower (or upper) W bits of a shared memory 80 having 2W-bit width. The 2nd bidirectional buffer 62 acts so as to connect the prescribed W bits of the processor 70 to the upper (or lower) W bits of the shared memory 80 based upon a changeover signal CH. The changeover signal CH is supplied to an external output terminal 60 comple mentally with the buffer 62, and when the host computer 70 is a processor with W-bit width, a changeover circuit 68 supplies the changeover signal to the buffer 62. Thus, the host processor having the different bit width can be connected to the microprocessor.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a microprocessor having at least a microprocessor, a host processor, and a shared memory, the microprocessor and the host processor having exclusive access to the shared memory. It's about systems.

(Prior Art) Conventionally, as this type of technology, there has been one shown in FIG. 2, for example.

FIG. 2 is a schematic block diagram showing an example of the configuration of a conventional microprocessor system.

This microprocessor system includes a microprocessor 10, a host processor 30, and a shared memory 40.
The combination constitutes a high-speed processing subsystem.

The microprocessor 10 has the function of accessing the shared memory 40 and processing data, as well as the function of the host processor 3.
0 and the shared memory 40, for example, 32
Built-in BIT microprocessor body 11,
As a connection terminal on the host processor side, there is a host side bus terminal (hereinafter referred to as H bus terminal) 12 that can be connected to, for example, 32 bits to a data line from the host processor 30.
, a data bus terminal (hereinafter referred to as D bus terminal) 13, an address bus terminal (hereinafter referred to as A bus terminal) 14, a write signal output terminal (hereinafter referred to as WE terminal) 15, as connection terminals on the private memory side. and a read signal d power terminal (hereinafter referred to as an RE terminal) 16.

Furthermore, inside the microprocessor 10, the H bus terminal 12 and the D bus terminal 13 are connected by a 32-bit data line, and the H bus terminal 12 and the A bus terminal 14 are connected by a 16-bit address line. A bidirectional buffer 17 for the host processor side is on the line, and an address register 18 for the host processor side is on the address line.
are provided for each. Microprocessor body 1
1, a 32-bit data line is connected to the D bus terminal 13, a 16-bit address line is connected to the A bus terminal 14, and a bidirectional buffer for the microprocessor side is connected to the data line. 19, and address registers 20 for the microprocessor side are provided on the address lines, respectively.

Furthermore, this microprocessor 10 has a WE terminal 1.
A signal generation port that supplies write signal WE and read signal RE to terminal 5 and RE terminal 16, respectively! @21 is built-in.

The host processor 30 is provided externally to the microprocessor 10, has a function of exchanging data with the shared memory 40 via the microprocessor 10, and is composed of, for example, a 32-bit wide processor. This host processor 30 is connected to the microprocessor 10 via an external bus, and a 32-bit data line is connected to the H bus terminal 12, for example.

The shared memory 40 is provided outside the microprocessor 10 and the host processor 30, is accessed exclusively by the microprocessor main body 11 and the host processor 30, and has a maximum capacity of, for example, 64 kW x 3.
Consists of 2-bit static RAM'''C', 32
The data is connected to the D bus terminal 13 via the bit data line, to the A bus terminal 14 via the 16-bit address line, to the WE terminal 15 via the write signal line, and to the RE via the read signal line.
They are connected to terminals 16, respectively.

Next, the operation will be explained.

When the microprocessor main body 11 is at rest for the first time,
The host processor 30 transfers the data and program (or command string) to be processed by the microprocessor main body 11 to the shared memory 40 (data transfer). At this time, the host processor 30 first sends an address signal to the address register 18 side to designate the transfer destination, and then transfers data, programs, etc. to the H bus terminal 12, bidirectional buffer 17, and D bus terminal 13. The data is sent to the shared memory 40 via the shared memory 40.

After data, programs, etc. are transferred into the shared memory 40, the microprocessor main body 11 transfers the data to the D bus terminal 13 via the address register 20 and the bidirectional buffer 19.
The program in the shared memory 40 is read out via the A bus terminal 14, data processing is performed on the data in the shared memory 40 based on the program, and the processing result is stored in the shared memory 40.

When the microprocessor body 11 finishes processing the data,
The host processor 30 reads the processing results in the shared memory 40 via the H bus terminal 112 and the like.

During the above operation, the shared memory 40 is accessed exclusively in units of 32 bits by both the microprocessor main body 11 and the host processor 30, and writing and reading thereof are performed from the signal generation diagram 821 to the WE terminal 15 and the RE terminal 16, respectively. This is executed by applying a write signal WE and a read signal RE (for example, both are pulse signals) inputted via the .

In such a conventional microprocessor system, the signal generation diagram &@21 that generates control signals such as the write signal WE and the read signal RE, and the bidirectional buffers 17 and 19 that are connection circuit elements are connected to the microprocessor main body. 1
1 and is built into the microprocessor 10, constituting a relatively compact system.

(Problems to be Solved by the Invention) However, the microprocessor system having the above configuration has the following problems.

(a> Although the host processor 30 only performs the function of data transfer to the shared memory 40, it occupies the H bus terminal 12 of the 32-bit data line in the microprocessor 10. As a result, the area of the microprocessor 10 increases in proportion to the number of its terminals, and the closeness of the terminals increases, making external wiring etc. denser and more complex, making wiring layout difficult due to routing, etc. It becomes.

Therefore, in conventional microprocessor systems, the utilization efficiency of terminals has not been sufficiently improved, the microprocessor 10 has become larger, external wiring has become closer and more complex, and the reliability of the entire system has been reduced. Sexuality decreases.

(b) In the microprocessor system shown in FIG. 2, a high-speed processing subsystem is configured by the combination of the microprocessor 10 and the shared memory 40, and the high-speed processing subsystem is connected to the host processor 3 via an external bus.
is combined with In this way, in conventional microprocessor systems, the host processor 30 is allowed to be relatively loosely coupled to the high-speed processing subsystem, so it is possible to replace the host processor 30 with a 16-bit I system, for example. However, in conventional systems, there is no means to deal with this on the high-speed processing subsystem side, making it difficult to combine host processors with different bit widths.

The present invention provides a microprocessor system that solves the problems of the above-mentioned conventional technology, such as the failure to sufficiently improve the utilization efficiency of terminals and the difficulty in connecting host processors with different bit widths. It is something.

(Means for Solving the Problems) In order to solve the above problems, a first invention provides a microprocessor having a built-in microprocessor main body having a 2W bit width (W is a positive integer), and a microprocessor having a predetermined W bit width. a host processor having a bit width including; a shared memory having the 2W bit width and accessed exclusively by the microprocessor main body and the host processor;
In this microprocessor system, the following measures are taken.

That is, a first bidirectional buffer connects a predetermined W bit of the host processor to the lower or upper W bit of the shared memory; and a first bidirectional buffer connects the predetermined W bit of the host processor to the upper or lower W bit of the shared memory based on a switching signal. a second bidirectional buffer connected to the W bit; an external output terminal to which a switching signal is supplied complementary to the second bidirectional buffer; The microprocessor is provided with a switching circuit for outputting to either the bidirectional buffer or the external output terminal.

In a second aspect of the invention, based on the first aspect, the host processor is configured with a processor having the 2W bit width, and a predetermined value of the host processor is determined based on a switching signal inputted via the external output terminal. A third bidirectional buffer is provided outside the microprocessor to connect W bits other than the W bits of the microprocessor to the upper or lower W bits of the shared memory.

(Operation) According to the first invention, since the microprocessor system is configured as described above, the first bidirectional buffer transfers a predetermined W bit of the host processor to the lower (or upper) of the shared memory. Works to connect to the W bit.

The second bidirectional buffer serves to connect a predetermined W bit of the host processor to the upper (or lower) W bit of the shared memory based on a switching signal.

A switching signal is supplied to the external output terminal in a complementary manner to the second bidirectional buffer, and the switching circuit supplies the switching signal to the second bidirectional buffer, for example, when the host processor is a W-bit width processor. When the host processor is a 2W bit wide processor, the switching signal is supplied to the external output terminal.

Therefore, in this first invention, for example, when the host processor is configured with a W-P1-F processor, the processor to the host 1 is configured to perform
Signals are exchanged with the lower or upper bits of the shared memory via the first bidirectional buffer, and the upper bits of the shared memory are transferred via the second bidirectional buffer. Signals are exchanged with the lower (lower) W bit.

According to a second invention, in the first invention, the host 1
Since the host processor is configured with a processor with a 2W bit width and the third bidirectional buffer is provided, the host processor uses the predetermined W bits to read data from the shared memory via the first bidirectional buffer. Signals are exchanged with the lower (or upper) W bits, and the remaining W bits other than the predetermined W bits are used to transmit signals to and from the upper (or lower) W bits of the shared memory via the third bidirectional buffer. ) Transfers signals to and from the W bit.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a microprocessor system showing a first embodiment of the present invention.

This microprocessor system includes, for example, a microprocessor 50, a host processor 7o, and a shared memory 80, and the combination of the microprocessor 50 and shared memory 8o constitutes a high-speed processing subsystem.

The microprocessor 50 has, for example, a function of accessing the shared memory 80 and processing data, and a function of connecting between the host processor 70 and the shared memory 80. Built-in.

The microprocessor 50 has an H bus terminal 5, which can be connected to a data line from the host processor 70, for example, for 16 bits, as a connection terminal on the host processor side.
2. As connection terminals on the shared memory side, there are a data bus terminal (hereinafter referred to as DU bus terminal) 53 for upper 16 bits of data DU and a data bus terminal (DL) for lower 16 bits of data (
(hereinafter referred to as DL Babasu) 54, A bus terminal (hereinafter referred to as WEU terminal), upper side write signal output terminal (hereinafter referred to as WEU terminal)
6. Lower one rule write signal output terminal (hereinafter referred to as WEL terminal) 57, write signal output RE terminal ``58,
Furthermore, the selection signal S, which is a terminal related to the characteristics of this embodiment,
Five external input terminals for EL input, an external output terminal 60 for outputting a switching signal CH, and the like are provided.

Further, inside the microprocessor 50, for example, 16-bit data is stored between the H bus terminal 52 and the DL bus terminal 54, between the H bus terminal 52 and the DU bus terminal 53, and between the H bus terminal 52 and the A bus terminal 55. A first bidirectional buffer 61, a second bidirectional buffer 62, and an address register 63 for the host processor side are provided on each line. The microprocessor body 51 contains the upper 16 bits of data DU.
A data line for the lower 16 bits of data DL is connected between the DL bus terminal 54, and a 16-bit address line is connected between the A bus terminal 55. , a bidirectional buffer 64, a bidirectional buffer 65, and an address register 66 for the microprocessor are provided on each line.

Here, the address registers 63 and 66 each have a function of temporarily storing an address signal on the host processor side and a microprocessor side, for example, and are constructed using flip-flops or the like.

Further, the bidirectional buffers 61, 62, 64, and 65 have, for example, a function of selectively passing a signal, and are configured using, for example, a tri-state buffer circuit. Note that for the bidirectional buffer 62, the switching signal C
It is configured to function only when H is supplied.

Furthermore, this microprocessor 50 includes a signal generation circuit 67 that supplies an upper write signal WEU, a lower write signal WEL, and a read signal RE to the WEU terminal 56, WEL terminal 57, and RE terminal 58, respectively, and a switching circuit. 68 is built-in.

Here, the switching circuit 68 outputs the switching fs number CH (for example, an enable signal) to the bidirectional buffer 62 or external output based on the selection signal SEL set according to the bit width of the host processor connected to the H bus terminal 52. This is a circuit that outputs to either one of the terminals 60, and is composed of, for example, circuits 1 to 1, and is connected to an external input terminal 59, an external output terminal 60, and a bidirectional buffer 62, respectively, via signal lines. In this embodiment, the switching circuit 68 outputs the switching signal CH only to the second bidirectional buffer 62 when the selection signal SEL is fixed at a low level (Low), and the selection signal SEL is fixed at a high level. The switching signal CH is set to be output only to the external output terminal 60 when the external output terminal 60 is activated.

The host processor 70 is provided externally to the microprocessor 50, has the function of transmitting and receiving data to and from the shared memory 80, for example, by controlling the microprocessor 50, and is composed of, for example, a 16-bit wide processor. There is. This host processor 70 is connected to the microprocessor 50 via an external bus, and a 16-bit data line is connected to the H bus terminal 52, for example.

The shared memory 80 is provided outside the microprocessor 70 and the shared memory 80, is accessed exclusively by the microprocessor 70 and the shared memory 80, and is composed of, for example, a static RAM with a maximum capacity of 64 kW x 32 bits. . This shared memory 80 is connected to the DU bus terminal 53 via a data line for the upper 16 bits of data DU, to the DL bus terminal 54 via a data line for the lower 16 bits of data DL, and via a 16-bit address line. to the A bus terminal 55, to the WEU terminal 56 via the signal line for the upper write signal WEU, to the WEL terminal 57 via the signal line for the lower write signal WEL,
They are each connected to an RE terminal 58 via a signal line for read signal RE.

Next, the operation will be explained.

When the selection signal SEL input to the switching circuit 68 becomes low level, the bidirectional buffer 68 functions (enables). When the microprocessor main body 51 is initially at rest, the host processor 70 transfers, for example, data and programs (or command sequences) to the shared memory 80 (
data transfer). This data transfer by the host processor 70 is performed, for example, as follows.

The host processor 70 sends an address signal indicating the transfer destination address to the shared memory 8 via the address register 63.
At the same time as outputting to the 0 side, first, a write data signal of the upper 16 bits of data is outputted.

Ru. This write data signal enters the microprocessor 50 through the H bus terminal 52 via a 16-bit data line, passes through bidirectional buffers 61 and 62, and is shared via the DL bus terminal 54 and the DU bus terminal 53, respectively. It is output to the memory 80 side. At this time, the upper side write signal WEU is generated by the signal generation circuit 67, and the upper side write signal WEU is sent to the shared memory 8 via the WEU terminal 56.
0, and in the shared memory 80, the write data signal of the upper 16 bits of data from the DU terminal 53 is written to the upper 16 bits 71 of the address specified by the address signal.

Next, the host processor 70 outputs a write data signal for the lower 16 bits of data. This write data signal enters the microprocessor 50 through the H bus terminal 52 via a 16-bit data line, and enters the bidirectional buffer 61.
and 62, and are output to the shared memory 80 side via the DL terminal 54 and the DU Babasu child 53, respectively. At this time, the signal generation circuit 67 generates the lower side write signal WEL.
is generated, and the lower side write signal WEL is sent to WEL terminal 5.
7 to the shared memory 80, and the shared memory 8
0, the write data signal of the lower 16 bits of data from the DL terminal 54 is written to the lower 16 bits of the address specified by the address signal.

After the data, programs, etc. from the host processor 70 are transferred to the shared memory 80 as described above,
For example, the microprocessor main body 51 starts operating.

The microprocessor main body 51 has an address register 66
The address is specified by an address signal via the A bus terminal Raw and the bidirectional buffer 64 and the DU terminal 33.
The data signal of the upper 16 bits of data is sent and received via
Also, data signals of the lower 16 bits of data are exchanged via the bidirectional buffer 65 and the DL terminal 54, respectively.
Performs data processing based on the program, data, etc. transferred from the host processor 70 to the shared memory 80,
The processing results are stored in the shared memory 80.

When the microprocessor body 51 finishes data processing and stores the processing results in the shared memory 80, the host 1-processor 70 reads the processing results, for example, as follows.

The host processor 70 outputs an address signal indicating the address to be read to the shared memory 80 side via the address buffer 63, and also generates a read signal RE by the signal generation circuit n67.

This read signal RE is output to the shared memory 80 via the RE terminal 58. As a result, the read data signal of the upper 16 data bits i- of the shared memory 80 is output to the bidirectional buffer 62 side via the DU bus terminal 53, and the read data signal of the lower 16 data bits is output to the DL bus terminal 54.
The signal is output to the bidirectional buffer 61 system via the . At this time,
For example, the bidirectional buffer 62 is controlled to pass one code to the H bus terminal 52 side, and the bidirectional buffer 61 is controlled so as not to pass a signal, so that only the read data signal of the upper 16 bits of data from the shared memory 80 is transmitted. It passes through the H bus terminal 52 and is taken in by the host processor 70 via a 16-bit data line.

The host processor 70 stores the top 1 data in the shared memory 80.
After taking in the 6-bit read data signal, the bidirectional buffer 61 passes the signal to the H bus terminal 52 side, and the bidirectional buffer 61 is controlled so as not to pass the signal, and the lower 16 data from the shared memory 80 are transferred. Only the bit read data signal passes through the H bus terminal 52 and is taken in by the host processor 70 via the 16-bit data line. In this way, the host processor 70 reads the processing results in the shared memory 80 via the microprocessor 50.

This first embodiment has the following advantages.

In this embodiment, the microprocessor 50 is provided with an external output terminal 60, first and second bidirectional buffers 61 and 62, and a switching circuit 68, and the switching circuit 68 converts the switching signal CH into two directions according to the setting of the selection signal SEL. The data is output to the buffer 62 to make the bidirectional buffer 62 function, and 16 bits are connected to the H bus terminal 52 of the microprocessor 50 as a data line from the host processor 70. In the microprocessor system of this embodiment, when the host processor 70 is configured with a 16-bit wide processor, the host processor 7
0, the 32-bit wide shared memory 80 can be accessed in 16-bit units.

Therefore, in the microprocessor system of this embodiment,
The number of terminals on the microprocessor 50 can be reduced compared to the conventional one, improving the efficiency of terminal usage, making the microprocessor 50 more compact, and making the external wiring pattern closer and more complex due to the closeness of the terminals. This also makes it possible to solve problems such as difficulty in layout and improve the reliability of the entire system.

FIG. 3 is a schematic block diagram of a microprocessor system showing a second embodiment of the present invention. In the figure, common elements with those in FIG. 1 are given the same reference numerals.

This microprocessor system includes a microprocessor 50 and a shared memory 80, similar to the microprocessor system of FIG.

Here, the shared memory 80 stores the upper 16 bits of data DU
The data line for the lower 16 bits of data is connected to the DU bus child 53 via the data line for the DL, and the DL bus child 54 is connected to the DL bus child 54 through the data line for the lower 16 bits of data DL.
In addition, it is connected to the A bus terminal 55 via a 16-bit address line, to the WEL terminal rough via a write signal line, and to the RE terminal 58 via a read signal line. Furthermore, a host processor 90 and a third bidirectional buffer 100 are provided outside the microprocessor processor 0.

The host processor 90 has almost the same functions as the microprocessor 80 in FIG. It is connected to the H bus terminal 52 of the microprocessor 50.

The third bidirectional buffer 100 is operated by the supply of the switching signal CH, and has a function of selectively passing a signal, for example, and is connected to the external output terminal 60 via a signal line, and is connected to the host processor. The upper 16 bits of data DU of 90 and the data line of the upper 16 bits of data DU of shared memory 80 are connected to each other via 16 bit data lines.

In addition, in the microprocessor system shown in Fig. 3,
In the microprocessor 50, the selection signal SEL supplied to the switching circuit 68 is fixed at a high level (High). Further, the WEL terminal 57 is connected to the write signal line of the shared memory 80, and the WEU terminal 56 is unnecessary and is not connected to the shared memory 80.

Next, the operation will be explained.

Since the selection signal SEL input to the switching circuit 68 is at a high level, the switching circuit 68 outputs the switching signal CH to the external output terminal 6.
0 to the bidirectional buffer 100, the bidirectional buffer 100 functions (enables), and the bidirectional buffer 6
2 is in a disabled state.

When the microprocessor main body 51 is at rest for the first time,
The host processor 90, for example, stores data and programs (
or a command string) to the shared memory 80 (data transfer). This data transfer by the host processor 90 is performed, for example, as follows.

The host processor 90 outputs an address signal indicating the transfer destination address to the shared memory 80 side via the address buffer 63, and a write data signal of the lower 16 bits of data is output to the microprocessor 50 via the H bus terminal 52. and passes through the bidirectional buffer 61 to D.
The lower 1 data of the shared memory 80 via the L Baba child 54
Output to 6-bit DL. At the same time, the write data signal of the upper 16 bits of data I- from the host processor 90 is output to the upper 16 bits of data DU of the shared memory 80 via the bidirectional buffer 100 without passing through the microprocessor 50. . After this, the signal generation circuit 6
7 generates a write signal WEL, and the write signal WEL
When input to the shared memory 80 via the WEL terminal 57, each write data signal from the host processor 70 is taken into the shared memory 80.

When the data transfer from the host processor 90 to the shared memory 80 is completed, data processing by the microprocessor main body 5-L is performed in the same manner as in the first embodiment,
The processing results are stored in the shared memory 80.

When the microprocessor body 51 finishes processing the data,
The host processor 90 reads the processing results in the shared memory 80, for example, as follows.

The host processor 90 first outputs an address signal indicating the read destination to the shared memory 80 side via the address buffer 63, and the signal generating circuit 67 outputs the read signal RE to the shared memory 80 side.
It is output to the shared memory 80 side via the E terminal 58. Then, in response to the address signal, the read data signal of the lower 16 bits of data is inputted to the host processor 90 side via the bidirectional buffer 61 of the microprocessor 50 via the H bus terminal 2, and the read data signal of the upper 16 bits of data is inputted to the host processor 90 side via the H bus terminal 2. read data signals are input to the host processor 90 side via the bidirectional buffer 100, and the host processor 90 takes in these read signals and stores them in the shared memory 80.
The processing results are read from the .

This second embodiment has the following advantages.

In this embodiment, the microprocessor processor 0 is provided with an external output terminal 60, bidirectional buffers 61 and 62, and a switching circuit 68, and the external output terminal 60 is provided with a bidirectional buffer 10.
0 was connected. Therefore, the host processor 90 is
When configured with a processor for the host processor 90, the system can be configured without changing the configuration of the microprocessor 50, for example, with the H bus terminal 52 allowing only 16 bits for the data line.
can access the shared memory 80 in units of 32 bits.

Furthermore, the bidirectional buffer 100 is a microprocessor 5.
Since the microprocessor 50 is provided externally to the microprocessor 0 and is operated by receiving only the switching signal CH, the microprocessor 50 can be made smaller as in the first embodiment, and the density and complexity of the wiring pattern can be reduced. Furthermore, it is possible to eliminate difficulties in wiring layout due to wiring routing, etc., and improve the reliability of the entire system.

As can be seen from this embodiment, the microprocessor 50
A microprocessor system using this system improves the efficiency of terminal usage, provides compatibility with the host processor, and achieves high system reliability.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(I> The microprocessor systems of the first and second embodiments can be modified in various ways, including their configurations.

For example, the microprocessor 50 may have other circuit configurations added to it, the host processor 70.90 may be set to function as a bus driver, etc., and the shared memory 80 may have, for example, a dynamic It may also be configured with RAM or the like.

Further, in the above embodiment, a 32-bit system was explained, but the microprocessor system of the present invention
It is applicable to systems with arbitrary bit (long) width W (W is a positive integer).

(II) The microprocessor system of the above embodiment is exemplified as being composed of one microprocessor 50, one host processor 70 (or 90), and one shared memory 80. The host processor 70 (or 90) may have a complex system configuration, such as access from other microprocessors or host processor 70 (or 90) accessing multiple subsystems.

(III) In the above embodiment, a typical operation was illustrated, but the operation example can be changed as appropriate as the configuration of the microprocessor system is changed.

(Effects of the Invention) As described in detail above, according to the present invention, the microprocessor is provided with a first bidirectional buffer, a second bidirectional buffer, an external output terminal, and a switching circuit, and the external output terminal By simply connecting a third bidirectional buffer to the host processor, it is possible to connect the host processor to either the 2W bit width processor or the W bit width processor, thereby increasing the compatibility of the host processor. can get.

Furthermore, the microprocessor becomes more compact with fewer terminals, and the reliability of the entire system can be improved due to wiring and the like.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a microprocessor system according to a first embodiment of the present invention, FIG. 2 is a schematic block diagram of a conventional microprocessor system, and FIG. 3 is a block diagram of a conventional microprocessor system. FIG. 2 is a schematic configuration diagram of a microprocessor system showing a second embodiment of the invention. 50...Microprocessor, 51...Microprocessor main body, 60...External output terminal, 61...First bidirectional buffer, 62...Second bidirectional buffer, 68...Switching Circuit, 70.90...Host processor, 80...Shared memory, 100...Third bidirectional buffer, CH...Switching signal.

Claims (1)

[Scope of Claims] A microprocessor with a built-in microprocessor main body having a bit width of 1 or 2 W (W is a positive integer), a host processor having a bit width including a predetermined W bit,
In a microprocessor system comprising a shared memory having a 2W bit width and accessed exclusively by the microprocessor main body and a host processor, a predetermined W bit of the host processor is set to a lower or upper part of the shared memory. a first bidirectional buffer that connects to the W bit; a second bidirectional buffer that connects a predetermined W bit of the host processor to the upper or lower W bit of the shared memory based on a switching signal; an external output terminal to which a switching signal is supplied complementary to the buffer; and a switching circuit that outputs the switching signal to either the second bidirectional buffer or the external output terminal depending on the bit width of the host processor. A microprocessor system, characterized in that the microprocessor is provided with: 2. The microprocessor system according to claim 1, wherein the host processor is configured with a processor having the 2W bit width, and the predetermined switching signal of the host processor is determined based on a switching signal input via the external output terminal. A microprocessor system comprising: a third bidirectional buffer that connects W bits other than the W bits of the shared memory to upper or lower W bits of the shared memory, provided outside the microprocessor.