KR950006547Y1 - Process double time common memory access circuit - Google Patents

Abstract

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Description

Common memory access circuit in processor duplication

1A and 1B are access circuit diagrams of a common memory of a conventional processor.

2 is an overall configuration diagram of a common memory access circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

14, 24: common memory 11-13, 21-23: buffer

16, 26: Oagate 15, 25: Inverter

The present invention relates to a common memory access circuit in a case where the processor controlling the system is redundant, and in particular, a processor that effectively accesses common memory without affecting the operation of the counterpart processor when the counterpart processor is in operation. The present invention relates to a duplexer common memory access circuit.

In general, when constructing a system, the stability and reliability of the system are considered first. Above all, the redundancy of the processor that controls the entire system is important.

The true meaning of processor redundancy means that accessing the common memory without affecting the operation of the counterpart processor when the counterpart processor is in operation, and the active counterpart processor no longer performs its normal function due to system congestion or external factors. When it is not possible, the function is directly inherited and prevented from stopping the entire system operation and continuing normal operation.

Conventionally, when two processors access a common memory, two types of common memory access circuits are used, as shown in FIGS. 1A and 1B.

In the common memory access circuit shown in FIG. 1A, in order to access the common memory, both of the two redundant processors (CPUs) access the common memory. One of the two processors (CPUs) is operated by the master processor and the other. Is operated as a slave processor. In this circuit, buffers can be accessed so that signals such as address buses (AB), data buses (DB), and control buses (CB) of the master and slave processors do not collide with each other according to the club (QA). do.

In addition, in the common memory access circuit as shown in FIG. 1B, each processor (CPU) can access the divided pages of a common memory, one of the two processors (CPU) is operated as a master processor and the other is a slave processor. When enabled, the master processor floats the hardware flag (H / W FLAG) on the clock input terminal (CK) of the corresponding latch in time according to the time when it is enabled at the high potential of the hardware clock (+ 5V). A predetermined value input is written to select a page of a common memory. Thus, when dividing a page of memory into four pages, the master processor writes one or two pages and three or four pages, so that the processor can operate on both sides without affecting the operation of the counterpart processor.

As described above, since the processor is configured to access the common memory in accordance with the clock cycle by enabling the buffer using a hardware clock signal, the processor is excessively loaded when the program is executed, resulting in a poor program execution efficiency. There was a problem.

The present invention has been made in view of the above-described problems. In a redundant system, the processor reduces the load when the processor accesses the common memory to prevent an unexpected system down state such as system down. The purpose is to improve the stability and reliability of the system.

In order to achieve the above object, the present invention provides an address bus AB, a data server DB, and a control bus connected between the first processor 10 and the common memory 14 in a common memory access circuit during processor duplication. The page signal applied from the first processor 10 to the signal transmitted through the (CB) A first buffer 12 controlled according to the first processor 12 and a signal transmitted through an address bus AB, a data bus DB, and a control bus CB connected to the first processor 10. Active signal applied from 10) Signals transmitted through the address bus AB, the data bus DB, and the control bus CB connected between the second buffer 11 and the second buffer 11 and the common memory 14 controlled according to Transfer is performed through the address bus AB, the data bus DB, and the control bus CB connected between the third buffer 13, the second processor 20, and the common memory 24 controlled according to the control signal. A page signal applied from the second processor 20 The fourth buffer 22, which is controlled according to the present invention, is transferred through the address bus AB, the data bus DB, and the control bus CB connected between the second processor 20 and the second buffer 11. An active signal applied from the second processor 20 And a signal transmitted through the address bus AB, the data bus DB, and the control bus CB connected between the fifth buffer 21 and the fifth buffer 21 and the common memory 24. The sixth buffer 23 to control the control signal according to the control signal, and the active signal applied from the first processor 10 A first inverter 15 for inverting the signal, a signal applied from the first inverter 15, and a page signal applied from the second processor 20 The first oragate 16 outputting the result of the logical sum to the third buffer 13 side, and the active signal applied from the second processor 20 A second inverter 25 for inverting the signal, a signal applied from the second inverter 25 and a page signal applied from the first processor 10. The second OR gate 26 for outputting the resultant result of the logical sum as a control signal to the sixth buffer 23 side is provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The common memory access circuit according to the present invention includes the processor 10, 20, the buffers 11-13, 21-23, the common memories 14, 24, the inverters 15, 25, and the oragate as shown in the second diagram. 16, 26).

In FIG. 2, two processors 10 and 20 are shown. One of the two processors is currently operated as a master processor that performs normal operation and the other processor is a slave processor that performs standby operation. Slave Processor). For convenience of description, the processor 10 is defined as a master processor and the processor 20 is defined as a slave processor. The buffer 11 receives signals transmitted through the address bus AB, the data bus DB, and the control bus CD from the master processor 10. The buffer 12 controls the signals transmitted through the address bus AB, the data bus DB, and the control bus CB connected between the master processor 10 and the common memory 14. 10) from page signal The buffer 13 oragates a signal transmitted through an address bus AB, a data bus DB, and a control bus DB connected between the buffers 11 and 21 and the common memory 14. Control in accordance with the signal from (16). The buffer 21 transmits signals from the slave processor 20 through the address bus AB, the data bus DB, and the control bus DB connected between the buffers 11 and 13 and the slave processor 20. Active signal The buffer 22 controls the signals transmitted through the address bus AB, the data bus DB, and the control bus CB connected between the common memory 24 and the slave processor 20. Page signal from 20) The buffer 23 controls the signal transmitted through the address bus AB, data bus DB and CB connected between the buffer 21 and the common memory 24 to the oragate 26. Control according to signal from Inverter 15 is an active signal applied from the master processor 10 Is outputted to the oragate 16 side, and the oragate 16 is a signal applied from the inverter 25 and a page signal applied from the slave processor 20. Is outputted to the buffer 13 as a control signal.

The inverter 25 applies a signal applied from the slave processor 20 and a page signal applied from the master processor 10. Is output as a control signal to the buffer 23 side.

The common memory access circuit of the present invention configured as described above operates as follows.

First of all, in a system where two processor cards are mounted, a processor that is currently performing normal operation is called a master processor, and an operating state thereof is called an active state, and a waiting processor among the two processors is called a slave processor. The operating state is called a stand-by state. The common memories 14 and 24 are shared by two processors, that is, the master processor 10 and the slave processor 20. The two processors can access the common memory 14 and 24 by dividing them into two pages. When the page 1 is accessed, the page signal is accessed. Is used and page 2 is accessed Use In addition, the master processor 10 is a low-level active signal The slave processor 20 outputs a high level active signal. Outputs When the master processor 10 accesses the common memory 14, the page signal is supplied to the buffer 12 side. The buffer 12 is operated to access the common memory 14 through the address AB, the data bus DB, and the control bus CB. Level active signal By operating the buffer 11 by the page signal Is output to the oragate 26 side and the buffer 23 is operated by the oragate 26 to access the common memory 24 through the address bus AB, the data bus DB, and the control bus CB. can do. In addition, the slave processor 20 in the standby state can access only the common memory 24, and the page signal to the buffer 22 side. The common memory 24 can be accessed through the address bus AB, the data bus DB, and the control bus CB by operating the buffer 22 by outputting the. That is, the active master processor 10 has access to both the common memory 14 of page 1 and the common memory 24 of page 2 (where access means that the processor writes information to the memory and reads it simultaneously). The slave processor 20 in the standby state can only access the common memory 24 of page 1.

As described above, when the master processor 10 fails and the operation is stopped while the normal operation is performed while recording information on the operation status of the system performed by the master processor 10 in the common memories 14 and 24, the standby operation is performed. The slave processor 20 in the state is converted into an active state to serve as a master processor. When the slave processor 20 operates as a master processor, as described above, all of the common memories 14 and 24 are accessed. The master processor 10 directly takes the information on the operation status of the system recorded by the operation to perform the entire operation of the system without stopping.

As described above, according to the circuit of the present invention, when the processor that controls the entire system is redundant, the processor can reduce the load when accessing the common memory, thereby preventing the system from stopping unexpectedly. The stability and reliability of the can be further improved.

Claims (2)

The common memory access circuit for processor duplication includes: transmitting a signal transmitted through an address bus (AB), a data bus (DB), and a control bus (DB) connected between the first processor 10 and the common memory 14; 1 buffer 12 and the page signal applied from the first processor 10 The first processor 12 and the signal transmitted through the address bus (AB), data bus (DB)] and the control bus (CB) connected to the first processor 10 according to the control of the first processor Active signal applied from (10) And a signal transmitted through the address bus AB, the data bus DB, and the control bus CB connected between the second buffer 11 and the second buffer 11 and the common memory 14. Active signal applied from the first processor 10 And a signal transmitted through the address bus AB, the data bus DB, and the business CB connected between the second buffer 11 and the second buffer 11 and the common memory 14. The page signal applied from the second processor 20 The fourth buffer 22, which is controlled according to the present invention, is transmitted through the address bus AB, the data bus DB, and the business CB connected between the second processor 20 and the second buffer 11. An active signal applied from the second processor 20 A fifth buffer 21 for controlling according to the control, a sixth buffer 23 for controlling a signal transmitted between the fifth buffer 21 and the common memory 24 according to a control signal, and the eleventh processor Signal applied from 10 and page signal applied from the second processor 20 The OR signal is outputted to the third buffer 13 side as a control signal and the active signal applied from the second processor 20. A second inverter 25 for inverting the signal, the second inverter 25, a signal applied from the second inverter 25, and a page signal applied from the first processor 10. And a second orifice (26) for outputting the resultant result of the logical sum as a control signal to the sixth buffer (23) axis. The processor of claim 1, wherein a processor operating as a master processor among the first and second processors 10 and 20 is an active signal of a first level. Outputs a page signal , The processor which outputs all and runs as a slave processor has the second level active signal. Outputs a page signal A common memory access circuit for processor duplication, characterized in that only outputs.