JPH046029B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address and data bus interface circuit in a communication control device.

In general, a communication control device has a line control unit with a built-in DMA (direct memory access) function that inputs and outputs addresses and data in a time-sharing manner, and a bus for the line control unit and a bus for the central processing unit and main memory unit. It consists of a bus interface circuit that converts the interface. In such a communication control device, when converting the bus interface circuit into an IC or LSI in order to reduce the amount of hardware,
As the address and data bus width of a communication control device increases, the number of external terminals of the bus interface circuit increases, and it is necessary to divide the bus interface circuit into a plurality of parts. For this reason, conventionally, a bus interface circuit has been configured with a plurality of latch circuits each having a bus width of several bits and one bus control circuit, and these have been separately integrated into ICs.

FIG. 1 shows an example of a conventional configuration of this type of bus interface circuit. In FIG. 1, 1 is a line control section, 2 is a main memory section, 3 ₁ and 3 ₂ are latch circuits,
4 is an address/data common bus, 5 is an address bus, 6 is a data bus, 7 is a bus control circuit, 8 is a DMA control signal line, 9 is a latch circuit control signal line, 10 is a memory access signal line, 20 is a central processing The bus interface circuit is composed of a bus control circuit 7 and latch circuits 3 ₁ and 3 ₂ . That is, in FIG. 1, two sets of latch circuits 3 ₁ and 3 ₂ are provided for bit slicing the bus widths of the address bus 5 and data bus 6 of the main memory section 2 into two.
The bus control circuit 7 controls data transfer between the line control section 1 and the latch circuits 3 ₁ and 3 ₂ and between the latch circuits 3 ₁ and 3 ₂ and the main storage section 2 . The operation of FIG. 1 is as follows.

Write operation: The line control unit 1 instructs the bus control circuit 7 to write through the DMA control signal line 8, and first slices the write address into two bits and puts them on the address/data common bus 4. The bus control circuit 7 runs from the line control section 1 to the signal line 8.
Based on the DMA control signal provided through
The latch circuit 3 ₁ ,
3 ₂ , the write address on the address/data common bus 4 is latched into the latch circuits 3 ₁ and 3 ₂ and placed on the address bus 5 . Next, line control section 1
Similarly, the write data is sliced into two bits and placed on the address/data common bus 4, and the bus control circuit 7 is sent to the latch circuit 3 in the same way.
₁ and 3 ₂ and put it on the data bus 6. When the write address and write data are available on the address bus 5 and data bus 6, the bus control circuit 7 outputs a write signal to the memory access signal line 10 based on the DMA control signal given from the line control unit 1, and the main memory Access 2.

Read operation: The line control unit 1 instructs the bus control circuit 7 to read through the DMA control signal line 8, and also slices the read address into two bits and puts them on the address/data common bus 4. The bus control circuit 7 controls the latch circuits 3 ₁ and 3 ₂ using the latch circuit control signal line 9, latches the read address on the address/data common bus 4 to the latch circuits 3 ₁ and 3 ₂ , and latches the address bus 5. put it on.
At the same time, the bus control circuit 7 outputs a read signal to the memory access signal line 10 to access the main memory section 2. The read data from the main memory section 2 passes through the data bus 6, is sliced into two bits and latched into the latch circuits 3 ₁ and 3 ₂ , and then transferred to the address/data common bus under the control of the bus control circuit 7. The data is transferred to the line control unit 1 via 4.

As mentioned above, in conventional bus interface circuits, there are two types of IC units: bus control circuits and latch circuits, so when designing a new bus interface circuit, it is necessary to develop two types of ICs. The drawback was that development costs were high. Furthermore, since the bus control circuit is separated from the latch circuit, there is a drawback that the number of external terminals for each IC unit increases.

In order to eliminate the above-mentioned conventional drawbacks, the present invention configures a bus interface circuit using the same functional unit consisting of a latch circuit, a bus control circuit, and a selector circuit, as many as the number of bits to be sliced. , Examples will be described in detail.

FIG. 2 shows an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts. 11 is a memory read signal line for reading data from the main memory section 2;
2 is a memory write signal line for writing data to the main memory section 2; 13 is a selector for selecting either the memory read signal line 11 or the memory write signal line 12; Either the read signal line 11 or the memory write signal line 12 can be selected. 15 is a functional unit that constitutes a bus interface circuit.
This functional unit 15 is composed of a latch circuit 3, a bus control circuit 7, and a selector 13. The memory access signal line 10 consists of a memory read signal line and a memory write signal line, one of which is a functional unit 15.
The memory read signal line 11 is connected to the memory read signal line 11 by the switching terminal 14.
Take out the switching terminal 1 from the other functional unit 15.
4, the memory write signal line 12 is taken out. That is, each functional unit 15 uses a memory read signal line 11 or a memory write signal line 1 among the memory access signal lines 10 that access the main memory section 2.
However, it has a redundant circuit configuration in which both a memory read signal and a memory write signal are created within each functional unit, and the selector 13 uses only one of them. Here, the operation in FIG. 2 will be described assuming that the memory read signal line 11 is taken out from the upper functional unit 15 and the memory write signal line 12 is taken out from the lower functional unit 15.

Write operation: The line control unit 1 instructs the bus control circuit 7 of each functional unit 15 to write through the DMA control signal line 8, and first slices the write address into two bits and transfers the address/data common bus 4.
put it on. The bus control circuit 7 of each functional unit 15 controls its own latch circuit 3 through the latch circuit control signal line 9 based on the DMA control signal given from the line control section 1 through the signal line 8, and controls the own latch circuit 3 on the address/data common bus 4. The write address of is latched in the corresponding latch circuit 3 and placed on the address bus 5. Next, the line control unit 1 bit-slices the write data into two pieces and puts them on the address/data common badge 4, and in the same way, the bus control circuit 7 of each functional unit 15 sends them to its own latch circuit 3. Latch it and put it on data bus 6. When the write address and write data are available on the address bus 5 and data bus 6, the bus control circuit 7 of each functional unit 15 enables the memory write signal line 12, but since this is a write operation, the selector 13 controls the lower function. Memory write signal line 1 of unit 15
2 is selected and the main storage section 2 is accessed.

Read operation: The line control section 1 instructs the bus control circuit 7 of each functional unit 15 to read through the DMA control signal line 8, and slices the read address into two bits and puts them on the address/data common bus 4. Bus control circuit 7 for each functional unit 15
controls its own latch circuit 3 through a latch circuit control signal line 9, latches the read address on the address/data common bus 4 to the corresponding latch circuit, and transfers it onto the address bus 5. At the same time, the bus control circuit 7 of each functional unit 15 connects the memory read signal line 1
1 is assumed to be valid, but since this is a read operation, the memory read signal line 11 of the upper functional unit 15 is selected by the selector 13, and the main storage section 2 is accessed. The read data from the main memory section 2 passes through the data bus 6, is sliced into two bits, and is latched into the latch circuit 3 of each functional unit 15.
The data is transferred to the line control unit 1 via the address/data common bus 4 under the control of each bus control circuit 7.

Figure 2 shows an example in which two functional units are used in response to bit slicing the bus widths of the address bus 5 and data bus 6 into two. Needless to say, the number of units will also increase.

As explained above, according to the present invention, the bus interface circuit is divided into multiple functional units with the same circuit configuration, so by converting the functional units into ICs, the bus interface circuit can be completed using one type of IC. It has the advantage of being configurable. Furthermore, because only one type of IC is required to develop, IC development costs are reduced, and because multiple ICs of the same type are used in the bus interface circuit, the number of ICs produced increases, resulting in lower bus interface Ace circuit configuration
This has the advantage of lowering the cost of ICs. Also,
Since the functional units constituting the bus interface circuit include a latch circuit and a bus control circuit in pairs, there is an advantage that connections between the functional units are not required.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a conventional bus interface circuit, and FIG. 2 is a diagram showing an embodiment of the bus interface circuit of the present invention. 1...Line control unit, 2...Main storage unit, 3...Latch circuit, 4...Address/data common bus, 5
... Address bus, 6 ... Data bus, 7 ... Bus control circuit, 8 ... DMA control signal line,
9...Latch circuit control signal line, 10...Memory access signal line, 11...Memory read signal line, 1
2...Memory write signal line, 13...Selector,
14...Switching terminal, 15...Functional unit, 20...
Central processing unit.

Claims (1)

[Claims] 1 An address/data common bus that inputs and outputs addresses and data in a time-sharing manner, and a data write/data common bus.
Equipped with a DMA control signal line that instructs reading.
Line control unit with built-in DMA function, address bus,
A main memory bus consisting of a data bus and a memory access signal line for instructing data writing/reading, the address/data common bus, and the
In a bus interface circuit of a communication control device comprising a bus interface circuit that transfers data to and from a bus of the line control unit consisting of a DMA control signal line, the bus interface circuit comprises a plurality of bus interface circuits having the same configuration. Each functional unit circuit includes a latch circuit that latches bit-divided addresses and data, and a memory read signal and a memory write signal based on instructions from the DMA control signal line. A bus control circuit that controls data transfer between a control section and the latch circuit and between the latch circuit and the main memory section, and selecting either a memory read signal or a memory write signal generated by the bus control circuit. A bus interface circuit for a communication control device, comprising a selector circuit outputting to the memory access signal line.