JPS5842544B2 - Memory card block selection device - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a memory card in which memory such as an IC memory is configured into blocks of nK bytes, and several blocks can be configured on one board, and the memory area can be increased for each block. be.

Particularly, the present invention is characterized in that the number of memory blocks can be increased to a certain extent without restrictions with respect to this memory card.

The board that makes up the memory card is equipped with a circuit that indicates the status of the memory block, and this circuit sends the status signal to the memory book selection circuit on the central processing unit (CPU) side. It is possible to specify memory blocks according to the state.

For example, if the memory card configuration is such that one block is 8 bytes and up to 4 blocks can be added to one board, that is, up to 32 bytes (hereinafter abbreviated as KB), then 3
When increasing the size to 2 KB or more, an additional board is required.

Conventionally, when selecting this memory block, for example, if one program has a capacity of 5KB and another program has a capacity of 10KB, the absolute address of the memory card (the physical address of the memory card) is used in the CPU. ) and sends a signal specifying a predetermined memory block and an address signal to the memory card to specify the address.
Since the block is 8KB, write a 5KB program to the first memory block of the memory card and write it again.
A capacity of 0 KB is written following the above address, that is, it is written across the first memory block and the second memory block.

In other words, the CPU side described above simply converts the memory card's absolute address into an absolute address according to the step order of the program, sequentially selects the memory block area corresponding to the absolute address, and instructs the memory card side. It was done without any problems.

In the above example, the capacity of the first program is up to 5KB, so each step only specifies the first memory block, and similarly, the capacity of the next program is 1OKB, so the steps up to 3KB are The first memory block is pointed to, and then the first
Since the capacity exceeds the capacity of the second memory block, the second memory block is automatically designated for subsequent steps.

To explain this a little more with reference to the drawings, FIG. 1 shows a memory block selection method in a conventional memory card, which is roughly divided into a central processing unit (CPU) 1 and a memory part 2.

Further, the memory portion 2 has 8 KB as one memory block 4, and one board (memory card) 5 has four memory blocks 4A and 4B.

4C and 4D can be added respectively, and two boards 5A and 5
It shows what can be expanded up to B.

Therefore, the memory part 2 can be expanded from 8 KB to a maximum capacity of 64 KB.

The board 5A is connected to the CPU 1 via a connector 6A, and the board 5B is connected to the CPU 1 via a connector 6B.
It is connected to the.

CPIJl is E that outputs a memory block designation signal.

- E for specifying the memory block, having an output line of E7 and a signal line D for other signals such as address, data, R/W, etc.;

~E3 are connected to corresponding memory blocks 4A to 4D via connectors 6A, respectively.

That is, Eo is connected to 4A, El to 4B, and E2 to 4C.

Furthermore, E4 to E7 are connected to corresponding memory blocks 4E to 4H, respectively, via connectors 6B.

Furthermore, the signal wires are connected to the boards 5A, 5B through connectors 6A, 6B, respectively.

In such a configuration, if the memory block 4A is specified, E from the CPUI.

A logic "1" signal is output only to the line El to designate the memory block 4A, and similarly the El line is "1".
Then, memory block 4B is designated.

As described above, the CPU simply converts into absolute addresses of the memory part 2 according to the step order of the program and sequentially indicates the memory blocks corresponding to the absolute addresses, so as shown in FIG. In the case where the configuration in 2 has a capacity of 24 KB with only memory blocks 4A and 4B installed on the board 5A and only memory block 4E installed on the board 5B, for example, if a certain program has a capacity of 10 KB and another program Mo l0
If the capacity is KB and this is to be written to the memory part 2, the CPU 1 converts it to an absolute address of the memory part 2 and outputs the corresponding output line E.

- Since it only outputs an instruction signal to E7, the first l
E for a program with a capacity of 0KB.

Set the line to "1" to indicate memory block 4A,
When the capacity of the memory block 4A is exceeded, the E1 line is set to "1" to instruct the memory block 4B and then writing is performed.

Next, for another program with a capacity of 10 KB, the E1 line is set to "1" to indicate memory block 4B, and the program is written following the writing of the above program.
When the capacity of the memory block 4B is exceeded, the E2 line is set to "1" to indicate the memory block, but since there is no memory block connected to this E2 line, writing cannot be performed.

In other words, conventionally, the CPU 1 converts the absolute address of the memory part 2 and outputs the corresponding output line E.

-E7, it is not possible to add a memory block 4 as shown in FIG. 2, but the memory block must be connected to line E as shown in FIG.

, E, , E2... The only option was to connect and expand them in the order corresponding to them.

In other words, in a device that can connect up to two boards (memory cards) 5 consisting of 4 blocks each with 8 KB, it is only possible to add memory blocks as shown in the table below.

For this reason, in the past, it was only possible to add memory blocks as shown in the table above, and the methods of adding them were extremely limited, resulting in various inconveniences.

For example, the board is already equipped with a memory card with a capacity of 24KB (3 memory blocks), and a memory card with a capacity of 32KB
If you wanted to increase the memory capacity to 32 KB, you had to remove the board and replace it with a new memory card with a capacity of 32 KB.

This is because if an attempt was made to add a board with a capacity of 8 KB to a board with a capacity of 24 KB, the memory block arrangement would be similar to that shown in FIG. 2 above, and this would not be possible.

Therefore, there have been various problems in that increasing the number of memory blocks is expensive and the workability is very poor.

The present invention eliminates the above-mentioned drawbacks and allows memory block expansion with a degree of freedom such as, for example, simply adding a board with an 8KB capacity to a board with a capacity of 24KB to increase the memory capacity to 32KB. It was possible.

FIG. 4 is a diagram showing the configuration of the present invention, where 1 is a central processing unit (CPU), 2 is a part of memory, and 3 is a memory selection circuit installed in the CPUI.

The memory part 2 stores 8KB in one memory block 4.
One board (memory card) 5 has four memory blocks 4A, 4B, and 4C.

4D can be added to each, and two boards 5A.

It shows the one that can be expanded up to 5B.

The board 5A is connected to the memory selection circuit 3 of the CPU 1 via the connector 6A, and the board 5B is connected to the connector 6.
It is connected to the memory selection circuit 3 of the CPU 1 via B.

The memory selection circuit 3 outputs a memory block designation signal E.

- B7 output line and signal line D for other signals such as address, data, R/W, etc., and E for specifying the memory block.

- B3 are connected to the corresponding memory blocks 4A to 4D through the connector 6A, and E4 to E7 are connected to the corresponding memory blocks 4E to 4 through the connector 6B.
Connected to H respectively, and further signal lines are connected to connectors 5A and 6B.
are connected to the substrates 5A and 5B via the respective substrates 5A and 5B.

The boards 5A and 5B described above are equipped with block number designation circuits 7A and 7B that instruct the memory selection circuit 3 about the memory block status of each board.

These block number designating circuits 7A and 7B are B.

This B has an output line jBl.

, B1 indicates the memory block state.

FIG. 5 shows a specific configuration of the block number designation circuit,
The terminals of the Bo and B1 lines are connected to ground by printed wiring, and are also connected to the voltage source of the Bo and CC in the middle.

Therefore, B by connecting or disconnecting the B/, B//(7) portions of the printed wiring.

, B1 can have four different output states.

In other words, B when both the B' and F axis parts are connected.

. B1 is the logic rOJ, rOJ, and if only B' is disconnected, the logic is rlJ, rOJ, if only B'' is disconnected, the logic is "O", "1", and if both B' and B//G are disconnected, the logic is "1" , becomes "1".

The following table shows how these logical states correspond to the memory block states of the board 5.

Therefore, the output line B of the block number designation circuit 7A provided on the board 5A in FIG.

, B1 are respectively introduced into the memory selection circuit 3 via the connector 6A, and are output lines B of the block number designation circuit 7B provided on the board 5B.

, B1 is a status signal B from the block number designation circuit 7A whose board 5B is on the board 5A side.

, B1, so the memory selection circuit 3
There is no need to introduce it.

Further, in FIG. 4, S is introduced into the memory selection circuit 3.

-87 is a block selection signal after being converted by the CPU 1 into an absolute address of the memory part 2.

The memory selection circuit 3 is an output line B from the block number designation circuit 7A.

, B1 according to the block selection signal S.

-87 is the memory block designation signal E.

-B7, which is shown in FIG.

In FIG. 6, output B of the block number designation circuit 7A.

, B□ is "0", "0", that is, when the number of memory blocks on the board 5A is one as shown in the above table, the output line E is used for the "So" signal.

is selected, and output line E4 is selected for the “Sl” signal.
is B5 for "B2", B6 for "B3", r
B7 is selected for s4J, respectively.

Furthermore, when Bo and B1 are "1" and "0", the number of memory blocks on the board 5A is two, and E is equal to rsOJ.

, El for "Sl", B4 for "B2", "B
B5 is selected for "3," B6 is selected for "B4," and B7 is selected for "S.".

Below is B.

, B1 is "O", "1", "1" and "1" as shown in FIG.

FIG. 7 shows a specific configuration of the memory selection circuit 3 that performs the operation shown in FIG. 6 above.

In FIG. 1, output line B from the block number designation circuit.

, B1 are introduced into gates 10 to 13, respectively, and Bo
, B1 are respectively rOJ and rOJ, the gate 11 is conductive, and when rOJ and rlJ, the gate 13 is conductive, and
1” At “O”, the gate 10 is conductive and further rlJ
In rlJ, the gate 12 is conductive.

The output of the gate 11 is introduced into one input side of gates 14 to 17, respectively, and the output of the gate 10 is introduced to one input side of gates 18 to 2.
Furthermore, the output of gate 13 is connected to one input side of gate 2.
The output of gate 12 is input to one input side of gates 26 to 29, respectively.

And a block selection signal S.

is output line E. and the signal S1 is connected to the output line E
1 and the other input of gate 14, signal S2 is connected to output line E2 and the other input of gates 15 and 18, and signal S3 is connected to output line E3 and the other input of gate 16.1.
9 and 22, respectively.

Moreover, the signal S4 is the gate 17, 20, 23, 26
At the other input of the signal S, the gate 21, 24°27
The signal S6 is connected to the other input of the gate 25.28, and the signal S7 is connected to the other input of the gate 29.

On the other hand, the outputs of gates 14, 18, 22, and 26 are connected to output line E4 via gate 30, and gates 15,
The outputs of gates 19, 23, and 27 are connected to output line E through gate 31, the outputs of gates 16, 20, 24, and 2B are connected to output line E6 through gate 32, and gate 17゜21 ,
The outputs of 25 and 29 are connected via gate 33 to output line E7.

Therefore, output line B.

, B1 are rol, rOJ, gate 11 is conductive, gates 14 to IT are enabled, and signal S is output.

If there is an output line E. is selected, and when signal S1 is present, output line E4 is selected, and when signal S2 is present, output line E4 is selected.
5, when the signal S3 is present, the output line E6 is selected, and when the signal S4 is present, the output line E7 is selected.

In other words, the operations shown in FIG. 6 described above are performed sequentially.

To explain this operation a little more, as shown in FIG. 8, the configuration of the memory part 2 is that the board 5A is equipped with memory blocks 4A and 4B to have a capacity of 16 KB, and the board 5B is further equipped with a memory block 4E. is installed to increase the capacity by 8KB, the output line B from the block number designation circuit 7A of the board 5A.

, B1 to the logic state of Ill,roj.

In other words, B in Figure 5. Cut the line at part B'.

Therefore, in FIG. 7, gate 10 becomes conductive and gates 18 to 21 are enabled.

In this case, it is assumed that a certain program has a capacity of 10 KB and another program also has a capacity of 10 KB, and these programs are written to the memory part 2.

First, the CPU 1 converts the absolute address of the memory portion 2 into the corresponding block selection signal S.

~S7 is output.

In other words, for the first 10KB program, S
.

becomes "1" and the memory selection circuit 3 selects line E as shown in FIG.

Select and write to memory block 4A.

When the capacity of this memory block 4A becomes 8KB or more,
When Sl becomes "1", the memory selection circuit 3 selects the line E1 as shown in FIG. 7, and specifies the memory block 4B for writing.

Next, the CPU 1 similarly converts another 10 KB capacity program into an absolute address of the memory part 2, so that S becomes "1" and the memory selection circuit 3 selects the line E1 in the same manner as above. is selected, the memory block 4B is specified, and writing is performed following the above writing.

When the capacity of the memory block 4B reaches 8 KB or more, B2 becomes "1" and the block selection circuit 3 selects the line E2 and the line E4 via the gates 18 and 30 as shown in FIG.

However, since there is no memory block on line E2, line E4 is eventually designated and writing is performed in memory block 4E on board 5B.

That is, as shown in FIG. 2, this makes it possible to add memory blocks, which was not possible with the conventional system.

Therefore, following the memory block expansion configuration shown in FIG. 8 above, expansion configurations as shown in the table below can be made.

Comparing this table with the conventional expansion configuration table mentioned above,
It is clear that the configuration according to the present invention allows for more flexible memory expansion configuration.

In the above embodiment, the case where two memory cards on the boards 5A and 5B are added is described, but it is also possible to add three or four boards, and in this case, the second or second memory card can be added. Output line B from the memory number designation circuit on the second and third board.

. B1 are each connected to a memory selection circuit.

Furthermore, each of the above boards is equipped with a memory number designation circuit, but in the case shown in Figure 4, the second board 5B does not require a memory number designation circuit; Each board is equipped with the circuit so that it can be easily handled.

As described above, the present invention has a memory card in which the memory is configured into blocks of nK bytes, and this memo IJ block can be added to the board, and the memory block of the memory card is transferred from the central processing unit to the memory card. In this device, a block designation signal is sent to a predetermined memory block to specify an address, and the circuit board constituting the memory card is equipped with circuit means for deriving a status signal indicating the status of the memory block, and the CPU side is equipped with circuit means for deriving a status signal indicating the status of the memory block. It is equipped with a memory selection circuit that introduces a signal and switches the output line to specify a memory block according to the state of the memory block. Therefore, the memory selection circuit takes the state of the memory block into consideration when specifying a memory block. By doing so, it is possible to expand the memory blocks considerably, and the expansion of the blocks can be easily and inexpensively carried out, resulting in extremely beneficial effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional memory card memory block selection device, FIGS. 2 and 3 are block diagrams showing the memory block selection operation in the conventional device, and FIG. 4 is a block diagram of the memory card memory of the present invention. - a block diagram showing a block selection device; FIG. 5 is a circuit diagram showing a specific configuration of a memory number designation circuit according to the present invention; FIG. 6 is a construction diagram showing the operation of the memory selection circuit according to the present invention; FIG. 7 is a circuit diagram showing a specific configuration for the operation of FIG. 6, and FIG. 8 is a configuration diagram showing the operation of the apparatus of the present invention. 1...Central processing unit (CPU), 2...
・Part of memory, 3...Memory selection circuit, 4.
...Memory block, 5...Board (memory card), 6A and 6B...Connector, 7A and 7B...Memory number designation circuit, Eo
-E7...Output line for outputting a memory block designation signal, 5o-87...Block selection signal after being converted to an absolute address of a part of the memory.

Claims (1)

[Claims] 1. In a device that has a memory card in which the memory is configured into blocks of nK bytes so that the memory blocks can be added to the board, and addresses are specified from the central processing unit (CPU) to the memory blocks of the memory card,
A board constituting the memory card is equipped with circuit means for deriving a status signal indicating the status of the memory block, and the status signal is introduced into the CPU side to switch an output line for specifying the memory block according to the status of the memory block. A memory card block selection device characterized by being equipped with a memory selection circuit.