JPH09305483A - Memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform both 16-bit data simultaneous reading and writing and 8-bit writing by a simple circuit. SOLUTION: A microcomputer MCU connects to a RAM1 by a bit signal line of high order and to a RAM 2 by a bit signal line of low order. Then an OR circuit generates an OR signal between a select signal CS1 of a 1st address space and a select signal CS2 of a 2nd address space and the RAM1 is selected with the signal CSRAM1. The RAM2 connected to the data input/ output terminal of the MCU, on the other hand, is selected with the CS2. Further, an address of the RAM1 is selected with an address signal including the least significant digit bit among plural addresses. Consequently, the simple circuit consisting of only the ROM circuit can read and write 16-bit data simultaneously by using the RAM1 and RAM2 and writes and read 8-bit data simultaneously by using the RAM1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit and, for example, to a memory control circuit for supplying an optimum control signal and a backup power source to a memory connected to the outside of a microcomputer (micro control unit). .

[0002]

2. Description of the Related Art An external memory connected to a microcomputer is used as a stack memory or a working memory for temporarily storing data required when a central processing unit (hereinafter referred to as CPU) of the microcomputer operates, or an external memory. It is used as a backup memory to store unique adjustment data and information data such as operating time. For the external memory that stores the data, connect the power supply switching circuit between the battery for backup power supply and the power supply of the device,
Data is not lost even if the device is turned off. In addition, an external memory that stores data, a battery for backup power supply, and a power supply approval circuit for the power supply of the device are integrated to form a backup memory unit, and the microcomputer is connected via a connectable / separable connector. When connecting the printed circuit board (hereafter referred to as the microcomputer board) that is mounted and replacing the microcomputer board due to a failure of other components mounted on the microcomputer board, remove the backup RAM unit from the failed microcomputer board. ,
It is connected to a newly-replaced microcomputer board so that the stored data unique to the device will not be lost.

By the way, in the case of a conventional device which is not required to have high performance, one memory having an 8-bit input / output terminal is used as an external memory to simultaneously write and read 8-bit data. Therefore, when writing and reading 16-bit data, it is necessary to divide the data into 8-bit data in two steps, which requires processing time. On the other hand, in a device requiring high performance, a microcomputer having a 16-bit data input / output terminal for an external memory is used as described in Japanese Patent Laid-Open No. 7-84869, for example. The memory is connected to the upper 8-bit data input / output terminal, and the second memory is connected to the lower 8-bit data input / output terminal. Then, by connecting the upper write enable signal (WRHB) to the first memory and the lower write enable signal (WRLB] to the second memory, the microcomputer stores bytes in the first memory and the second memory. Data can be written in units of (8 bits) or in units of words (16 bits).

In such a device requiring high performance,
As shown in FIG. 4, a microcomputer MCU having a CPU capable of processing 16-bit data in parallel and having a 16-bit data input / output terminal for an external memory is used, and an 8-bit input / output terminal is used as an external memory. Two memories (RAM1 and RAM2) are used. And the first
Signal line (D
H) via the I / O terminal D8 of the upper 8 bits of the microcomputer
-D15, and the second memory RAM2 is connected to the lower 8-bit input / output terminals D0-D7 of the microcomputer MCU via the signal line (DL) for transmitting the lower 8-bit, and the microcomputer MCU is connected to the external memory. 16-bit data can be simultaneously written and read, and high-speed processing is performed.

[0005]

However, in the conventional device shown in FIG. 4, since writing is also performed in 8-bit data units, the write enable signal (WRB) from the CPU and the upper 8-bit data identification signal ( It is necessary to generate an upper write enable signal (WRHB) and a lower write enable signal (WRLB) from BHEB) and the least significant bit signal (AO) of the address signal and connect them to the first memory and the second memory, respectively. In addition, since the lower address area of this external memory is used as the backup memory and the upper address area is used as the stack memory and the working memory, these two external memories are used for backup power supply and the power supply of the device. Circuits must be connected to ensure that no data is lost if the device is interrupted in power. Therefore, 2 as stack memory or working memory
When a total storage capacity of 4 Kbytes and 8 Kbytes of backup memory, 32 Kbytes, is required, the backup memory unit includes two external memories and 16 signal lines for transmitting 16-bit data. 8
Book, DL: 8, AN: 14, RD: 1, WRH
B: 1 line, WRLB: 1 line, CS: 1 line, power supply of equipment not shown: 1 line, ground: 1 line, so 36 signals in total must be connected, so a 36-pin connector is required. You will need it.

A first object of the present invention is to provide a memory control circuit capable of simultaneously writing and reading 16-bit data and writing in 8-bit units with a simple circuit. A second object of the present invention is to provide a memory control circuit capable of holding data with a backup power supply for small letters. Further, a third object is to provide a removable memory control circuit which can be connected with a connector having a small number of pins and requires less parts training.

[0007]

According to a first aspect of the present invention, a microcomputer and a first memory connected to a data input / output terminal of the microcomputer via a signal line for transmitting a higher-order bit, To the data input / output terminal of the microcomputer,
Second connected through a signal line for transmitting lower bits
Memory, an address signal line for transmitting an address signal excluding the least significant bit among the addresses having a common number commonly connected between the microcomputer and the first memory and the second memory, and An address signal line connected between the microcomputer and the first memory, for transmitting an address signal of the least significant bit, and a first chip select signal indicating that the microcomputer has selected the first address space,
An OR circuit for obtaining a logical sum of a second chip select signal indicating that the microcomputer has selected the second address space and inputting the logical sum to the first memory, and between the microcomputer and the second memory The memory control circuit is provided with a chip select signal line which is connected and which transmits the second chip select signal, to achieve the first object. According to a second aspect of the present invention, in the memory control circuit according to the first aspect, when a power supply from the outside is cut off, a backup power source for holding data of the first memory, and an external power source are provided. The second object is achieved by including a power supply approval circuit that switches the backup power supply and supplies the power to the first memory. According to a third aspect of the present invention, in the memory control circuit according to the second aspect, a support body on which the first memory, the backup power supply, and the power support circuit are arranged, the support body, and the microcomputer. The connector that enables connection and disconnection of the above and a support body that integrates them are provided, and thus the third
Achieve the objectives.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a memory control circuit according to the present invention will be described in detail below with reference to FIGS. FIG. 1 shows a circuit configuration of a memory control circuit. In FIG. 1, the MCU is a microcomputer having a 16-bit data input / output terminal. The RAM 1 is a random access memory, which is a first memory having an 8-bit data input / output terminal and a capacity of 32 Kbytes. RAM
2 is also a random access memory, which is a second memory having an 8-bit data input / output terminal and a capacity of 32 Kbytes.

BATT is a lithium battery for a backup power source, and CNT is a power source switching circuit. The lithium battery (BATT) is connected to the power input terminal of the RAM 1 through the power switching circuit. Power switching circuit CNT
Compares the voltage of the power supply of the device (not shown) with the voltage of the lithium battery BATT, and the power with the higher voltage is stored in the RAM.
1 is supplied. For this reason, if the power of the device is cut off, the power of the lithium battery is supplied to the RAM 1, so that the data stored in the RAM 1 is not lost. The lithium battery BATT supplies electric power only to RAM1 and does not supply electric power to RAM2. Therefore, it is possible to hold data for the same period with a battery having a half capacity as compared with the case where power is supplied to both RAM1 and RAM2.

DH is a signal for transmitting the higher 8 bits D8 to D15 of the 16-bit data, and connects the microcomputer MCU and the data input / output terminals D0-D7 of the RAM1. DL is a signal for transmitting the lower 8 bits D0 to D7 of the 16-bit data, and connects the microcomputer MCU and the data input / output terminals D0-D7 of the RAM2.

AN is a signal line for transmitting an address signal of A1 to A14 bits among a plurality of address signals output from the microcomputer MCU, and an address input terminal A1 of the RAM1.
-A14 and address input terminals A0-A13 of RAM2
Connected in common. A0 is a signal line for transmitting the address signal of the least significant bit of the address signal, and RAM1
Is connected to the address input terminal A0. WR is a write enable signal issued by the microcomputer MCU, and RAM1 and RA
The write control signal input terminals WE of M2 are commonly connected. RD is a read permission signal issued by the microcomputer MCU, and is commonly connected to the output control signal input terminals OE of the RAM1 and RAM2.

CS1 is a backup memory selection signal output from the microcomputer MCU, and CS2 is a stack memory and working memory selection signal output from the microcomputer MCU. Both of the selection signals CS1 and CS2 are activated by a memory selection signal generation circuit (not shown) in the microcomputer MCU by using the upper 3 bits A21 to A23 of the 24-bit address signal of the CPU. For example, the memory selection signal generation circuit is A23 = 0, A22
When = 0 and A21 = 1, it is determined that the backup memory address space is selected, and the selection signal CS1 is activated. Further, the memory selection signal generation circuit is
When 23 = 0, A22 = 0 and A21 = 1, it is determined that the stack memory address space or the working memory address space is selected, and the selection signal CS2 is activated.

OR is an OR circuit, which takes the logical sum of the selection signals CS1 and CS2 and selects the memory 1 selection signal (CSRA).
M1), and the chip select input terminal C of RAM1
Connect to E. RAM2 chip select input terminal CE
The selection signal CS2 is connected to.

Next, the operation of the embodiment thus configured will be described. First, when the microcomputer MCU writes or reads data to or from the stack memory or the working memory, in order to perform high-speed processing, this address space writes or reads data at 16 bits at the same time. An internal bus controller (not shown) is set. Also, the microcomputer M
When the CU writes or reads data to or from the backup memory, the bus controller is set so that this address space simultaneously writes or reads data of 8 bits.

Simultaneous writing and reading of 16-bit data has the effect of speeding up the processing. Of the external memories, the frequency of writing and reading is high and the data length is 8
It is a memory used as a stack memory or a working memory that is longer than a bit in most cases, and a memory used as a backup memory that is not so is a case of simultaneous writing and reading of 8-bit data and the processing speed of the entire device. Are equivalent.

When the microcomputer MCU writes to or reads from the stack memory or the working memory,
First, the CPU sends an even address signal (A0 = A0 =) in the stack memory address space or the working memory address space.
0) is generated, and a memory selection signal generation circuit (not shown) of the microcomputer MCU activates the selection signal CS2. The bus controller in the microcomputer MCU informs the CPU that data is read and written in 16-bit units in this address space.

Since the selection signal CS2 becomes active, the selection signal CSRAM1 which is the output of the logical sum of the selection signal CS1 also becomes active. The RAM1 is selected by the selection signal CSRAM1 and changes from A0 to A
The memory at the address indicated by 14 is selected. RAM2
Also, the selection signal CS2 becomes active to bring it into the selected state, and the memories at the addresses indicated by A1 to A14 are selected.

When writing to the stack memory or the working memory, the microcomputer MCU outputs an upper 8-bit data signal to DH, a lower 8-bit data signal to DL, and WR becomes active.
It is written in the memory of the selected address of RAM1 and RAM2. On the other hand, at the time of reading, RD becomes active, the upper 8-bit data signal is output from RAM1 to DH, the lower 8-bit data signal is output from RAM2 to DL, and the microcomputer MCU reads it.

When the microcomputer MCU writes to or reads from the backup memory, the CPU
Generates an address signal (A23 = 0, A22 = 0, A21 = 1) in the backup memory address space, and the memory selection signal generation circuit activates the selection signal CS1. The bus controller inside the microcomputer MCU informs the CPU that data is read and written in 8-bit units in this address space. Since the selection signal CS1 becomes active, the selection signal CS2
The selection signal CSRAM1 which is an output obtained by taking the logical sum of The RAM1 is selected by the CSRAM1 and the memories at addresses A0 to A14 are selected. At this time, the RAM 2 is in the non-selected state.

When writing to the backup memory,
An 8-bit data signal is output from the microcomputer MCU to DH, the WR is activated, and the data is written in the memory of the selected address of the RAM1. At the time of reading, RD becomes active, an 8-bit data signal is output from RAM1 to DH, and the microcomputer MCU reads it.

A23, A22 and A21 are 0, 0,
When the selection signal CS1 is 1, the selection signals CS2 are active when A23, A22, A21 are 0, 1, 0,
8K bytes of the lower address of RAM1 is used as a backup memory and 24K bytes of the higher address is used as a stack memory or a working memory. Therefore, as shown in FIG. The address value of the CPU that can be used as the stack memory or the working memory is 402000h to 407FFEh. Also, the upper 16 Kbytes of RAM2 are not used, and a 16 Kbyte capacity RAM is sufficient, but in general 16 Kbyte memory is not commercially available, and a larger commercially available 32 Kbyte capacity memory is used. ing.

Next, FIG. 2 will be described. RAM1 is the above-mentioned first memory, BATT is the above-mentioned lithium battery for backup power supply, CNT is the above-mentioned power supply switching circuit, and CN1 is a connectable / separable connector for connecting to the microcomputer MCU. These are integrated by a support body to form a backup memory unit, which can be integrally attached to and detached from the microcomputer MCU board. CN2 is installed on the board of the microcomputer MCU and has a connector C
It is a connector connected to N1. The board of the microcomputer MCU has the microcomputer MCU shown in FIG.
R circuit is installed. The number of signal lines passing through the connectors CN1 and CN2 is DH: 8 and AN: 15
Book, RD: 1, WR: 1, CSRAM 1: 1, power supply for device (not shown): 1 and ground: 1 for a total of 28. Therefore, CN1 and CN2 can use a small connector of 28 pins. Moreover, since the backup memory unit has only the RAM 1 as the memory, the unit can be made small.

As described above, according to this embodiment, the microcomputer (MCU) and the data input / output terminal of the microcomputer (MCU) are connected via the signal line (DH) for transmitting the higher-order bits. The first memory (RAM1), the first chip select signal (CS1) indicating that the microcomputer (MCU) has selected the first address space, and that the microcomputer (MCU) has selected the second address space. Of the second chip select signal (CS2) indicating the logical OR by the OR circuit and selected by the first memory select signal generated, and the microcomputer (MCU) via the signal line (DL) transmitting lower bits. The second memory (RAM2) connected to the data input / output terminal is selected by the second chip select signal (CS2), and the address of the first memory is selected from the plurality of addresses. By selecting with an address signal including a significant bit, simultaneous writing and reading of 16-bit data using the first memory and the second memory and the use of the first memory can be performed by a simple circuit including only the OR circuit. In addition, a memory control circuit of a microcomputer capable of simultaneously writing and reading 8-bit data and performing high-speed processing can be obtained at low cost. Further, by supplying the power of the backup power supply (BATT) to the first memory (RAM1) only when the power supply from the outside is cut off, it is possible to retain the data for the same period with a battery having a small capacity, The backup memory device can be obtained at a small size and at low cost. In addition, the first memory (RAM
1), a backup power supply (BATT), a power supply switching circuit (CNT), and a connector (CN1) are integrated by using a support body to form a backup memory unit, thereby achieving miniaturization. it can.

[0024]

According to the invention described in claim 1, it is possible to perform simultaneous 16-bit data write, read and write in 8-bit units with a simple circuit.
According to the invention described in claim 2, data can be held by the backup power supply for small letters. According to the invention described in claim 3, it is possible to provide a removable memory control circuit which can be connected with a connector having a small number of pins, and which requires less parts training.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an external configuration of a memory control circuit of the above.

FIG. 3 is an explanatory diagram showing a memory map.

FIG. 4 is a circuit configuration diagram of a conventional memory control circuit.

[Explanation of symbols]

MCU Microcomputer OR OR circuit RAM1 memory RAM2 memory BATT Lithium battery for backup power supply CNT Power supply switching circuit DH Signal for transmitting higher 8 bits D8 to D15 DL Signal for transmitting lower 8 bits D0 to D7 AN address Signal line that transmits A1 to A14 bits of the signal A0 Signal line that transmits the address signal of the least significant bit of the address signal WR Write permission signal issued by microcomputer MCU RD Read permission signal issued by microcomputer MCU CS1 Backup issued by microcomputer MCU Memory selection signal CS2 microcomputer MCU outputs stack memory and working memory selection signal

Claims (3)

[Claims] 1. A microcomputer, a first memory connected to a data input / output terminal of the microcomputer via a signal line for transmitting an upper bit, and a lower bit to a data input / output terminal of the microcomputer. A second memory connected via a signal line for transmitting, and a least significant bit of the multiple addresses which are commonly connected between the microcomputer and the first memory and the second memory. An address signal line for transmitting an address signal other than the above; an address signal line for transmitting an address signal of the least significant bit connected between the microcomputer and the first memory; and the microcomputer selecting the first address space. And a first chip select signal indicating that the microcomputer has selected the second address space is ORed to obtain the first memory. An OR circuit for input to said microcomputer and connected between said second memory, said memory control circuit, characterized in that it and a chip select signal line for transmitting a second chip select signal. 2. When the power supply from the outside is cut off, the backup power supply for holding the data in the first memory, and the external power supply and the backup power supply are switched to be supplied to the first memory. The memory control circuit according to claim 1, further comprising: 3. A support for arranging the first memory, the backup power supply, and the power support circuit, a connector for connecting and disconnecting the support and the microcomputer, and these are integrated. The memory control circuit according to claim 2, further comprising: