JPH0512883A - Sequential memory - Google Patents

Abstract

PURPOSE:To obtain a sequential memory which can set the different bit widths between the input and output data. CONSTITUTION:The switch circuits 18a and 18b are provided with (m) pieces of switches 18a1-18am and 18b1-18bm respectively. Then a switch circuit 18c contains (m) pieces of changeover switches 18c1-18cm in order to connect an input buffer 14a or an output buffer 14b to an input/output buffer 16. The switches 18a1-18am and 18b1-18bm of both circuits 18a and 18b are turned on and off by the signal received from a control-signal generating circuit 20. Thus the number of signal. lines are set for both input/output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential memory capable of continuously accessing data.

[0002]

2. Description of the Related Art In recent years, due to remarkable progress in semiconductor integration technology, memory capacity has been increased, and recently, with the diversification of needs, only a memory having a mere read-out (or read-out at any time, write-once as needed) function has been available. Instead, multifunctional memory has been put to practical use. FIG. 3 is a schematic block diagram of a conventional sequential memory. The sequential memory shown in FIG. 3 has a memory cell array 52 and a data input terminal 56.
a and a data output terminal 56b, an input bus 62a and an output bus 62b, and an input buffer 64a and an output buffer 64b for temporarily storing data. In the conventional sequential memory, generally, the number of signal lines of the input bus 62a and the output bus 62b is configured to be equal.

When writing data in the memory cell array 52, the first data is written in a predetermined position in the memory cell array 52, the following data is written in the column direction following the previous data, and one column is written. When each column is moved to the next column when it is full, writing is performed in the same manner. When reading data from the memory cell array 52, for example, the input n-bit data is output one by one in the written order. Therefore, the written n-bit data is read as it is as n-bit data.

[0004]

In recent information processing techniques, in order to perform optimum data processing, there are increasing cases where data is processed with different bit widths on the same system. However, in the conventional sequential memory, since the number of signal lines used in the input bus 62a and the output bus 62b is equal, it is difficult to realize a sequential memory in which the bit width of input data is different from the bit width of output data.

The present invention has been made under the above circumstances, and an object thereof is to provide a sequential memory capable of changing the bit width of input data and the bit width of output data.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a sequential memory for continuously accessing data to memory cells arranged in a matrix having an input bus and an output bus. A switch means for connecting / disconnecting each signal line constituting the input bus and the output bus, and a control means for controlling connection / disconnection of each signal line by the switch means are provided, and data is arranged in a row direction of the memory cells. It is characterized by writing.

[0007]

According to the present invention, the switch means is turned on and off by the control means to set the number of signal lines to be used for the input bus and the output bus. Further, since data is written in the row direction of memory cells arranged in a matrix, the bit width of data to be written or read at one time can be changed according to the number of signal lines of the input bus and the output bus. it can.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a sequential memory which is an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of its input / output circuit. The sequential memory shown in FIG. 1 has a memory cell array 2 in which memory cells are arranged in a matrix, an input / output circuit 4 for inputting / outputting data, and a data input / output terminal 6. Data is sequentially written in the row direction of the memory cell array 2. 1-bit data is stored in each memory cell, and m is stored in one row as a whole.
Bit data is stored.

The input / output circuit 4 includes a common data bus 10 and
Input bus 12a having a plurality of signal lines for input data
And an output bus 12 having a plurality of signal lines for output data
b, and an input buffer 14 for temporarily storing input data
a and an output buffer 14 for temporarily storing output data
b, the input / output buffer 16 for temporarily storing the input / output data and timing the operation speed, and the switch circuit 18
a, 18b, 18c and control signal generation circuit 20
Consists of. Input bus 12a and output respectively to the bus 12b of the m signal lines 12a ₁ ~12a _m, 12b ₁ ~12
b _m is provided, and each switch circuit 18 is correspondingly provided.
There are also m switches 18a _{1 to} 18a _m , 1 for a and 18b.
8b ₁ ~18b _m is provided. Switch circuit 18
c has m switching switch 18c ₁ ~18c _m for connecting one of the input buffer 14a and an output buffer 14b to the output buffer 16. The input buffer 14a and the output buffer 14b are each of m bits.

In the sequential memory of this embodiment, the switch circuit 18 is provided on the input bus 12a and the output bus 12b.
a, 18b are provided, and the number of used signal lines of the input data and the output data can be set in advance by turning on / off the switch circuits 18a, 18b by a signal generated from the control signal generating circuit (control means) 20. it can. The switch circuit 18c also turns on and off by the control signal generating circuit 20 of the changeover switch 18c ₁ ~18c _m is controlled.

Next, the operation of accessing the sequential memory configured as described above will be described. First,
The switch circuit 18 is controlled by the control signal generation circuit 20.
Set ON / OFF of a, 18b, and 18c. For example, eight switches 18a ₁ in the switch circuit 18a
The ～18A ₈ is turned on, the 16 switches 18b ₁ ～18B ₁₆ in the switching circuit 18b to the ON state. The switch circuit 18c is at the time of input of the data, the changeover switch 18c ₁ ~18c ₈ corresponding to the signal lines that is in the ON state in the switch circuit 18a is turned on, when the output of the data, the signal line which is in the ON state in the switch circuit 18b Corresponding changeover switches 18c _{1 to} 18c
_{Turn 16} on. This is to prevent data from being input to unused signal lines.

When data is written to the memory cell array 2, 8-bit data D _{1 to} D ₈ is sent to the input buffer 16 by the switch 18c, and the common data bus is sent via the switches 18a _{1 to} 18a ₈ of the switch 18a. The data is written in a predetermined position of the memory cell array 2 through 10. In the memory of this embodiment, each data is written sequentially in the row direction, so that the input buses 12a ₁ to 1a 1
The data D _{1 to} D ₈ sent via 2a ₈ are written in predetermined positions in the row direction in the memory cell array 2. When the next data is written, the previous data D _{1 to} D ₈ is 1
The word is moved in the row direction. In this way, 8-bit data is sequentially stored in the memory cell array 2 as shown in FIG.
Written in Further, as the data is written, the already written data D _{1 to} D ₈ etc. are sequentially sent downward in the column direction.

Next, when reading data from the memory cell array 2, the control signal generating circuit 20 turns on the switches 18b _{1 to} 18b ₁₆ of the switch circuit 18b, and the switch 18c is connected to the output buffer 14b side. .. Switch circuit switches 18b _{1 to} 18b
The _16, of the m data stored on the bottom line is the output terminal of the memory cell array 2, the data D ₁ to D ₁₆ is output to the output buffer 14b via the output bus 12b ₁ ~12b ₁₆ respectively. Furthermore, the data D ₁ to D ₁₆ are outputted through the output buffer 16 and the switch circuit 18c to the data input-output terminal 6. These data D _{1 to} D
₁₆ is externally read as 16-bit width data. In this way, at the same time the data D _{1 to} D ₁₆ are read out,
The memory cell array 2 is formed by the read data D _{1 to} D _16.
The vacant storage area generated in the inside is the subsequent data D _{17 to} D _32.
16 bits of data are sequentially read out in the same manner.

In the sequential memory according to the present embodiment, data can be sequentially written in the memory cell array in the row direction so that a maximum of m bits of data can be read at a time via the output bus. Also, the switch circuit 1
Since the number of signal lines used in the input bus 12a and the output bus 12b can be changed by 8a and 18b, the bit width of the input data and the bit width of the output data can be changed according to the number of used signal lines. it can. Therefore, the sequential memory of this embodiment is effective when processing data of different bit widths on the same system. In the above embodiment, the case where the data input / output terminal having the data input terminal and the data output terminal in common is used has been described, but the present invention is not limited to this, and the data input / output terminal is The input terminal and the data output terminal may be separately provided. In this case, since it is not necessary to switch the data signal line between the data input and the data output, the switch circuit 18c can be omitted.

[0015]

As described above, according to the present invention, the number of used signal lines of the input bus and the output bus is set by the switch means provided on the input bus and the output bus and the control means for turning on and off the switch means. Moreover, by sequentially writing the data in the row direction of the memory cells, it is possible to provide a sequential memory capable of changing the bit width of the input data and the bit width of the output data.

[Brief description of drawings]

FIG. 1 is a diagram for explaining how to access a sequential memory according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of an input / output circuit of a sequential memory which is an embodiment of the present invention.

FIG. 3 is a diagram for explaining how a conventional sequential memory is accessed.

[Explanation of symbols]

 2 memory cell array 4 input / output circuit 6 data input / output terminal 10 common data bus 12a input bus 12b output bus 14a input buffer 14b output buffer 16 input / output buffer 18a, 18b, 18c switch circuit 20 control signal generation circuit

Claims (1)

Claim: What is claimed is: 1. A sequential memory which has an input bus and an output bus, and successively accesses data to memory cells arranged in a matrix, wherein the input bus and the output bus are configured. A sequential memory comprising: switch means for connecting / disconnecting each signal line; and control means for controlling connection / disconnection of each signal line by the switch means, and writing data in the row direction of the memory cells.