JP2973895B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device comprising a memory array divided into a plurality of memory blocks.

[0002]

2. Description of the Related Art The storage capacity of a semiconductor memory device has been increasing with higher integration. Further, logic circuits other than memory control can be incorporated in a semiconductor memory device, and are widely used. In this case, in order to suppress an increase in die size, a method of inputting / outputting data from one side of a memory block has been adopted.

Referring to FIG. 3, which shows a conventional semiconductor memory device in blocks, the conventional semiconductor memory device includes memory arrays 1 and 2, Y decoders 3 and 4 corresponding to each of the memory arrays 1 and 2, and It includes X decoders 5 and 6 corresponding to each of the memory arrays 1 and 2, an I / O bus 37 commonly connected to the memory arrays 1 and 2, a Y decoder output line 9, and an input / output circuit 39.

An input / output circuit 39 is connected to the I / O bus 37 and performs data amplification and output, a data latch circuit 393 for data latching, and write data for the chip input / output circuit to the I / O bus 37. And a write buffer 392 for outputting the same.

Next, the operation of the conventional semiconductor memory device will be described with reference to FIG.
Activating one Y switch for the / O bus 37,
One sense amplifier is connected to the / O bus 37. In response to this, in the read operation, the data amplifier 391 is activated to read data on the I / O bus 37. In the write operation, the write buffer 392 controls the I / O bus 3
7, data is written to the sense amplifier and the memory cell.

The connection of the memory array 2 to the I / O bus 37 will be described with reference to FIG. 4 showing a part of the memory cell array 2. The memory array 2 includes a memory cell 23 for storing information, and a sense amplifier 22. A Y switch 21 for connecting the sense amplifier 22 and the I / O bus 37 in response to activation of the output of the Y decoder 4, a bit line 25,
An output line of the X decoder 6 for selecting the memory cell 23, that is, a word line 24 is provided.

In a typical dynamic memory, 1
In the memory arrays, the number of sense amplifiers connected to the I / O bus is 512. Thus, the number of sense amplifiers connected to one I / O bus of the semiconductor memory device of the type including the two memory arrays 1 and 2 shown in FIG.
It reaches 024. As a result, the floating stray capacitance and the like cannot be ignored, which is a hindrance to the high-speed operation.

As a countermeasure against this, it is conceivable to provide a plurality of I / O buses. However, as described above, since the I / O is performed from one side of the memory block, an increase in die size cannot be avoided.

[0009]

In the conventional semiconductor memory device described above, the number of sense amplifiers to be connected to one memory array increases as the capacity of the memory block increases due to the higher integration of the memory. Inevitably, the stray capacitance of the I / O bus is increased, which has a drawback of hindering high-speed operation.

In addition, providing a plurality of I / O buses as a countermeasure has a disadvantage that the die size is increased.

[0011]

A first semiconductor memory device of the present invention has external input / output terminals intensively arranged on one side of a semiconductor chip, and a plurality of memory cells are arranged in a row and column direction. in dynamic semiconductor memory device comprising a first memory cell array which is disposed away from the external input and output terminals, and a second memory cell array arranged in the vicinity of the external input and output terminals, said first memory cell That
A first I / O bus for transmitting the data of
A first data output circuit for outputting data of the first memory cell array connected to the I / O bus is disposed in the vicinity of said first memory cell array, said second Memorise
Transmitting the data of the first array and the first data
Before connecting to the input / output circuit and passing through this first input / output circuit
And a second memory cell for transmitting data of the first memory cell array.
An I / O bus connected to the second I / O bus;
De together with a vicinity of the memory cell array is disposed in the vicinity of the external input and output terminals of said second memory cell array
Data and the first memo via the second I / O bus.
And a second data input and output circuits for input and output of the Riseruarei data is constructed.

A second semiconductor memory device according to the present invention has external input / output terminals intensively arranged on one side of a semiconductor chip, and a plurality of memory cells are arranged in a row and column direction. In a dynamic semiconductor memory device including a first memory cell array arranged at a distance and a second memory cell array arranged near the external input / output terminal, the dynamic semiconductor memory device is arranged near the first memory cell array. A first memory cell array for data input / output;
And a first data input / output circuit connected to the first data input / output circuit for transmitting data of the first memory array.
An I / O bus, a data latch circuit for latching data of the first data input / output circuit, and a second data input / output circuit arranged near the second memory cell array and the external input / output terminal. A second I / O circuit connected to the data latch circuit and the second data input / output circuit for transmitting data of the second memory cell array and data of the first memory cell array held in the data latch circuit, respectively. / O bus, wherein the first memory cell array has first and second memory blocks, and the second memory cell array has third and fourth memory blocks, respectively. At the time of an access cycle, each of the first and third sets of memory blocks or the second and fourth sets of memory blocks is simultaneously accessed to access the first and third memory blocks. Read data of a third memory block is held in the data latch circuit, and at the time of a second access cycle, data held in the data latch circuit is passed through the second I / O bus and the second input / output circuit. And output.

[0013]

FIG. 3 shows an embodiment of the present invention.
Referring to FIG. 1, which is similarly denoted by a block with common reference characters / numerals attached to common components, the semiconductor memory device of the present embodiment shown in FIG. 2, Y decoders 3, 4 and X decoders 5, 6
, Y decoder output line 9, and memory arrays 1 and 2.
2 respectively, dedicated I / O buses 7 and 8, an input / output circuit 10 corresponding to the I / O bus 7 and an output terminal connected to the input end of the I / O bus 8, and an I / O bus 8 And an input / output circuit 11 having an output terminal connected to an input / output terminal of the chip via a wiring.

For convenience of explanation, the memory array 2 is arranged near or near the external input / output terminals arranged on one side of the chip as described above, while the memory array 1 is separated from the external input / output terminals. At the far end.

Next, the operation of the present embodiment will be described with reference to FIG.
Outputs the Y decode signal to the Y decoder output line 9 by the Y decoder 3 and selects one of the sense amplifiers connected to the I / O bus 7. This output data is I / O
The data is transmitted to the input / output circuit 10 via the bus 7 and is controlled by the input / output circuit 10 at the time of writing. Therefore, the capacity load of the I / O bus 7 is I / 2 compared to the conventional I / O bus 37.

The data on the I / O bus 7 is connected to the I / O bus 8 by the input / output circuit 10 and is input / output to / from the input / output circuit 11 via the I / O bus 8. Performs input / output of data with input / output terminals. At this time, the I / O buses 7 and 8 are separated from each other by the input / output circuit 10,
Since the capacity load is half of that of the conventional I / O bus 37, high-speed operation is possible. In addition, since access to the memory array 1 is performed via the I / O bus 8 of the memory array 2 without newly providing a data bus, it does not cause a significant increase in die size.

On the other hand, access to the memory array 2 is performed by operating the input / output circuit 11 for the I / O bus 8. At this time, the input / output circuit 10 connected to the input / output I / O bus 8 is in a high impedance state, and does not have any influence on the I / O bus 8.

Next, a second embodiment of the present invention will be described with reference to FIG. 2, which is a block diagram in which constituent elements common to FIG. The difference from the first embodiment is that two memory blocks 101 and 10 are used instead of the memory arrays 1 and 2 respectively.
2A and memory arrays 1A,
2A, Y decoders 301, 302, 401, and 402 corresponding to these memory blocks 101, 102, 201, and 202 in place of the Y decoders 3 and 4, respectively, and data between the input circuit 10 and the I / O bus 8. That is, a latch 12 is further provided.

Next, the operation of this embodiment will be described with reference to FIG. 2. The memory is required to increase the transfer speed of continuous data. Therefore,
At the time of accessing the memory, the memory blocks 101 and 201 of the memory arrays 1A and 2A are operated simultaneously,
Similarly, the memory blocks 102 and 202 are operated simultaneously. First, the data in the memory block 201 is transferred to the input / output circuit 1
1 and the memory block 101
Are operated via the input / output circuit 10. During a read operation, data is read by the input / output circuit 10 and the result is held in the latch circuit 12. Subsequently, in the next cycle, the data of the latch circuit 12 is read by the input / output circuit 11. In the subsequent cycle, data is read from block 202 of memory array 2A, and block data of memory block 102 is similarly read out to latch 1
Latch to 2. By repeating the above operations, high-speed data transfer can be realized without a significant increase in die size.

[0020]

As described above, the semiconductor memory device of the present invention comprises a first data input / output circuit for a first memory cell array, a first I / O bus, and a second memory cell array. And a second I / O bus connected to the first and second data input / output circuits, respectively. Access to the memory array is performed via an I / O bus connected from the input / output circuit of the near-end memory array via the I / O line of the near-end memory array to the input / output circuit of the far-end memory array. By doing, I /
There is an effect that the load capacity of the O bus is significantly reduced, high-speed operation is enabled, and an increase in die size can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the semiconductor memory device of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional semiconductor memory device.

FIG. 4 is a block diagram showing details of a memory array of FIG. 3;

[Explanation of symbols]

1, 2, 1A, 2A Memory array 3, 4, 301, 302, 401, 402 Y decoder 5, 6 X decoder 7, 8, 37 I / O bus 9 Y decoder output line 10, 11, 39 Input / output circuit 12 Data latch 21 Y switch 22 Sense amplifier 23 Memory cell 24 Word line 25 Bit line 391 Data amplifier 392 Write buffer

Claims (1)

(57) [Claims] 1. A first memory cell array having external input / output terminals intensively arranged on one side of a semiconductor chip, a plurality of memory cells arranged in rows and columns, and arranged away from the external input / output terminals And a second memory cell array disposed in the vicinity of the external input / output terminal, wherein the dynamic memory device is disposed in the vicinity of the first memory cell array for data input / output of the first memory cell array. A first data input / output circuit, a first I / O bus connected to the first data input / output circuit and transmitting data of the first memory array, and a first data input / output circuit A data latch circuit for latching data, a second data input / output circuit arranged near the second memory cell array and the external input / output terminal, A second I / O bus connected to the second data input / output circuit for transmitting data of the second memory cell array and data of the first memory cell array held in the data latch circuit; The first memory cell array includes first and second memory blocks, and the second memory cell array includes third and fourth memory blocks. At the time of memory access, the first memory cell array includes the first and second memory blocks. 1, a third set of memory blocks or the second set
Each of the sets of the fourth memory blocks is simultaneously accessed to hold the read data of the first or third memory block in the data latch circuit, and to hold the data held in the data latch circuit in the second access cycle. A semiconductor memory device which outputs via a second I / O bus and the second input / output circuit.