JP3138460B2 - Data writing / reading method for semiconductor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory configured to write or read data at a specified address.

2. Description of the Related Art Conventionally, an example of this type of semiconductor memory will be described with reference to FIGS.

FIG. 5 is a block diagram of a static random access memory including memory cells of 32768 × 8 bits.

This memory is configured to input and output 8-bit data in one cycle, and to store 3 bits specified by address signals A0 to A14 input to the address buffer.
It is configured to write or read data to one address (address) of 2768. The signal ▼ is a signal for activating the memory, and controls the memory so that writing or reading can be performed at a low level. The signals ▼ and ▼ are control signals for writing and reading, and control is performed so that writing can be performed at a low level and reading can be performed at a high level. ▲ ▼ is an output enable signal. When a low level signal is input, the output terminal is enabled to enable a read operation.

DI / O1 to DI / O8 are data input / output signals, which are used as input of write data or output of read data.

The write or read operation of the memory will be described focusing on an I / O bus portion for accessing data to a memory cell.

FIG. 6 shows a column decoder, which is configured to be able to access 8-bit data at a time to a memory cell.
I / O bus, transfer gate (sense switch),
FIG. 3 is a circuit diagram showing a part of a digit line.

I / OB0, I / OB to I / OB7, I / OB are complementary I / O
This is an I / O bus that inputs and outputs signals in phase with input and output data.
I / OB to I / OB where signals of opposite phase are input / output to / OB0 to I / OB7
Consists of a total of 16. M0 to M are memory cells,
D0, D to D7, D are digit lines for accessing the memory cells M0 to M7, and Q0, Q to Q7, Q are the digit lines to which the memory cells M0 to M7 are connected.Complementary I / O bus I / OB0 , I / OB
Transfer gates (sense switches) connected to .about.I / OB7, I / OB, on / off controlled by the SSl signal output from the column decoder CDl.

In the case of writing, externally input write data is
Amplified by input data control circuit, complementary I / O bus I
/ OB0, I / OB to I / OB7, I / OB and transfer gates (sense switches) Q0, Q to Q7, Q controlled by the output signal SSl of the column decoder CDl selected by the column address signal , And write data is transferred to the digit lines D0, D to D7, D corresponding to the selected column.

When the word line connected to the row decoder selected by the row address signal goes to the selected level, data is written to the 8-bit memory cell corresponding to the address of the selected row / column.

In the case of reading, data of a memory cell connected on a word line selected by a row address signal is transmitted to a digit line, and a transfer gate (sense switch) of a selected column specified by a column address, for example, Q0, Q
To Q7 and Q, and the complementary I / O buses I / OB0 and I / OB to I
/ OB7, transmitted to I / OB, the data is amplified by the output data control circuit, and when the output is enabled
It is output as read data from DI / O1 to DI / O8 terminals.

As described above, in the case of a semiconductor memory configured to access a plurality of bits of data to a memory cell by a conventional one-cycle write or read operation, a signal line of an I / O bus is written or read at a time. It is necessary to prepare according to the number of bits to be read. For example, 32768 shown in FIG.
In the case of a × 8-bit memory, if the I / O bus is configured as a complementary type, a total of 16 signal lines are required.
The I / O bus runs for a length corresponding to one side of a two-dimensionally configured memory cell array.

[Problems to be solved by the invention]

The conventional semiconductor memory described above requires an I / O bus consisting of a total of 16 signal lines in the case of an 8-bit configuration. In a semiconductor memory requiring such a large number of signal lines, this I / O bus is used. The area required for bus layout increases, and the use of fine processes, etc., increases the area of the entire chip even if peripheral circuits are made smaller and highly integrated. There is a disadvantage that it occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory in which the number of signal lines of an I / O bus is smaller than that in the related art, and therefore the area required for the layout of the I / O bus is small.

[Means for solving the problem]

The data write / read method of the semiconductor memory according to the present invention includes a first memory cell selected by a predetermined address signal and a second memory cell selected by the predetermined address signal.
Memory cells, a first digit line for accessing the first memory cell, a second digit line for accessing the second memory cell, an I / O bus, and the first A first transfer gate connecting the digit line to the I / O bus, a second transfer gate connecting the second digit line to the I / O bus, and supply of the predetermined address signal. After the first transfer gate is turned on in response to the I / O bus and the first digit line is connected, the second transfer gate is turned on and the I / O bus and the second And a connection means for connecting the digit lines.

[Action]

Since the number of signal lines of the I / O bus is reduced, the area required for the layout of the I / O bus can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, comprising a column decoder of a semiconductor memory, an I / O bus, a transfer gate (sense switch), and part of a digit line.

As in the conventional example shown in FIG. 5, it is configured such that 8-bit data can be accessed to a memory cell in one write or read cycle.

I / OB0, I / OB to I / OB3, I / OB are complementary I / O buses multiplexed according to the present invention, and I / OB0 to I / OB for inputting and outputting signals in phase with the input / output bus. I / O that signals in and out of phase with OB3
It is composed of a total of eight OB to I / OB. M0 to M7 are memory cells, D0, D to D7, D are digit lines for accessing the memory cells M0 to M7, and Q0, Q to Q7, Q are digit lines D0 to which the memory cells M0 to M7 are connected. , D〜D7, D
And a transfer gate (sense switch) connecting the complementary I / O buses I / OB0, I / OB to I / OB3, I / OB,
ON / OFF is controlled by the signal SSl output from the column decoder CDl, the multiplexing control signal CDE0 and the signal CED1, and the signals SSI10 and SSI20 which are ANDed by the AND circuits AND1 and AND2. Ie transfer gate
Q0, Q to Q3, Q are controlled by the SSI10 signal and the I / O bus I / OB
0, I / OB to I / OB3, I / OB. Also, the transfer gates Q4, Q to Q7, Q are controlled by the SSI20 signal, and the I / O buses I / OB0, I / OB to I / OB3, I / OB
Connected to each other.

Next, the operation of the present embodiment will be described. First, in the case of writing, eight bits of externally written data are fetched. When writing to a memory cell, the fetched write data is divided into upper four bits and lower four bits. That is, first, the complementary I / O buses I / OB0, I / OB to I / O
4 bits of upper write data (WD0 to WD3)
), The column decoder output signal SSl and the multiplexing control signal CDE0 are set to the selected level, the transfer gates Q, Q0 to Q3, and the on / off control signal SS110 of the Q are set to the selected level, and the transfer gates Q, Q0 to Make Q3 and Q conductive. As a result, first, the write data of the upper 4 bits is loaded on the bit lines D0, D to D3, D of the selected column, and writing is performed on the memory cell on the word line selected by the row address signal. Next, the multiplexing control signal CDE0 is not selected, the transfer gates Q0, Q to Q3, Q are turned off, and the lower 4 bits (I / OB0, I / OB to I / OB3, I / OB) ( WD4 to WD7). After that, the multiplexing control signal CDE1 is set to the selection level, the on / off control signal SSI20 of the transfer gates Q4, Q to Q7, Q is set to the selection level, and the transfer gates Q4, Q
To Q7, Q are made conductive, the lower 4 bits of write data are placed on the bit lines D4, D to D7, D of the selected column, and writing is performed on the memory cells on the selected word line. This completes the writing of 8 bits of write data.

Next, in the case of reading, the data of the memory cell on the word line selected by the row address signal is transferred to the digit line, and the column decoder output signal SSl selected by the column address signal and the multiplex control signal CDE0 are selected. To set the signal SS110 to the selected level. As a result, the transfer gates Q0, Q to Q3, Q (RD0 to RD3
) Read data is I / O bus I / OB0, I / OB to I / OB
3, Transferred to I / OB3. Thereafter, the read data is amplified and latched by a latch circuit for upper 4-bit data.

Next, the multiplexing control signal CDE0 is deselected, the transfer gates Q0, Q to Q3, Q are turned off, and the other multiplexing control signal CDE1 is set to the selected level, and the signal SSl2
Set 0 to the selection level. As a result, the transfer gates Q4, Q to Q7, Q are turned on, and the lower 4 bits on the digit line are turned off.
The read data of bits (RD4 to RD7) is transferred to I / O bus I
/ OB0, I / OB to I / OB3, I / OB, similarly amplify the read data and latch it with the lower 4 bit latch circuit. When all the 8 bit read data are available, Output data from the data input / output terminals DI / O1 to DI / O8.

The outline of the operation of the present embodiment has been described above. An example of the configuration of the peripheral circuit section relating to data input / output with the I / O bus will be described with reference to FIG. 2, and the timing relationship between the external control signal and the internal signal will be described. Will be described with reference to FIG.

The circuit shown in FIG. 2 includes a write system circuit for transferring write data to the I / O bus, and a read system circuit for amplifying and latching data from the I / O bus. DF0 to DF7 are D-type flip-flops for latching write data (WD0 to WD7) input from the outside, and are latched by inverted signals of the ▲ ▼ signals. Output signals of the D-type flip-flops DF0 to DF7 are input to input terminals of data selectors DS0 to DS3. Here, the output signals of WD0 to WD3 are the data selector DS
The signals are input to the D0 terminals of 0 to DS3, and the output signals of WD4 to WD7 are input to the D1 terminals of the data selectors DS0 to DS3, respectively. MP
The WC1 and MPWC2 signals are selection signals for signals input to the D0 and D1 terminals of the data selectors DS0 to DS3.When the MPWC1 signal is at the selected level, the signal input to the D0 terminal is output from the Y terminal, and the MPWC2 signal is output. At the selection level, a signal input to the D1 terminal is output from the Y terminal. The data output from the Y terminal is the write amplifier WA0-W
When input to A3 and the write amplifier enable signal WAE is on, signals in-phase and out-of-phase with the input are sent to the I / O bus I / OB
Output to 0, I / OB to I / OB3, I / OB. When the write amplifier enable signal WAE is off, the write amplifiers WA0 to WA3
Are configured to be high impedance.
Write data on the I / O bus is written to the designated memory cell through the transfer gates Q0 to Q as described in the embodiment of FIG. The read data on the I / O bus is amplified by the data amplifiers DA0 to DA3, and the output signals are D-type flip-flops DF8 to DF1.
5 is input to the data input terminal D. At this time, the output signals of the data amplifiers DA0 to DA3 are D-type flip-flops DF8 to DF8.
F11 data input and D-type flip-flops DF12 to DF15
Is input to each data input. The first latch signal MPRC1 is input to the clock input terminals CK of the D-type flip-flops DF8 to DF11, and the second latch signal MPRC2 is input to the clock input terminals CK of the D-type flip-flops DF12 to DF15. Read data RD0 to RD7 are output from the data output terminals Q of the D-type flip-flops DF8 to DF15.

The timing relationship between the external control signal and the internal signal based on the example of the peripheral circuit shown in FIG. 2 will be described with reference to FIG. When the signal ▼ changes to low level, the chip enters the selected state. The signal ▼ indicates an example in which reading is performed in the first half of the cycle and writing is performed in the second half. The signal ▲ ▼ is in an output enable state only at the time of reading. First, address signals A0 to A14 are input, and read and write addresses are designated. The word line specified by the row addresses A0 to A8 becomes the selection level, and the contents of the memory cell connected to the word line are transferred to the digit line. Further, the column decoder output specified by the column addresses A9 to A14 becomes the selection level. At this time, the multiplexing control signal CDE0 outputs the selection level, the transfer gates of the upper four bits of data RD0 to RD3 are turned on, and the upper four bits of data are transmitted on the I / O bus. This data is amplified through the data amplifiers DA0 to DA3 and latched by D-type flip-flops DF8 to DF11 at the rising edge of the signal MPRC1. Thereafter, the signal CDE0 turns off, and the multiplexing control signal CDE1 instead outputs the selected level. As a result, the transfer gate for the lower 4 bits of data in the selected column is turned on, and the lower 4 bits of read data are transmitted on the I / O bus. This data is amplified through data amplifiers DA0-DA3 and latched by D-type flip-flops DF12-DF15 at the rising edge of MPRC2 signal.
When the MPRC2 signal rises, valid data output from this memory element is started.

When the read operation is completed, the signal ▼ becomes high level to perform the write operation, the data output is prohibited, and the input of write data becomes possible. In this example, the write data is configured to be input as valid data when the signal 信号 falls. The valid write data is latched by D-type flip-flops DF0 to DF7 in response to a signal opposite to the signal ▲. Thereafter, the upper four bits of data WD0 to WD3 are selectively output by the data selectors DS0 to DS3 by the MPWC1 signal, and the write amplifier WA0 is output.
Through WA3 to the I / O buses I / OB0, I / OB to I / OB3, I / B. Thereafter, the multiplexing control signal CDE0 goes to the selection level, the transfer gate of the upper 4 bits of data is turned on, the write data is transmitted to the digit line, and the writing to the memory cell is performed. When the writing of the upper 4 bits is completed, the signals MPWC1 and CDE0 become non-selected, and instead, the signal MPWC2 becomes the selection level. As a result, the lower four bits of data WD4 to WD7 latched by the D flip-flops DF4 to DF7 are selectively output by the data selectors DS0 to DS3, and similarly I / O is passed through the write amplifiers WA0 to WA3.
The signals are transmitted to the O buses I / OB0, I / OB to I / OB3, I / OB. Thereafter, the multiplexing control signal CDE1 goes to the selection level, the lower 4 bits of the data transfer gate is turned on, and the write data is transmitted to the digit line, whereby the lower 4 bits of data are written to the selected memory cell. Done. When the writing of the lower 4 bits of data is completed, the signals MPWC2 and CDE1 are deselected and a series of writing operations is completed. The operation of reading and writing has been described with reference to the timing chart of FIG. 3. However, depending on the case, the address may be changed in the middle of a cycle and another new cycle may be started, as in the case of address access. In this case, the start of another new cycle may be detected by the address change detection circuit, and the same operation may be repeated thereafter.

FIG. 4 shows a column decoder according to a second embodiment of the present invention;
I / O bus, transfer gate (sense switch),
FIG. 3 is a circuit diagram of a circuit constituted by a part of a digit line. As in the first embodiment shown in FIG. 1, the memory cell is configured so that 8-bit data can be accessed in one write or read cycle. 1 is different from FIG. 1 in that the I / O bus is not made to be of a complementary type, but is constituted by one line per 1-bit data, and one digit line is constituted by one line of memory cells. Where you are. Such a configuration can be applied to a dynamic memory device.

I / OB0 to I / OB3 are multiplexed I / O buses, M10 to M17, M20
To M27 are memory cells, D10 to D17, D20 to D27 are digit lines for accessing the memory cells M10 to M17, M20 to M27, respectively, and Q10 to Q17 are digit lines D10 to D17 to which the memory cells M10 to M17 are connected. Transfer gates that connect the I / O buses I / OB0 to I / OB3, and Q20 to Q27 are memory cells M20 to M
Digit lines D20 to D27 to which 27 is connected and I / O bus I / OB0 to
The transfer gate that connects I / OB3, AND11 is the multiplexing control signal CDE0 and the signal output from the column decoder CDl1
Transfers the logical product signal SSl12 of SSl1 to transfer gates Q10 to Q1
An AND circuit that outputs a logical product signal SSl12 of the multiplex control signal CDE1 and the signal SSl1 output from the column decoder CDl1 to the transfer gates Q14 to Q17, AND21 is a multiplex control signal CDE0 and a column AND circuit that outputs a logical product signal SSl21 of the signal SSl2 output from the decoder CDl2 to the transfer gates Q20 to Q23, AN
D22 is an AND circuit that outputs a logical product signal SSl122 of the multiplexing control signal CDE1 and the signal SSl2 output from the column decoder CD12 to the transfer gates Q24 to Q27.

The operation is the same as that of the first embodiment shown in FIG. 1. Write data or read data is divided into upper 4 bits and lower 4 bits, and a selected bit line is accessed through an I / O bus. In the case of a dynamic memory device, the number of memory cells connected to one digit line is limited. Therefore, in the case of a dynamic large-capacity memory element, the number of columns is particularly increased, and the direction in which the columns change In this case, the I / O
By multiplexing the buses and reducing the number of buses, there is an advantage that the effect of reducing the chip area is great.

In recent dynamic memory devices, complementary I / O buses are often used in order to increase the operation speed and stability, and the effect of the present invention can be said to be greater in that respect.

In the first and second embodiments, an example has been described in which the number of I / O buses in a memory for inputting / outputting 8-bit data is set to half that of the conventional 4-bit memory. Needless to say, the number of I / O buses can be increased or decreased. In particular, when the number of I / O buses is 1 / m (m is an integer of 2), the number of accesses to the memory cells may be divided into m times.

〔The invention's effect〕

As described above, according to the present invention, in a semiconductor memory configured to write or read n bits (n is an integer of 2 or more) in one write or read cycle, I / O buses are multiplexed by time division. By performing data writing and reading with data, the number of I / O buses can be reduced, the chip area required for the layout of the I / O buses can be reduced, and a low-cost semiconductor memory can be realized. It is particularly effective for a memory having an input / output terminal having a multi-bit configuration. In addition, the data fetched from a data input terminal such as an image memory is converted into a multi-bit configuration by serial-parallel conversion to be written into a memory cell, and the data read from the memory is read. The present invention is also effective for a memory or the like in which bit-structured data is converted from parallel to serial and output from a data output terminal. In this case, a serial-parallel converter and a parallel-serial converter may be added to the data input / output circuit in addition to the embodiment described with reference to FIGS.
Access to the memory cells may be performed by external control in units of blocks subjected to serial-parallel conversion.

[Brief description of the drawings]

FIG. 1 is a column decoder showing a first embodiment of the present invention;
I / O bus, transfer gate (sense switch),
FIG. 2 is a circuit diagram of a circuit constituted by a part of a digit line, FIG. 2 is a configuration example of a peripheral circuit section relating to data input / output with an I / O bus according to the present invention, and FIG. 3 is a diagram of a semiconductor memory embodying the present invention. Timing chart of external control signal and internal signal, 4th
FIG. 5 is a circuit diagram showing a second embodiment of the present invention, and FIG.
FIG. 6 is a block diagram of an 8 × 8-bit static random access memory, and FIG. 6 is composed of a column decoder, an I / O bus, a transfer gate, and part of a digit line used in the conventional memory shown in FIG. FIG. CDl, CDl1, CDl2 ... column decoder SSl, SSl1, SSl2 ... column decoder output, AND1, AND2, AND11, AND12, AND21, AND22 ... and circuit, CDE0, CDE1 ... multiplex control signal, SSl10, SSl20, SSl11, SSl12, SSl21, SSl22 ... Transfer gate drive signal, I / OB0, I / OB to I / OB7, I / OB ... I / O bus, Q0, Q to Q7, Q, Q10 to Q17, Q20 to Q27: Transfer gate, D0, D to D7, D, D10 to D17, D20 to D27 ... Digit line, M0 to M7, M10 to M17, M20 to M27 ... Memory cell, WD0 to WD7 ... Write data, DF0 to DF15: D-type flip-flop, DS0 to DS3: Data selector, MPWC1, MPWC2: Data selector control signal, WA0 to WA3: Write amplifier, WAE: Write amplifier enable signal, WE: Write enable signal , DA0 to DA3: Data amplifier, MPRC1, MPRC2: Read D-type flip-flop control signal, RD0 to RD7: Read data, ▲ ▼: Chip select signal , A0~A14 ...... address signal, ▲ ▼ ...... output enable signal, DI / O1~DI / O8 ...... data input and output signal.

Claims (2)

(57) [Claims] A first address selected by a predetermined address signal;
Memory cells, a second memory cell selected by the predetermined address signal, a first digit line for accessing the first memory cell, and a second digit line for accessing the second memory cell. The second digit line and the I /
An O bus, a first transfer gate connecting the first digit line to the I / O bus, a second transfer gate connecting the second digit line to the I / O bus, The first transfer gate is turned on in response to the supply of the predetermined address signal, and the I / O
After connecting the O bus and the first digit line, the second transfer gate is turned on, and the data writing / writing of the semiconductor memory is provided with connection means for connecting the I / O bus and the second digit line. Read method. A first digit line connected to the I / O bus and read out on the I / O bus via the first digit line;
First data holding means for storing the information of the memory cell of the second type, and the second memory cell connected to the I / O bus and read out on the I / O bus via the second digit line 2. The apparatus according to claim 1, further comprising: a second data holding unit that stores the information of the first and second types; and an output control unit that simultaneously outputs the information stored in the first and second data holding units to the outside. Data writing to semiconductor memory
Read method.