JPH06124585A - Semiconductor memory device and its write-in and read-out device - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines, to attain a high density packaging when a flopy disk and a hard disk are replaced with a semiconductor memory, and to increase the transfer speed comparing with the semiconductor memory of a conventional serial access type by allowing an address input terminal to be shared with a data input terminal. CONSTITUTION:Plural address counters 14, 15, 16 having the same bits as that of an address data input/output terminal 12 and capable of parallel-inputting are provided. Those plural address counters are connected in series, the parallel input terminals 18 of the address counters are connected to the address data input/output terminal. Addresses are selected continuously by count-ups and a head address of a continuous read-out is loaded to address counters via the address data input/output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a sequential access type semiconductor memory device and an address / data input / output method.

[0002]

2. Description of the Related Art Addresses in conventional semiconductor memory
Data input / output methods include a parallel access type and a serial access type.

The parallel access type is provided with the same number of data input / output terminals as the number of bits forming one word, an address input terminal of the number of bits capable of designating the total capacity, and a control terminal for controlling the input / output of data. .

At the time of writing / reading, the writing / reading address is inputted to all address input terminals, and one word of data is inputted / outputted in parallel from the data input / output terminal.

The serial access type has a 1-bit address / data shared input terminal, a 1-bit data output terminal, and a control terminal for controlling input / output of address / data, regardless of the number of bits forming one word. Prepare

At the time of writing / reading, first, the leading address for writing / reading is serially input to the address / data sharing input terminal bit by bit, the same number of times as the number of address bits, and then from the data output terminal in advance in terms of the memory configuration. Data of a predetermined number of words is serially input / output bit by bit.

[0007]

As a substitute for a floppy disk or a hard disk, when a large-capacity sequential access type high-speed auxiliary storage device is constructed by using a large number of semiconductor memories, the conventional semiconductor memory device has the following structure. There are problems as described.

The parallel access type requires a large number of signal lines such as a plurality of address lines, a plurality of data lines, and a few control lines. Therefore, the area occupied by the signal lines becomes large, and it becomes difficult to mount the semiconductor memory on the wiring board at a high density.

In particular, when the chip-on-board mounting is used, an extra area for the package is not required, so that the wiring area of the signal line is increased and the utilization efficiency of the mounting area is reduced as compared with the chip area.

Furthermore, when a semiconductor memory is used as a substitute for a hard disk, only the leading address for writing and reading is required to access the memory, and after that, the addresses are continuously increased and it is decided. It suffices to read the data of the number of words. This is called sequential access.

In the parallel access type semiconductor memory,
Since it is necessary to input the address for each 1-word data input / output, it is wasteful.

In the serial access type, since only one address / data common input terminal line, one data output terminal line, and a few control terminal lines, which are a small number of signal lines, can be used, It occupies a small area and is advantageous for high-density mounting. Further, since the serial access type memory can be accessed sequentially, it is not necessary to input the address many times.

However, in the serial access type, since the address input and the data input / output are carried out bit by bit, the data transfer rate is lowered.

For connection with a computer,
A conversion circuit from serial to parallel is required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a semiconductor memory device having a small number of signal lines, high-density mounting and a high data transfer rate, and an address
And a data input / output method.

[0016]

In order to achieve the above object, the present invention employs the following configurations and methods.

The semiconductor memory according to the present invention has a memory array, an X decoder, a Y decoder, an I / O buffer, an address / data input / output terminal, and the same number of bits as the address / data input / output terminal. It is equipped with multiple address counters capable of parallel input with, and these multiple address counters are connected in series, and the parallel input terminals of the address counter are connected to the address / data input / output terminals, and all addresses are counted up. Are continuously selected, and the start address of continuous reading is loaded into the address counter through the address / data input / output terminal.

The semiconductor memory writing / reading method according to the present invention is provided with the same number of address / data input / output terminals as the number of bits forming one word. When an address is input, the address is divided into word units for input. 1 for data input / output
Input and output in word units.

The semiconductor memory writing / reading method according to the present invention is provided with address / data input / output terminals whose number is an integer fraction of the number of bits forming one word. Input is divided into the number of terminals, and when inputting / outputting data, data is divided into the number of address / data input / output terminals and input / output.

[0020]

In order to solve the drawback of the serial access type, that is, the reduction of the data transfer rate, data input / output is performed by the number of bits forming one word. That is, data input / output is performed in parallel. Since the data is input in parallel, the data transfer speed becomes faster than when the data is input serially bit by bit.

On the other hand, in order to prevent an increase in the number of signal lines, which is a drawback of the parallel access type, the input of the address is shared with the data input / output terminal, and when the number of bits forming the address is larger than that of the data, the data Divide into the number of bits and input multiple times. Since the address input terminal is also used as the data input / output terminal, the address input terminal becomes unnecessary and the number of signal lines is reduced. Therefore, the area occupied by the signal line is reduced.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a semiconductor memory device according to the present invention,
It is a circuit diagram for explaining a writing and reading method.

In FIG. 1, as an example, 1024 × 10
FIG. 2 is a circuit block diagram showing a 1 megabit sequential access type semiconductor memory device using a memory array 10 having a 24-bit structure and each word being composed of 8 bits. In FIG. 1, the numbers attached to the signal lines connecting the blocks and the signal lines connecting the address / data input / output terminals to the blocks represent the number of signal lines.

Address / data input / output terminal 12 for writing / reading data, I / O buffer 13, and Y
And a decoder 11. Data can be written and read from the address / data input / output terminal 12 through the I / O buffer 1
This is performed on the path to the Y decoder 11 via 3.

The number of address lines described below is required to select the target 8 bits from the 1024 × 1024 memory matrix.

In order to select one from 1024 X addresses of the memory array 10, 10-bit X address signals A7 to A16 are required. Further Y address 102
To select one word (8 bits) from four, use 7
Bit Y address signals A0 to A6 are required.

In order to store these addresses, the lower 8 bits A7 to A1 of the X address signals A7 to A16 are stored.
4, an X address counter L14 that stores 4 bits, an X address counter H15 that stores the upper 2 bits A15 to A16 of the X address signals A7 to A16, and a Y address counter 1 that stores 7 bits of the Y address signals A0 to A6.
6 and are provided.

The counter output terminals 3 of the X address counter L14 and the X address counter H15, respectively.
0 and the counter output from the counter output terminal 31 are X
Decoded by the decoder 17, the X address is selected. Further, the counter output from the counter output terminal 29 of the Y address counter 16 is decoded by the Y decoder 11 to select the Y address.

In order to load an address to each of the X address counter L14, the X address counter H15, and the Y address counter 16 through the eight address / data input / output terminals 12,
A parallel input terminal 18 is provided. The parallel input terminals 18 are connected to the address / data input / output terminals 12, respectively.

Further, these three X address counters L
14, the X address counter H15, and the Y address counter 16 are connected in series in order to continuously and sequentially select all the addresses in the memory array 10.

The carry output terminal 19 of the Y address counter 16 is connected to the count-up input terminal 20 of the X address counter L14, and the carry output terminal 21 of the X address counter L14 is connected to the count-up input terminal 22 of the X address counter H15. ing.

Next, a method of reading data will be described.

First, the read start address is set to Y
Address counter 16 and X address counter L14
And X address counter H15.

To this end, Y address signals A0 to A6
Is applied to the address / data input / output terminal 12, and a Y address load signal is output from the Y address load output terminal 25 of the control circuit 23 to the load input terminal 32 of the Y address counter 16 to output the Y address signals A0 to A6. The counter 16 is loaded.

Subsequently, X address signals A7 to A14
To the address / data input / output terminal 12, and the X address L load output terminal 26 of the control circuit 23 outputs the X address L load signal to the load input terminal 33 of the X address counter L 14 to output the X address signals A7 to A1.
4 is loaded into the X address counter L14.

Similarly, the X address signals A15 to 16 are transferred to the X address H load output terminal 27 of the control circuit 23.
X address H load signal from X address counter H1
5 to the load input terminal 34 to output the X address signal A
15 to A16 are loaded into the X address counter H15.

The counter output of the Y address counter 16 is decoded by the Y decoder 11, and the counter outputs of the X address counter L14 and the X address counter H15 are decoded by the X decoder 17, and the data of the head address is selected.

The selected data is read by I / O buffer 13 and output to address / data input / output terminal 12.

When the reading of one word is completed, the control circuit 23 outputs an address increment signal from the address increment output terminal 24 to the count-up input terminal 28 of the Y address counter 16 in order to read the next address. The counter 16 is counted up.

After that, the reading is repeated by the required number of words.

Next, a method of writing data will be described.

First, the start address of writing is set to the Y address counter 1 by the same method as the above-mentioned reading method.
6, the X address counter L14 and the X address counter H15 are loaded and decoded.

Next, write data is applied to the address / data input / output terminal 12 to write the data to the selected address through the I / O buffer 13.

When the writing of one word is completed, the control circuit 23 writes data to the next address.
An address increment signal is output from the address increment output terminal 24 and input to the count-up input terminal 28 of the Y address counter 16 to count up the Y address counter 16.

After that, writing is repeated for the required number of words.

[0046]

As is apparent from the above description, since the address input terminal and the data input / output terminal can be shared, the number of terminals can be reduced and the occupied area of the signal line can be reduced. Therefore, a large number of semiconductor memories can be mounted on the wiring board with high density.

Further, data input / output is performed by the number of bits forming one word, and data input / output is performed in parallel. Therefore, the data transfer speed is higher than that of the serial access type in which serial input / output is performed bit by bit.

Further, the semiconductor memory of the present invention can obtain a data transfer rate almost the same as that of the parallel access type. This is because it is possible to input / output data at the same transfer rate as the parallel access type after inputting the head address, and if the transfer amount is large, the input time of the head address can be ignored.

Further, the semiconductor memory of the present invention has high expandability because it is not necessary to increase the number of address input terminals even if the memory capacity increases.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a configuration of a semiconductor memory device according to the present invention and a writing / reading method thereof.

[Explanation of symbols]

 10 memory array 11 Y decoder 12 address / data input / output terminal 13 I / O buffer 14 X address counter L 15 X address counter H 16 Y address counter 17 X decoder 18 parallel input terminal 23 control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 11/413

Claims (3)

[Claims] 1. A memory array, an X decoder, a Y decoder, an I / O buffer, an address / data input / output terminal, and a plurality of parallel input terminals having the same number of bits as the address / data input / output terminal. Address counters, the plurality of address counters are connected in series, and the parallel input terminal of the address counter is connected to the address / data input / output terminal, and all addresses are continuously selected by counting up. Then, the leading address of continuous reading is loaded into the address counter through the address / data input / output terminal. 2. An address / data input / output terminal having the same number as the number of bits forming one word is provided, and when the address is input, the address is divided and input in 1-word units, and when the data is input / output, it is input in 1-word units. A writing / reading method of a semiconductor memory device characterized by outputting. 3. An address / data input / output terminal having an integer number of bits constituting one word is provided, and when inputting an address, the address is divided into the number of the address / data input / output terminals and input. A method for writing and reading data in a semiconductor memory device, wherein data is input / output by dividing the data into the number of address / data input / output terminals.