JPH0863969A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To reduce power consumption required for serially accessing a memory cell array by converting a first address sequence generated by the use of an address sequence generation circuit to a specified second address list using a code conversion circuit. CONSTITUTION: A first address sequence which is supplied from the counter 14 to serially access the memory array 2 is converted into the code of the second address sequence in which the hamming distance of the neighboring address is 1 using the code conversion circuit 16, and the columns of the memory array 1 are accessed through the column decoder 8. By this conversion process, only one bit changes its state when an address composed of two or more bits is switched, and the power consumption required for address switching is minimized. In addition, this method can be similarly applied to the row direction or both the row and the column directions, too.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device characterized by being able to reduce power consumption.

[0002]

2. Description of the Related Art With the development of portable information devices and the like, demands for lower power consumption of semiconductor memory devices are increasing. In particular, a semiconductor memory device using a serial access mode such as a DRAM serial access mode or a flash memory page mode, in which addresses are sequentially switched in the row direction or the column direction to continuously read or write data, is used for high speed operation. For those aimed at, further reduction of power consumption is demanded.

FIG. 6 is a schematic diagram showing a main part of a conventional semiconductor memory device. This semiconductor memory device has a random access mode and a serial data read mode in data reading, and can be switched and used by a control signal MS.

The memory cell array (MA) 102 is basically composed of a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at each intersection of the word lines WL and the bit lines BL. .

A row address Ar is externally applied to a row address buffer (RAB) 110, which is sent to a row decoder (RD) 106 to activate a word line WL corresponding to the address. The data of the memory cells MC connected to the activated word line WL are read to the corresponding bit lines BL, detected by the sense amplifier (SA) 104 of each bit line BL, and latched.

In the random access mode, the column address Ac externally input to the column address buffer (CAB) 112 is sent to the column decoder (CD) 108 via the multiplexer (MUX) 118 and the corresponding bit line BL.
The data latched by the sense amplifier (SA) 104 of FIG.
It is read out from 0.

In the serial data read mode, the column address Ac externally input to the column address buffer (CAB) 112 is sent to the counter (CTR) 114 and set as the initial value of the counter (CTR) 114.
The counter operates in synchronization with (CTR) 114, for example, a clock signal CE input from the outside, and counts up the address. The address counted up by the counter (CTR) 114 is a multiplexer (MUX).
It is supplied to the sequential column decoder (CD) 108 via 118, and the data of the cell MC corresponding to this address is sequentially read out.

In such a conventional semiconductor memory device, the output of the counter described above runs vertically inside the column decoder as an address input signal to the column decoder arranged on one side of the memory array. As the degree of integration of the semiconductor memory device increases, the wiring of the address signal becomes longer, and at the same time, its load capacity also increases.

Therefore, in the conventional semiconductor memory device,
In the mode in which addresses are switched and sequentially accessed, there is a problem that the power consumed by the decoder for switching addresses tends to increase.

[0010]

As described above, the conventional semiconductor memory device has a problem that the power consumption required for address switching increases as the degree of integration increases. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of reducing the power consumption required for address switching during serial access.

[0011]

According to the present invention, there is provided a semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, and the memory cell array is accessed according to a series of addresses in a predetermined order. The address series is represented by a code series in which the Hamming distance between adjacent addresses is 1.

Further, according to the present invention, in a semiconductor memory device for selecting and accessing a predetermined one of a plurality of memory cells according to a given address, a memory cell array having the plurality of memory cells arranged in a matrix is provided. An address sequence generating circuit for generating a first address sequence represented by a binary code for sequentially accessing the memory cells, and a Hamming distance between adjacent addresses of the first address sequence are 1. And a code conversion circuit for converting into a series of second addresses.

Preferably, the circuit further comprises a circuit for inputting the series of the second addresses as a column address or a row address and sequentially switching the addresses to access the memory cell.

Further, preferably, the address series generation circuit and the code conversion circuit are provided respectively corresponding to a column address and a row address represented by a binary code and correspond to a column address represented by a binary code. A circuit for inputting an output of the code conversion circuit as a column address, sequentially switching the column address to access the memory cell, and an output of the code conversion circuit corresponding to a row address represented by a binary code as a row address. A circuit for inputting and sequentially switching the row address to access the memory cell is further provided.

[0015]

According to the present invention, when the semiconductor memory device is in the operation mode in which the memory cells are accessed in a predetermined order, the addresses of the memory cells sequentially accessed are the codes with the Hamming distance between adjacent addresses being 1. Therefore, when the address composed of a plurality of bits is switched, the bit whose state changes is always only one of the bits. On the other hand, when an address represented by a normal binary code is used, the number of bits whose state changes when the address is switched varies from 1 bit to all bits depending on the content of the address.

Therefore, according to the present invention, in the semiconductor memory device in the serial access mode, the number of addresses to which the state transits is minimized, and the power consumption required for address switching can be reduced as compared with the conventional one.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. An embodiment will be described by taking as an example a semiconductor memory device having a function of sequentially switching addresses in the column direction and reading data continuously at a high speed, such as a serial access mode of a DRAM or a page mode of a flash memory.

FIG. 1 is a schematic diagram showing the main part of the semiconductor memory device according to the embodiment. As shown in FIG. 1, the semiconductor memory device of this embodiment has a memory cell array (M
A) 2, sense amplifier (SA) 4, row decoder (RD)
6, column decoder (CD) 8, row address buffer (RA
B) 10, column address buffer (CAB) 12, counter (CTR) 14, code conversion circuit (CC) 16, multiplexer (MUX) 18, data input / output circuit (DAT)
A) It is composed of 20. The present embodiment is characterized in that a code conversion circuit 16 is provided for converting an externally input address into a code such that the Hamming distances of adjacent addresses (after conversion) are all 1.

This semiconductor memory device has a random access mode and a serial data read mode for data reading, and can be switched and used by a control signal MS.

The memory cell array 2 basically has a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells M arranged at each intersection of the word lines WL and the bit lines BL.
Composed of C.

A row address Ar is externally applied to a row address buffer 10 and is sent to a row decoder 6 to activate a word line WL corresponding to the address. The data of the memory cells MC connected to the activated word line WL are read to the corresponding bit lines BL, detected by the sense amplifiers 4 of the respective bit lines BL, and latched.

In the random access mode, the column address Ac externally input to the column address buffer 12 is sent to the column decoder 8 via the multiplexer 18, and the data latched in the sense amplifier 4 of the corresponding bit line BL is the data. Sent to the line and read out from the data input / output circuit 20.

On the other hand, in the serial data read mode, memory cells are sequentially accessed in a predetermined order. That is, the column address Ac externally input to the column address buffer 12 is sent to the counter 14 and set as the initial value of the counter 14. Counter is 1
4. Operates in synchronization with a predetermined control signal (for example, a clock signal CE input from the outside) and counts up (or counts down the address; the count up will be described below). The address counted up by the counter 14 is supplied to the code conversion circuit 16. The code conversion circuit 16 sequentially converts each address represented by the binary code generated by the counter 14 into a code having a Hamming distance of 1 between adjacent addresses. The series of addresses generated by the code conversion circuit 16 is passed through the multiplexer 18 to the sequential column decoder 8
The data of the cell MC corresponding to each address is sequentially read.

Here, when the semiconductor memory device is in the serial data read mode, since the Hamming distance between adjacent addresses is 1 in the addresses of memory cells that are sequentially accessed (after conversion), a plurality of bits are used. When the addresses to be configured are switched, there is always only one bit in the address whose state changes. On the other hand, when an address is represented by a normal binary code, the number of bits whose state changes when the address is switched varies from 1 bit to all bits depending on the content of the address.

Therefore, according to the present invention, when the address is switched in the serial access, it is possible to suppress the change of the state of the address signal line having a large load capacitance which runs in the inside of the column decoder of a plurality of bits to one bit. Therefore, the power consumption required for address switching can be reduced as compared with the conventional case. The load capacity of the code switching circuit is small, and the power consumed here is extremely small.

Specific examples and modified examples of each part of the semiconductor device according to the above-described embodiment will be described below. As the “code having a Hamming distance of 1 between adjacent addresses” used in the code conversion circuit 16, for example, a cyclic code can be used.

FIG. 2 shows a concrete circuit example of the code conversion circuit 16. The code conversion circuit 16 is an example of a circuit that converts a binary code into a Gray code well known as one of cyclic codes. This can be realized by an extremely simple circuit composed of a plurality of exclusive OR circuits 21 as shown in the figure.

Q in the figure is determined according to the number of bits of the address signal. Also, a gray coat (Gi; i = 0 to 0
q) is calculated by the following conversion formula based on the binary code (Ai; i = 0 to q).

Gi = Ai exor Ai + 1 (0 ≦ i ≦ q−1) (1) Gq = Aq where exor represents an exclusive OR.

FIG. 3 shows a circuit example of the column decoder when the address is 3 bits. A plurality of AND circuits 31 to which the 3-bit address signal and the enable signal ENBL are input
(And the NOT circuit 32) constitutes one column decoder. One of eight column decoders is selected by a 3-bit address signal, and its output CSLi (i = 0 to 0) is selected.
7) becomes a high voltage.

In the case of serial access, basically, the column decoders are sequentially selected one by one from the CSL0 side to the CSL7 side. Alternatively, it is possible to start halfway (for example, CSL3) and select an arbitrary column decoder (for example, CSL6).

The right side of the column decoder in FIG. 3 shows combinations of 3-bit address signals for selecting the column decoders for the binary code and the Gray code.

In the case of binary code, for example, CS
When changing the selected column from L1 to CSL2, A0 and A
2 addresses of 1 must be changed, and C
When changing from SL3 to CSL4, 3 of A0, A1 and A2
The state of one address must be changed. On the other hand, when the address converted into the gray code is used as in the present invention, only the address G1 is changed in the case of CSL1 → CSL2 and only the address G2 is changed in the case of CSL3 → CSL4. In other cases, the next column can always be accessed by changing only one bit of the 3-bit address.

As described above, according to the present invention, the transition probability of the address signal can be minimized to reduce the power consumption required for address switching. In the embodiment of FIG. 3, the maximum value of the column address (in this case, 11 in binary
Even when 1) and the minimum value (here, 000 in binary) are continuously accessed, the change in address after conversion is 1 bit, and the effect of the present invention can be obtained.

The address generated by the code conversion circuit is not limited to the cyclic code as in the above embodiment, but any code can be used as long as the Hamming distance between adjacent addresses is 1. FIG. 4 shows an example of a 4-bit code of a type different from the code shown in FIG. Further, FIG. 5 shows a 4-bit Gray code. When the maximum value (for example, 1111) and the minimum value (for example, 0000) of the column address are continuously accessed, it is effective to use the cyclic code because the address change becomes 1 bit.

In the above embodiment, the case where the present invention is applied to the circuit portion related to the column address of the DRAM having the serial access mode or the flash memory having the page mode has been described. It is also possible to apply to both address and row address. Further, the present invention can be applied not only to reading as in the above embodiment but also to writing.

In FIG. 1, the semiconductor memory device having the random access mode has been described as an example, but the invention can be applied to the semiconductor memory device having only the serial access mode.

Further, the present invention is not limited to the application to serial access at the time of reading of the semiconductor memory device, but can be applied to other operations in which the order of access to the memory cells is predetermined. . For example, in the case of the self-refresh operation of the dynamic RAM, the present invention may be applied to the row address.

The present invention can be applied to any semiconductor memory device such as SRAM in addition to DRAM and flash memory. Furthermore, in the present embodiment, the internal counter is used to realize the random access mode, but even if the internal counter is not provided, binary that continues from the outside (increases or decreases by 1) from the outside. Even when a code sequence is input as an address, or when the counter of FIG. 3 is externally provided, the present invention can be applied and its effect can be obtained. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0040]

According to the present invention, when the semiconductor memory device is in the operation mode in which the memory cells are accessed in a predetermined order, the addresses of the memory cells sequentially accessed have a Hamming distance of 1 between adjacent addresses. Therefore, it is possible to make only one bit whose state changes when the address composed of a plurality of bits is switched.

Therefore, according to the present invention, in the semiconductor memory device in the serial access mode, the number of addresses whose states transit is minimized, and the power consumption required for address switching can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a code conversion circuit in the embodiment.

FIG. 3 is a diagram showing a configuration of a column decoder circuit in the same embodiment.

FIG. 4 is another example of the code generated by the code conversion circuit.

FIG. 5 is still another example of the code generated by the code conversion circuit.

FIG. 6 is a block diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

2 ... Memory cell array, 4 ... Sense amplifier, 6 ... Row decoder, 8 ... Column decoder, 10 ... Row address buffer, 1
2 ... Column address buffer, 14 ... Counter, 16 ... Code conversion circuit, 18 ... Multiplexer, 20 ... Data input / output circuit, 21 ... Exclusive OR circuit, 31 ... AND circuit,
32 ... NOT circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G11C 17/00 309 J

Claims (4)

[Claims] 1. A semiconductor memory device comprising a memory cell array in which a plurality of memory cells are arranged in a matrix, and the memory cell array is accessed according to a series of addresses in a predetermined order, wherein the series of addresses are adjacent to each other. A semiconductor memory device represented by a code sequence in which a Hamming distance of an address to be set is 1. 2. A semiconductor memory device for selecting and accessing a predetermined one of a plurality of memory cells according to a given address, a memory cell array in which the plurality of memory cells are arranged in a matrix, and the memory cell. An address sequence generation circuit for generating a sequence of first addresses represented by a binary code for sequentially accessing the first address sequence and a second address for which the Hamming distance of adjacent addresses is one. A semiconductor memory device comprising: 3. The semiconductor device according to claim 2, further comprising a circuit for inputting the series of the second addresses as a column address or a row address and sequentially switching the addresses to access the memory cell. Storage device. 4. The address series generation circuit and the code conversion circuit are respectively provided corresponding to a column address and a row address represented by a binary code, and the code conversion corresponding to a column address represented by a binary code. An output of the circuit is input as a column address, a circuit for sequentially switching the column address to access the memory cell, and an output of the code conversion circuit corresponding to a row address represented by a binary code are input as a row address, 3. The semiconductor memory device according to claim 2, further comprising a circuit that sequentially switches the row address to access the memory cell.