JPH0365745A - Ic card - Google Patents

Abstract

PURPOSE:To make the data bus width of an IC card capable of being switched by changing the memory configuration of a semiconductor memory element by giving a prescribed signal. CONSTITUTION:Plural data bus switch signals 33,34 are supplied to a memory select signal switching circuit 10 installed in order to switch the connection of an address decoder circuit 1, plural semiconductor memory elements 2 to 5 and each data bus buffer circuit 6 to 9 for these in the IC card, bus switching circuits 11,12, most significant address switching circuits 15,16 and N-bits inhibition circuits 13,14 to control a card enable signal 35 to be given to the data bus buffer circuits 6 to 9. Then, the memory configuration in the IC card is switched so that plural semiconductor memory elements 2 to 5 operate independently or plural semiconductor memory elements 2 to 5 operate in parallel. Thus, the change of the data bus width can be made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application j] This invention relates to an IC card equipped with a semiconductor memory element.

[Conventional technology]

Figures 2 and 3 are block diagrams showing the internal structure of conventional IC cards, and Figure 2 is an 8-pit dedicated IC card.
FIG. 3 shows an IC card exclusively for 16 bits.

First, in the case of the 8-bit dedicated IC card shown in FIG.
) are connected to chip select signals M (29) (30) from the address decoder circuit (1). Further, a card enable signal line (35) and a top address line (40) are connected to the address decoder circuit (1).

In order to enable this circuit to operate (read or write), the card enable signal (35) is set to the 1L" level. As a result, the address decoder circuit (1) becomes active. Next, the highest address signal (40) b and address signal (19)
is given. For example, when the highest address signal (40) is in the 'L' level state, the address decoder circuit (1)
Chip select signal (29) wo"I," level status,
Since the chip select signal i (30) is set to the "H" level state, the semiconductor memory element (3) is in the active state and the semiconductor memory element (2) is in the standby state, and the semiconductor memory element is connected via the data bus (25). (3) It becomes possible to write to or read from. When the most significant address signal (40) is at @R'' level, the opposite is true, and writing to or reading from the semiconductor memory element (2) is possible via the data bus (24).

Next, in the case of the 16-bit dedicated IC card shown in FIG. Since the semiconductor memory elements (3) are activated at the same time, it is possible to read or write 16-bit data via the respective 8-bit data buses (24) and (25).
The two semiconductor memory elements (2) and (3) will operate in parallel. Control signals for writing and reading operations are actually provided, but their explanation will be omitted here.

[Problem to be solved by the invention] Since the conventional IC card was configured as described above,
There was a problem that one IC card could not be used for both 8-bit and 16-bit because there were two types: one for 8-bit and one for 16-bit, and each had a different internal structure. .

This invention was made to solve the above-mentioned problems, and provides an IC card that can change the memory configuration of a semiconductor memory element and switch the data bus width of an XC card by applying a predetermined signal. The purpose is to obtain.

[Means to solve the problem]

An IC card according to the present invention includes a plurality of N-bit semiconductor memory elements provided as a memory portion of the IC card;
An address decoder circuit is inserted into each N-bit delta bus connected to the plurality of semiconductor memory elements, and an address decoder circuit that makes a predetermined memory element of the plurality of semiconductor memory elements operable according to an upper address signal from outside the card. ,
a data bus buffer circuit that controls data input/output;
A switching circuit inserted between the address decoder and the plurality of semiconductor memory elements, between the plurality of semiconductor memory elements and the data bus buffer circuit, and on the upper address line to the address decoder circuit allows A storage configuration switching means for switching the connections of the elements and the data bus buffer circuit, and a plurality of data bus switching signals for controlling the switching to each of the switching circuits of the storage configuration switching means, and a plurality of data bus switching signals for switching these data buses. a switching control means for controlling a card enable signal to enable the data bus buffer circuit to operate according to a signal, and the plurality of semiconductor memory elements can be connected to each other independently or to a plurality of semiconductor memory elements. By switching the memory configuration so that the elements operate in parallel, the data bus width of the IC card can be changed to N bits, 2N pits, 3H bits, and 4 bits.
It is possible to switch between N bits and MN bits (N%M is a natural number).

[Effect]

The IC card according to the present invention includes an address decoder circuit in the IC card, a memory selection signal switching circuit provided for switching connections between a plurality of semiconductor memory elements 4 and each of these data bus buffer circuits, a path switching circuit, and a top layer. A plurality of data bus switching signals are applied to an N-bit disable circuit that controls a card enable signal applied to an address switching circuit and a data bus buffer circuit, and a plurality of semiconductor memory elements can be controlled independently, or a plurality of semiconductor memory elements can be By switching the memory configuration in the IC card so that they operate in parallel, -ri/2N/3N/.
-/vn bit switching, and in particular, it is possible to change the data bus width of 8/16/32 bits, which are commonly used.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the internal configuration of an IC card according to an embodiment of the present invention.
As an IC card that also serves as a bit, for example, 8/16/32
An IC card that can also be used as a bit is shown. Among them, parts that are the same as or correspond to the conventional ones are indicated by the same reference numerals. (1) is an address decoder circuit, (2) (3
) (4) (5) is a semiconductor memory element, (6) (7)
(8) (9) is a data bus buffer circuit, (10)
are memory selection signal switching circuits, (15) (16) are upper address switching circuits, (11) (12) are internal data buses (20) (21) (22) (23) 8/16/
Bus switching circuit for switching to 32 bits, (13) is 8.16 for controlling data bus buffer <6) <7)
Bit disable circuit, (14) is data bus buffer (8)
8 pin l-9L circuit for controlling, (33) is 87
16 data path switching signal, (34) is 32/8・1\6
This is a data bus switching signal.

Next, referring to FIG. 1, the operation of the 8/16/32 bit common card at 32 bits will be explained. When performing 32-bit operation, the 3278/16 data bus switching signal (34) is set to the 1'' level. At this time, the memory selection signal switching circuit (11) connects the select signal line (32) (
31) (30) and the address decoder circuit (1) are disconnected, and the select signal @ (29) and the select signal line (30) (31) (32) are connected. Since the upper address switching circuits (15) and (16) are off, the input of the address decoder circuit (1) is set to 1L by the pull-down resistor (17) (1g) regardless of the input of the upper address (40) (41). level.!The internal data bus switching circuit (11) (
12) is in the off state, so the internal data bus (20)
(21), (22), and (23) will not interfere with each other. In the above state, the address bus (19
), enter the address, and enter the card enable input to 1L.
”In terms of level, select signal line (29) (30)
(31) and (32) simultaneously become 1L5 level, and semiconductor memory elements (2), (3), (4), and (5) become active. At this time, the data bus buffer (9) is activated by the card enable input (35), and the data bus buffer (8) in the case is activated by the 8-bit disable circuit (
The output signal (37) of 14) becomes @L”Vpe~, so it is active, and the data bus buffer (6) σ) becomes 8.1
The output signal line (36) of the 6-bit inhibit circuit (13) is 1L.
” level and is active, so 32-bit reading and writing is possible through the external data buses (24) (25) (26) (27).

Next, during 16-bit operation, when the 8716 data bus switching signal (33) is set to the 1V level and the 32/8/16 data bus switching signal (34) is set to the 1L'' level, the memory selection signal switching circuit (lO) Select signal line (32) (30)
and the address decoder circuit (1), select signal lines (31) and (32), and select signal line (29).
and (30) are connected respectively. Since the upper address switching circuit (15) is in an off state and (16) is in an on state, the upper address input (41) is decoded and appears on the select signal lines (29) and (31). On the other hand, the bus switching circuit (11) is off and (12) is on, so
The internal data bus (20) (21) is the internal data bus (
22) and (23) respectively. Now, when the card is enabled and the input (35) is set to the 1L" level, either semiconductor memory element (2) (3) - or (4) (5) is selected in accordance with the upper address input (41). The data bus buffer (8) is activated by the output (37) of the 8-bit disable circuit (14), and the data bus buffer (9) is activated by the card enable input (35).
) is also active, so the external data bus (26)
Data is written to or read from the semiconductor memory element (2) (3) or (4) (5) through (27). At this time, the data bus buffers (24) (25
) is the output (36) from the 8/16 bit inhibit circuit (13).
) is inactive at 1° V Bell, the external data bus (24) (25) is kept high impedance and has no effect on top writes or reads.

Next, during 8-bit operation, the data bus switching signal (33)
(34) is set to L” level, the memory selection signal circuit (
lO) is the select signal line (29) (30) (31)
(32) and the address decoder circuit (1) are connected, and the select signal lines are disconnected. Also, since the upper address switching circuits (15) (16) are in the on state, the upper addresses (40) (41) are decoded and the select signal lines (29) (30) (31) are decoded.
It appears in (32). On the other hand, the path switching circuit (11) is in the on state, the path switching circuit (12) is in the off state, and the internal data bus (2
0) (21) (22) are connected to the internal data bus (23). Now, when the card enable input (35) is set to "L" level, the upper address input (40) (
41), semiconductor memory elements (2) (3) (4
) (5) is selected. Since the data bus buffer (9) is activated by the card enable input, this When the data bus buffer (6) (7) (8) is the 8-bit inhibit circuit (13)
Output (36) of 8/16 bit inhibit circuit (14) (
37) is inactive because it is at H” level,
The data buses (24) (25) (26) are kept at high impedance and have no bearing on the above writing or reading.

Among them, in the above embodiment, the external data bus switching signal (
33) (34) Semiconductor memory elements (2) (3)
(4) The memory configuration and data bus width in (5) have been changed, but a mechanical switch is provided inside the IC card and it can be used alone or with a data bus switching signal (33) (3
4) In the above embodiment, the data bus width was changed to 8/16/32, but by increasing the number of data bus switching signal lines and upper address inputs, memory selection can be changed. circuit, path switching circuit,
By increasing the number of address switching circuits and prohibition circuits in the same manner as in this invention, N/2 N /3 N/4 N /s
N/−/M N bit data bus switching can be performed.

In the above embodiment, the address decoder circuit (IL memory selection signal switching circuit (10), path switching circuit (11) (
12), Upper address switching circuit (15) (16), 8
Bit disable circuit (14), 8/16 bit disable circuit (1
3), data bus buffer (6) (7) (8) (9
) were configured separately, but semiconductor memory elements (2) and (3
) (4) It is also possible to use a system in which an IC card that combines all of the functions except for (5) into one IC is used.

〔Effect of the invention〕

As described above, according to the present invention, the data bus switching signal (
33) Due to (34>), the semiconductor memory element of an IC card (
2) (3) (4) The memory configuration and data bus width in (5) can be changed, so even if the data bus on the system side is changed, it is convenient to be able to handle one card, and the chassis For example, data stored on an N-bit databus IC card can be transferred to a 2N-bitbus system or a 4N-bitpass system. In addition, since the reverse is also possible, even if the bus width on the system side changes, the IC
It becomes possible to effectively utilize and mutually use the memory contents of the card.

[Brief Description of the Drawings] Figure 1 is a circuit block diagram of an 8/16/32/bit common card according to an embodiment of the present invention, and Figures 2 and 3 are a conventional 8-bit exclusive card and a 16-bit exclusive card. FIG. 3 is a circuit block diagram of the card. In the figure, (1) is an address decoder circuit, (2) (
3) (4) (5) is a semiconductor memory element, (6) (7)
(8) (9) is a data bus buffer, (10) is a memory selection signal switching circuit, (11) (12) is a path switching circuit, (13) is an 8/16 bit prohibition circuit, and (14) is an 8 bit prohibition circuit. circuit, (15) (16) are upper address switching circuits, (17) (18) are pull-down resistors, (1
9) is the address bus, (20) (21) (22)
(23) is an internal data bus, (24) (25) (2
6) (27) is external data bus, (29) (30)
(31) (32) is the select signal line, (33) (
34) is a data bus switching input, (35) is a card enable input (40), and (41) is an upper address input. In the figures, the same reference numerals indicate the same, l, or equivalent parts. Figure 3

Claims (1)

[Claims] A plurality of N-bit semiconductor memory elements provided as a memory portion of the IC card and a predetermined memory element among the plurality of semiconductor memory elements are made operable in accordance with an upper address signal from outside the card. An address decoder circuit, a data bus buffer circuit that is inserted into each N-bit data bus connected to the plurality of semiconductor memory elements and performs data input/output control, and between the address decoder and the plurality of semiconductor memory elements. , a switching circuit inserted between the plurality of semiconductor memory elements and the data bus buffer circuit and on the upper address line to the address decoder circuit, the address decoder circuit, the plurality of semiconductor memory elements and the data bus buffer circuit are connected to each other. A storage configuration switching means for switching the connection of the buffer circuit, and a plurality of data bus switching signals for controlling the switching to each of the switching circuits of the storage configuration switching means, and a plurality of data bus switching signals for controlling the switching. switching control means for controlling a card enable signal to enable the data bus buffer circuit to operate the plurality of semiconductor memory elements, or By switching the memory configuration to operate in parallel, the data bus width of the IC card can be changed to N bits, 2N bits, 3N bits, 4N bits, etc.
- An IC card characterized by being able to switch to MN bits (N and M are natural numbers).