JP3038618B2 - Memory device with built-in test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rewritable memory unit, an input unit for outputting data on an internal common bus to a memory unit, and an output unit for outputting data from the memory unit to an internal common bus. An address control unit that outputs an address signal from an address bus to a memory unit, and exchanges data with the memory unit via an internal common bus and an input unit or an output unit, and exchanges data with an input port or an output port. And a memory device having a logic circuit unit.

[0002]

2. Description of the Related Art Conventionally, in this type of memory device, a memory test can be performed by directly connecting a terminal of a memory unit and an external terminal with a signal line and accessing from the outside, or connecting a terminal of the memory unit to a terminal of the memory unit. For example, a memory bus is provided with a dedicated test bus.

[0003]

In the above-mentioned conventional memory device, a circuit for performing a memory test is specially constructed without using an existing circuit configuration. is there.

[0004] In view of the above drawbacks, an object of the present invention is to provide a memory device capable of performing a memory test using an existing internal circuit.

[0005]

A memory device according to the present invention comprises:
A rewritable memory unit, an input unit for outputting data on the internal common bus to the memory unit, an output unit for outputting data from the memory unit to the internal common bus, and an address signal from the address bus to the memory unit An address control unit for outputting,
When a test mode is selected in a memory device having a logic circuit for transmitting and receiving data to and from a memory unit via an internal common bus and an input unit or an output unit, and for transmitting and receiving data to and from an input port or an output port, An input switching circuit for switching and outputting an address signal and a data signal from the input port to an internal common bus, and controlling the address signal from the internal common bus in place of the address signal from the address bus in a test mode. An address selector for switching and outputting to the unit, and a data signal on the internal common bus in the test mode,
A test data writing unit for writing test data based on the input data signal to the specified address of the memory unit via the input unit; and in a test mode, the data of the output unit is replaced by an internal common bus instead of an internal common bus. An output switching circuit that outputs to the data line, and an output selector that outputs data of the internal data line to the output port instead of outputting to the output port of the logic circuit unit in the test mode.

Preferably, the test data writing section includes a data generation circuit for generating test data of a suitable number of bits for the memory section from a data signal having a small number of bits, or the same number of bits as the number of bits of the memory section. A connection unit that outputs a data signal having a number to the memory unit as the test data via the input unit.

[0007]

When the test mode is set, the address signal and the data signal of the input port are output to the internal common bus, and the address signal indicates the address of the memory unit via the address selector and the address control unit. Is given as test data to the specified address in the memory unit by the test data writing unit. Data read from the designated address in the memory unit is output to an output port via an output unit, an output switching circuit, and an output selector.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the memory device of the present invention. The selector 1 outputs an address signal of the address bus when the mode signal MD is at a logical level low (hereinafter, described as L level), and outputs the internal common bus when the mode signal MD is at a logical level high (hereinafter, described as H level). 10 address signals are output. Address control unit 2
Indicates the corresponding address of the memory unit 3 according to the address signal output from the selector 1. Instructed memory unit 3
The data from the input unit 4 is written to the address of, or the data is output to the output unit 5. The selector 6 mode signal MD is output data of a predetermined bit position within the common bus 10 through the buffer ₇₁ at H level to the input unit 4, the internal common-mode signal MD via a buffer 7 ₂ at the L level A data signal at a predetermined bit position on the bus 10 is output to the input unit 4. The output unit 5 tristates data from the memory unit 3 when the mode signal MD is at the H level.
₁ to a data line DL (the number of lines is prepared only for transmitting data from the memory unit 3 in parallel), and when the mode signal MD is at the L level,
₂ to the internal common bus 10. Logic circuit section 9
Is the internal common bus 10 when the mode signal MD is at L level,
Buffer 7 ₂ , selector 6, input unit 4 and output unit 5,
With exchanges of the memory unit 3 and the data through the tri-state _82, the data from the input port 11 via a buffer 14 _1, the tri-state 15 ₂ uptake, the selector 16, the output port 12 via a buffer 14 ₂ Output data from The selector 16 outputs the data of the data line DL when the mode signal MD is at the H level, and outputs the output of the logic circuit unit 9 when the mode signal MD is at the L level.

Therefore, the output terminal of the memory tester 30 is connected to the input port 11, the input terminal is connected to the output port 12, and the select signal terminal is connected to the signal terminal 13.

Next, a second embodiment of the present invention will be described with reference to FIG. The embodiment of FIG.
This corresponds to the case where the number of bits of the data signal from is smaller than the number of bits required for writing each address in the memory unit 3.

The differences from the embodiment of FIG. 1 will be described below.

The input section 24 comprises a test data generation section 24 ₁ and a generation control section 24 ₂ . When generation control unit 24 ₂ is the mode signal MD is at the H level, the data signal test data generating unit 24 ₁ is input from the internal common bus 10 through the buffer 7 to the test data that matches the number of bits memory 3 The test data generation unit 2
4. Control ₁ When the mode signal MD is at L level,
The data signal input from the internal common bus 10 is output to the memory unit 3 as it is.

[0013]

As described above, according to the present invention, in the test mode, an address signal and a data signal are supplied to the memory unit via the input port and the internal common bus, and the output from the memory unit is supplied via the output port. By reading, there is an effect that the memory test can be easily performed without increasing the number of external terminals or using a dedicated test bus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a memory device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

1,6,16 selector 2 address control unit 3 memory 4, 24 input section 5 outputs portions 7 _1, 7 _2, 14 _1, 14 ₂ buffer 8 _1, 8 _2, 15 _1, 15 ₂ tristate 9 logical Circuit section 10 Internal common bus 11 Input port 12 Output port 13 Signal terminal 30 Memory tester

Claims (3)

(57) [Claims] A rewritable memory unit, an input unit for outputting data on an internal common bus to the memory unit, an output unit for outputting data from the memory unit to the internal common bus, and an address from an address bus. An address control unit for outputting a signal to the memory unit; a logic circuit unit for exchanging data with the memory unit via the internal common bus and the input unit or the output unit, and exchanging data with the input port or the output port. An input switching circuit for switching and outputting an address signal and a data signal from the input port to an internal common bus in a test mode, and replacing the address signal from the address bus in a test mode. An address selector for switching and outputting an address signal from an internal common bus to the address control unit, and a test mode. A test data writing unit for inputting a data signal on the internal common bus and writing test data based on the input data signal to the specified address of the memory unit via the input unit; An output switching circuit that outputs data of the output section to an internal data line instead of an internal common bus, and outputs a data of an internal data line instead of output to an output port of the logic circuit section in a test mode. A memory device, comprising: an output selector for outputting to a port. 2. The test data writing section includes a data generation circuit that generates test data having a bit number suitable for the memory section from a data signal having a small number of bits.
A memory device as described. 3. The test data writing unit is a connection unit for outputting a data signal having the same number of bits as the number of bits of the memory unit to the memory unit as the test data via the input unit. A memory device as described.