JPS59151371A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To attain simultaneous accessing to the same memory from plural systems by making the titled memory element accessible from two systems of address lines, providing a data line possible for read and write corresponding to one address line and providing a data line possible for read only corresponding to the other address line. CONSTITUTION:A memory element 11 has the 1st and 2nd address lines 12, 13. A data line 14 is provided corresponding to the address line 12 to read and write a data to an address selected by the address line 12 corresponding to contents of a read/write control line R/W 16. Further, a data line 15 is provided so as to read only the contents of the address selected by the address line 13. Through the constitution above mentioned, when using this memory element as a memory for, e.g., video, the address line 12 and the data line 14 have only to be connected to a CPU side and the address line and the data line 15 have only to be connected to a CRT controller side.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to improvements in address lines and data lines.

[Technical background of the invention]

As shown in FIG. 1, the Tatoe microcomputer's video RAM is used by switching the address line and data line of the same HJv1 into two systems: the CPU1ll11 and the CRT control side. In the figure, I is read/write memory IJ (RAM), 2 is CPU address gC-
4 is a multiplexer that selects one of the video address lines V-AIJ output from the T controller 3 and controls the address of the memory l.
A data buffer that controls reading and writing of the data line C-DT, 5 is a character that is given the data output of M-e+)z and inputs the corresponding data to the shift register 6 in parallel by the clock signal CLK of the CRT controller 3. It is a generator. Also, shift register 6
is the set signal ST given from the CRT controller 3
The output data of the character generator 5 is converted into a serial signal by the shift clock 5-CL and sequentially outputted. Then, the serial signal output from the shift register 6 is sent to the video signal synthesis circuit 7 for CR.
, and the synchronizing signal SYC provided from the T controller 3 to obtain the video signal VIIJEO. Note that the switching operation of the multiplexer 2 is also performed in synchronization with the control signal CT of the CRT controller 3 to control the signals so as not to collide. Furthermore, for the memo sono, the CI)U memory control signal C-CNT is given, and the CPU side reads out the selected memory.
Write mode control is performed, and when selected on the 1%T controller 3 side, a read signal RD is given to control the read mode.

That is, since conventional memory has a single input/output for data and addresses, there are two different systems, for example, the CPU side and the controller (11!) and the controller (11!).
When accessing the contents with I, for example, it was necessary to switch all the address lines◇ [Problems with background branching techniques] For this reason, systems that access the same memory from multiple systems, such as the CPU and (JtT In systems that control video memory accessed from a controller or memory that is subject to direct memory access (1) MA) control, there is a problem in that address switching [11] becomes complicated and costs increase. Also, since it is inherently unwise to access the same memory in multiple systems at the same time, an asynchronous circuit must be provided to control the bus to eliminate contention, and l'f'f configuration is unreliable. become.

Furthermore, in a system in which the same memory is accessed by multiple f systems, there is a problem in that the throughput of the entire system is reduced in a system in which the ratio of accesses by these systems is high.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and it is possible to access the same memory from multiple systems at the same time, and to simplify the configuration of the system by providing address lines corresponding to each system. The purpose is to provide children.

[Summary of the invention]

In other words, the present invention allows the contents to be accessed independently by two address bases, and provides a readable and writable data line corresponding to one address line, and a readable and writable data line corresponding to the other address line. This feature is characterized by providing an address line exclusively for output, which is possible only for output.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to a block diagram shown in FIG. In FIG. 2, reference numeral 1 denotes a memory element according to the present invention having a first address line 12 and a second address line 13. In FIG. A first data line 14 is provided corresponding to the first address line 12, and read/write control Q R/W t is applied to the address selected by the first address line I2.
Reading and writing are performed according to the contents of 6. Further, a second data line Z5 is provided corresponding to the second address line Z3, so that only the contents of the address selected by the second address line 13 can be read.

With such a configuration, when this memory element is used as a video memory, for example, the first address line 12 and the first data line I4 are connected to the CPLJ side,
CR the second address alS and the second data line 15
It may be used by connecting it to the T controller side. In this way, the overall configuration can be significantly simplified, without causing bus contention, and without having to switch the address lines. Coupled with the fact that the contents of the memory element can be accessed through wires, high-speed operation can be performed and the drop in throughput can be significantly reduced.

〔Effect of the invention〕

As described in detail above, according to the present invention, the contents of the memory can be accessed independently using two address lines, which simplifies the system configuration, lowers the cost, and reduces the drop in throughput. A live conductor memory element can be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of video R and AM;
The figure is a block diagram showing one embodiment of the present invention. 11...Memory element, 12...First address line, 1
3...Second address line, 14...First data line, I5...Second data line, I6...Read/write control Todoroki Applicant's agent Patent attorney Takehiko Suzue 459-

Claims (1)

[Claims] A first address line and a second address line that select the contents of the memory element independently of each other, and read or enrich the address selected by the first address line according to the contents of the read/write control register. a first data line for performing
and a chain 2 data line for reading out the contents of an address selected by a second address line.