JP2595707B2 - Memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a serial write parallel read type memory device.

2. Description of the Related Art Conventionally, a serial data communication device often used in a one-chip microprocessor or the like is constituted by a shift register, a shift counter, and a buffer register. A typical example is a Japanese Patent Publication No. Sho 60-5848.
No. 2 discloses this. When serial data is received, parallel data is transmitted from the shift register after storing one frame of data (often 4 bits or 8 bits constitutes one frame) in the buffer register, but several frames at a time. In order to receive a data group of a minute, a plurality of sets of buffer registers must be prepared, and there is a problem that the number of wirings at the output portion of the parallel data increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize a buffer register group in which the number of wires of the data input / output unit does not increase even when serial data for several frames is continuously received. Is to realize a memory device having a small number of wires, capable of storing data for a plurality of frames, and capable of extracting parallel data.

Means for Solving the Problems In order to solve the above-described problems, in the memory device of the present invention, a unit memory cell, a bit selection line, and the unit memory cell when the bit selection line is activated during data writing. A frame configured by arranging a plurality of data storage bits comprising input switch means connected to a common input line, and output switch means connecting the output of the unit memory cell to the bit select line when reading data; A decoder for selecting one of the data storage bits forming the frame via the bit selection line, an output terminal group for extracting parallel data from each bit selection line in the frame when reading data, and an output of the decoder for writing data. Decode connected to the bit select line of each data storage bit It has a switch.

Operation In the present invention, with the above-described configuration, reading of parallel data and selection of bit positions at the time of writing of serial data are performed through a common line, and the number of wirings for performing these operations is greatly reduced. Is done.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present invention. A first frame 100 is composed of data storage bits 110, 120, 130, 140, 150, 160, 170, 180. First bit 110 of data storage bit
Is a unit memory cell formed by an inverter 111 and a three-state inverter 112, a three-state buffer 113 for sending an output of the unit memory cell to a D0 terminal,
When the first bit of the first frame is selected by the data supplied to the X0, X1, X2, Y0, and Y1 terminals. A NAND gate 115 for setting the output of the three-state inverter 112 to a high impedance state; and an inverter 116 for setting the output of the three-state inverter 114 to a high impedance state when the three-state inverter 112 is active.
The second bit 120 to the eighth bit 180 of the data storage bits have the same configuration. Further, a second frame 200 and a third frame 300 are configured similarly to the first frame 100.

The input of the 3-state inverter of each bit for transmitting write data to the memory cell is commonly connected to the SX terminal, and the output of the 3-state buffer for transmitting the output of the memory cell is connected to the D0 to D7 terminals, respectively. It is connected to the.

On the other hand, a bit selection line group 400 is connected to the data readout lines connected to the data terminal groups D0 to D7, and the output side of the switch group 500 including eight 3-state buffers is connected to the bit selection line group 400. The output of the decoder 600 is supplied to the input side of the switch group 500.

When writing serial data from the SX terminal to each memory cell, the first frame 100 to the third frame
Two bits of data for selecting one of 300 are supplied, and three bits of data specifying the bit position of the selected frame are supplied to the X0, X1, and X2 terminals.
The level of the WRITE terminal is temporarily shifted to '1'.
When reading parallel data from the D0 to D7 terminals, WR
The level of the ITE terminal is fixed at “0”, and 2-bit data for selecting any of the first frame 100 to the third frame 300 is supplied to the Y0 terminal and the Y1 terminal.

The operation of the memory device configured as described above will be described based on the configuration diagram of FIG. 1 and the timing chart of the main part shown in FIG.

First, FIG. 2A shows a clock signal waveform for receiving serial data, FIG. 2B shows a change in input data from the SX terminal, and FIGS. 2C, 2D, and 2E show X0 terminal and X1 terminal, respectively. Terminal, X
Signal waveforms supplied to two terminals, and FIGS. 2F and 2G show signal waveforms supplied to the Y0 terminal and the Y1 terminal, respectively.

In the apparatus shown in FIG. 1, in order to write serial data to the first frame 100, the level of the WRITE terminal is set to "1".
Then, the levels supplied to the X0 to X2, Y0, and Y1 terminals may be changed as shown in FIGS. 2C to 2E, 2F, and 2G, respectively. That is, before the time t1 in FIG. 2, the levels of the X0 terminal to the X2 terminal, the Y0 terminal, and the Y1 terminal are all “1”, so that the output levels of the AND gates 608 and 3 are both “1”. And the output level of the NAND gate 385 constituting the data storage bit 380 of the third frame 300 is '0'.
It has become. Therefore, at this time, the data of the SX terminal is supplied to the inverter 381 via the inverter 384. When the leading edge (leading edge) of the clock signal arrives at time t1, the level of the X0 terminal changes from “1” to “0”.
(C in FIG. 2), whereby the output level of the AND gate 607 constituting the decoder 600 shifts to “1”, and data is written to the data storage bit 370 this time. Thereafter, similarly, until time t2, serial data is sequentially written into each data storage bit of the third frame 300.

When the leading edge of the clock signal arrives at time t2, the levels of the X0 to X2 terminals shift to “1”. At this time, the level of the Y0 terminal shifts to “0” (FIG. 2F). As a result, the output level of the AND gate 2 shifts to “1”, and the serial data is written to each data storage bit configuring the second frame 200 from this time to time t3.

Further, between the time t3 and the time t4, the first frame 10
Serial data is written to each data storage bit of 0.

On the other hand, in order to read data from the memory device shown in FIG. 1, it is sufficient to fix the level of the WRITE terminal to '0' and then supply the frame selection data to the Y0 and Y1 terminals. For example, in order to read the parallel data stored in the first frame 100, both the levels of the Y0 terminal and the Y1 terminal may be set to “1”, whereby the output levels of the AND gate 1 and the AND gate 12 become “1”. ', And the data terminal groups D0 to D7
To the first frame via three-state buffers 113 to 183
The parallel data stored in 100 is sent.

Thus, in the memory device shown in FIG. 1, reading of parallel data and selection of a bit position at the time of writing serial data are performed via a common line, that is, a line for reading parallel data. Therefore, the number of wires of the device is greatly reduced.

As is clear from the above description, the memory device according to the present invention has a unit memory cell (in the embodiment, the inverters 111 and 3).
It is composed of a state inverter 112. )
And a bit selection line (a line to which the non-common-side input terminal of the NAND gate 115 is connected, and a plurality of these collectively constitute a bit selection line group 400). Input switch means (3-state inverter 114) for connecting the unit memory cell to a common input line (SX terminal) when the data is read, and an output switch for connecting the output of the unit memory cell to the bit selection line when reading data. A frame 100 formed by arranging a plurality of data storage bits 110 comprising means (three-state buffers 113); a decoder 600 for selecting one of the data storage bits forming the frame via the bit selection line; Output terminal group (data terminal group D0 to D7) for taking out parallel data from each bit selection line in the frame when reading data And a decode switch (switch group 500) for connecting the output of the decoder to the bit selection line of each data storage bit at the time of data writing, so that serial data can be written and parallel data can be extracted with a small number of wirings. A memory device can be realized, and a great effect is achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory device according to an embodiment of the present invention, and FIG. 2 is a timing chart of a main part of FIG. 100 ... first frame, 110 ... data storage bits, 114 ...
... 3-state inverter, 113 ... 3-state buffer, 2
00: second frame, 300: third frame, 400: bit selection line group, 500: switch group, 600: decoder.

Claims (1)

(57) [Claims] 1. A unit memory cell, a bit selection line, input switch means for connecting the unit memory cell to a common input line when the bit selection line is activated during data writing, and the unit switch during data reading. A frame constituted by arranging a plurality of data storage bits each comprising output switch means for connecting an output of a memory cell to the bit selection line, and one of the data storage bits constituting the frame via the bit selection line. A decoder for selecting, an output terminal group for extracting parallel data from each bit selection line in the frame when reading data, and a decode switch for connecting the output of the decoder to the bit selection line of each data storage bit when writing data. Memory device.