JPS5992483A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify at a high speed the information processing (fetching, feed and substantial operation of data) of a microcomputer system, by providing the function of a random access memory and the function of a sequential memory to a semiconductor storage device. CONSTITUTION:A control circuit CONT produces various types of signals from the operation mode signals supplied from the outside of an IC to have selectively a random access action or a sequential action of a semiconductor memory device. An action switch signal C selects the random access and sequential actions at a high level and a low level respectively. Such a switching action is distinguished by the fact that, for example, a multiplexer MPX is set at the side of an address buffer ADB and an address signal AD1 is transmitted when a signal phimx is set at a high level, while the MPX is set at the side of a counter COUNT and an address signal AD2 is transmitted if the signal phimx is set at a low level.

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

An object of the present invention is to provide a new semiconductor memory device with expanded functionality.

Other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

A block diagram of an embodiment of the invention is shown in the drawings.

In the figure, each circuit block surrounded by a broken line is formed on a 11-piece semiconductor substrate using a known semiconductor integrated circuit manufacturing technique.

Although not particularly limited, the memory array M-ARY uses static flip-flop circuits as memory cells and is arranged in a matrix.

The X decoder X-DCR is connected to the memory array M-ARY
Word line selection is performed. Y-decoder y-DCR performs data line selection. In this embodiment, n sets of data lines are selected by one data line selection signal, so n-bit data is written and read. Therefore, the input/output circuit I10 is composed of n sets of data input circuits and data output circuits.

The address signal AD supplied to the X and Y decoders X and Y-DCH is sent to the following two addresses via a multiplexer MPX.
Different types of address signals ADI and AD2 are selectively supplied.

The address buffer ADB is connected to the memory array M-AR.
It is used to select Y at any time (random access), receives an address signal supplied from outside the IC, and forms one of the address signals ADI.

The counter C0UNT is an up/down counter that is used to sequentially select the memory array M-ARY, and performs an address increment operation according to a timing signal φ supplied from outside the IC. .

The control circuit C0NT forms various control signals for causing the semiconductor memory device to selectively perform the above-mentioned random access operation or sequential operation in accordance with an operation mode signal from outside the IC.

Among the operation mode signals, WE is a write 1-enable signal, and for example, a high level instructs a read operation, and a low level instructs a write operation.

Specifically, the control timing φrw of the input/output circuit 110
For example, if this signal φrw is at a high level, the data output circuit is operated to send read information from the selected memory cell to the outside of the IC, and the signal φrt+
If is at a low level, the data input circuit is operated to transmit write information supplied from outside the IC to the selected memory cell.

C8 is a chip selection signal; for example, if the signal is at a high level, this IC chip is placed in a non-selected state, and if it is at a low level, this IC chip is placed in a selected state. Specifically, if it is at the low level, it receives the timing signal φa that activates the address buffer ADB and the input timing signal φ of the counter C0UNT.

C is an operation switching signal, for example, a high level random access operation, and a low level a sequential operation. This kind of operation switching can be done by, for example,
If the signal φmx is at a high level, the multiplexer MPX is set on the address buffer ADB side to transmit the address signal ADI, and if the signal ψmx is at a low level, the multiplexer MPX
With X on the counter C0UNT side, address signal AD2
It is distinguished by conveying the following.

U/D is an up/down operation control signal; for example, if it is at a high level, it causes the counter C0UNT to operate as an amplifier count, and when it is at a low level, it causes the counter C0UNT to perform a down-count operation.

Next, a case will be described in which the semiconductor memory device IC of this embodiment is operated as a random access memory.

First, the operation mode signal C is set to high level as described above. Then, multiplexer MPX transmits the signal on the address buffer ADB side to the X decoder and Y decoder. Therefore, the known random access memory
(RAM), the address buffer ADB receives an external address signal AD1' in synchronization with the timing signal φa generated when the chip selection signal C8 changes to low level.
is taken in and processed into an internal address signal ADZ.

This internal address signal ADI is sent to the multiplexer MPX
The signal is supplied to the X decoder and Y decoder through the memory cell, and a memory cell selection operation is performed. If the write enable signal WE is at a high level, the data output circuit operates, so that the information held in the selected memory cell is output and read out. Also, if the write enable signal WE is at low level, the data input circuit operates, so
External write data is transmitted to the selected memory cell and writing is performed.

Note that in this embodiment, the counter C0UNT
is placed in a counting operation state by the change in the low level of the chip selection signal C3, but does not substantially perform any operation because the timing φ is not input.

Further, a case will be described in which the above-described semiconductor memory device IC is operated as a sequential memory.

The operation mode signal C is set to low level as described above. Then, multiplexer MPX outputs counter C0UN.
Address signal AD2 formed by T is sent to an X decoder and Y
Tell the decoder. Then, when the chip selection signal C8 becomes low level and the timing signal φ is input, the counter C0UNT performs a counting operation, and when the write enable signal WE is low level, the control signals U/P are set to high level and performs an amplifier counting operation. Therefore, an address signal that changes sequentially starting from the first address is formed. Therefore, a memory cell corresponding to this address signal AD2 is selected, and write data signals input in synchronization with the timing signal φ are sequentially written. On the other hand, in the above state, when the write enable signal WE is set to high level, the control signal U/P is set to low level, and the counter CO
Since U, N, and T are reversely counted down from the write final address, the written data is read out sequentially in reverse in synchronization with the timing signal φ.

In other words, it is possible to perform an operation equivalent to that of a conventional sequential memory.

In this embodiment, it is possible to have a function as a random access memory and a function as a sequential memory. Therefore, for example, if the device of this embodiment is used as an input/output data buffer for a microcomputer system, the sequential memory function can be used to easily and directly import data from a terminal device, etc. At the same time, it is possible to selectively read only necessary data out of this written data using a random access memory function, perform information processing, and rewrite it to a predetermined address. In this way, by using the semiconductor memory device of this embodiment, information processing (data acquisition, transmission, and substantial calculation) in a microcomputer system can be performed easily and at high speed.

The invention is not limited to the above embodiments.

Claims (1)

[Claims] 1. A function to write and read data of ×n bits at any time, a function to sequentially write and read data of ×n points according to an internally generated address signal, and both of the above functions can be performed by an external control signal. What is claimed is: 1. A semiconductor memory device comprising: a control function for selecting according to the following. 2. The semiconductor memory device according to claim 1, wherein the internal address signal is generated by a bidirectional counter circuit. 3. The semiconductor memory device according to claim 1 or 2, wherein the memory array section holding the xn bit data is constituted by static memory cells.