JPH03263686A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease number of devices required for decoding and to reduce remarkably a chip area by using one D flip-flop in common for fetch plural bits of a column address and operating the flip-flop in time division. CONSTITUTION:The device is provided with address pointers comprising plural selectors 1 receiving each of plural bits of an address signal and decoding the signal, plural D flip-flops 2 receiving an output of each selector 1 and shifting the signal sequentially synchronously with a timing signal and shifting the signal sequentially and a decoder 7 decoding an address signal. Then each selector 1 decodes prescribed number of consecutive bits among bits of the address signal respectively and the address signal is decoded while the result of decode is shifted by the D flip-flops 2 provided corresponding to the selector 1. Thus, plural bits of the address signal are decoded by one set of selector provided corresponding to one of the D flip-flops forming the serial pointers.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) 1. The present invention relates to a semiconductor memory device having a random access port and a serial access port.

(Prior Art) FIG. 6 is a block diagram showing a conventional example of this type of semiconductor memory device.

This conventional example has a random access port 60 (hereinafter referred to as RAM).
RAM port 60 has memory cell array 61) sense amplifier 62 (hereinafter referred to as 5A62), row decoder 63 (hereinafter referred to as X- Dc
c63), column de''-da64 (hereinafter referred to as Y-De
c64) and a random port 65.

In addition, the SAM boat 70 is a 1 in the ΔM boat 60.
a serial data holding circuit 71 (hereinafter referred to as line buffer 71) that holds data for one word as serial access data; a data transfer gate 73 that transfers data from the RAM boat 60 to the line buffer 771;
It consists of a serial pointer 72 for serial data access consisting of a shift register, and a serial port 74.

Here, the dual port memory to which this conventional example belongs will be briefly explained. What is dual port memory? Traditional RA
Random access function (RAM
A cycle (hereinafter referred to as a data transfer cycle or D
), and during this DT cycle, X-[
) The data of one row of memory cells selected by ec is transferred to the corresponding LB [- in serial access, and the data transferred to this LB is serially high-speed accessed by SR asynchronously with the RAM port. It has the added function of

FIG. 7 is a diagram showing a strategic layout when the memory array section of a conventional dual port memory is divided into two parts.

During the DT cycle, one word of data in the cell arrays 81 and 82 selected by the row address is amplified by sense amplifiers 87 and 88, respectively, and sent to line buffers 8 and 9.
Transferred to 0.

Further, FIG. 8 is a circuit diagram showing a serial pointer 72 used in the serial access port 70 of FIG. 6.

A D-type flip-flop circuit (hereinafter referred to as D, F/F) constituting the serial pointer 72 takes in an arbitrary column address signal (\SO~YS127>) by the Yl- signal, and uses the point of the taken address to set the clock C.
It is designed to shift up sequentially in synchronization with LK. Each output of the serial pointer 72 functions as a switch that connects a line buffer holding serial data to a data bus.

[Means to solve the problem]

The semiconductor memory device of the present invention includes a plurality of selectors that respectively input and decode a plurality of bits of an address signal, and a plurality of D-type flip 70 knobs that input the output of each selector and sequentially shift them in synchronization with a timing signal. , and a decoder that decodes the address signal based on the output of each type flip 70 block.

[Operation] Each selector decodes a predetermined number of successive bits of each bit of the address signal, and the address signal is decoded while shifting the decoded result by a D-type flip-flop provided corresponding to the selector.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a serial pointer of a first embodiment of a semiconductor memory device of the present invention, FIG. 2 is a timing diagram showing the relationship of each signal in the embodiment of FIG. 1, and FIG. 1
FIG. 4 is a circuit diagram showing the selector shown in the figure, and FIG. 4 is a timing chart showing the relationship between the respective signals in FIG.

1 is a 1/2 selector that selects a column address,
2 is a D-type flip-flop (hereinafter referred to as
3 is a counter made up of D-F/F, 4 is a line buffer that holds data, 5 is a tri-state buffer, and 6 is serial data that takes in the data transferred from the line buffer. bus, 7 is a sub decoder.

The data of DF/F2 that constitutes the serial pointer is taken in from two systems: one is the column address information YSO, YS1. ~． YS127, and the other is the angle state of D-F/F2 in the previous stage (lower b1t).

Column address fi! 'I\, l1IYSO, YSI,
. . . , YS127 are controlled by the take-in signal Y, and the information of the previous stage pointer is controlled by the clock CL K (A) or the clock CL K (B). Regarding the column address information YSO, YSI, . The principle does not change in the case of 5rli with 2 or more addresses. It is connected so as to be taken in as column address information data of the D-F/F circuit that constitutes the pointer. As a result, the lower bits are shifted up sequentially from the selected address in synchronization with the clock CI K (B).

The output of each pointer is input to the rib decoder 7 as an activation signal. This sub-decoder 7 receives the output of the pointer as well as the column address signal input to the main decoder, and also receives the output of the counter 3, which is operated by a signal φ synchronized with the SC clock generated externally to the pointer. I am inputting it.

FIG. 5 is a circuit diagram showing a serial pointer according to a second embodiment of the present invention.

This embodiment uses the time-divided clock C1 of the embodiment of FIG.
The pointer is controlled using a one-phase clock CLK instead of K(A), C1, and K(B). The other points are the same as the embodiment shown in FIG. 1, so their explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention uses one selector provided in correspondence with one D-type flip-flop that intercepts a serial pointer to address multiple bits of an address signal. However, by sharing the capture of multiple bits of the column address with one D-type flip-flop and performing time-division operation, the number of devices required for the data-reader can be reduced by the amount of shared data, and by extension It has the effect of significantly reducing facial appearance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a serial pointer of a first embodiment of a semiconductor memory device of the present invention, FIG. 2 is a timing chart showing the relationship of each signal in the embodiment of FIG. 1, and FIG.
4 is a timing chart showing the relationship between the signals in FIG. 3, and FIG. 5 is a circuit diagram showing the selector of the present invention.
FIG. 6 is a block diagram showing a conventional example; FIG. 7 is a circuit diagram showing a schematic layout of the conventional example; FIG. 8 is a circuit diagram showing a conventional serial pointer. It is a diagram. 1... Selector, 2... D-F/F, 3... Counter, 4... Line buffer, 5... Tri-state buffer, 6... Serial data bus, 7... Sub-decoding circuit, Ql, Q2. Q3...MOS transistor.

Claims (1)

[Claims] 1) In a semiconductor memory device having a random access port and a serial access port, a plurality of selectors each inputting and decoding a plurality of bits of an address signal, and a timing signal inputting the output of each selector. 1. A semiconductor memory device comprising an address pointer comprising: a plurality of D-type flip-flops that shift sequentially in synchronization with the D-type flip-flop; and a decoder that decodes the address signal based on the output of each D-type flip-flop.