JPH02206096A - Memory device - Google Patents

Abstract

PURPOSE:To remarkably curtail the number of wirings by providing a first switch for outputting parallel data to a bit selective line at the time of read, and a second switch for connecting an output of a decoder to the bit selective line at the time of write. CONSTITUTION:At the time of write of series data, when a WRITE terminals is set to '1' and X0-X2 terminals and Y0-Y1 terminals are varied as C-E, F and G respectively, data of an SX terminal is supplied to an inverter 381 through an inverter 384. At the time, t1, the X0 terminal is shifted from '1' to '0', and thereafter, written in a data store bit 370. Thereafter, in the same way, the data is written one after another in each store bit of a third frame to the time t2, and written in a second frame at t2 to t3, and in a first frame 100 at t3 to t4. On the other hand, at the time of read-out, the WRITE terminal is set to '0', and frame selective data is supplied to Y0 and Y1. In such a way, at the time of read-out of parallel data and write of series data, by executing them by using a common line, the number of wiring can be curtailed remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of a serial write/parallel read type memory device.

BACKGROUND OF THE INVENTION Serial data communication devices, which have been widely used in one-chip microprocessors, are composed of shift registers, shift counters, and buffer registers.
This is shown in Japanese Patent No. 482. When receiving serial data, one frame of data is stored in the buffer register (in most cases, one frame consists of 4 or 8 bits).
After storing the data, parallel data is sent out from the shift register, but in order to receive several frames of data at a time, multiple sets of buffer registers must be prepared, and the wiring at the output part of the parallel data is required. There is a problem in that the amount increases.

Problems to be Solved by the Invention Therefore, the problem to be solved by the present invention is to realize a group of buffer registers that does not require an increase in wiring for data input/output sections even when serial data for several frames are received in succession, and more specifically, to The goal is to realize a memory device that has a small number of wires, can store data for multiple frames, and can also retrieve data in parallel.

Means for Solving the Problems In order to solve the above-mentioned problems, the memory device of the present invention includes a frame configured by arranging a plurality of data storage bits, a decoder for selecting a bit position of the frame, and a decoder for selecting the bit position of the frame, and a plurality of bit selection lines respectively connected to the storage bits; a first switch means for outputting parallel data from the data storage bits to the bit selection lines when reading data; A second switch means is provided for connecting the output of the decoder.

In the present invention, with the above-described configuration, reading of parallel data and selection of bit positions during writing of serial data are performed via a common line, and the number of wirings required to perform these operations is greatly reduced. be done.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit diagram of a memory device according to an embodiment of the present invention, in which a first frame 100 includes data storage bits 110 . 120. 130.140,15
It is composed of 0,160,170,180.

The first bit 110 of the data storage bits is
11 and a 3-state inverter 112, a 3-state buffer 113 that sends the output of this unit memory cell to the DO terminal, and a 3-state inverter 114 that transmits write data from the SX terminal to the inverter 111. XO terminal, XI terminal, X2
When the first bit of the first frame is selected by the data supplied to the terminal, YO terminal, and Yl terminal,
It is composed of a NAND gate 115 that puts the output of the state inverter 112 in a high impedance state, and an inverter 116 that puts the output of the 3-state inverter 114 in a high impedance state when the 3-state inverter 112 is active. The second bit 120 to the eighth bit 180 also have the same configuration. Also, similar to the first frame 100, a second frame 200. A third frame 300 is configured.

The inputs of the 3-state inverters for each bit that transmit write data to the memory cells are commonly connected to the SX terminal, and the outputs of the 3-state buffers for each bit that transmit the output of the memory cells are DO to D7, respectively. connected to the terminal.

On the other hand, a bit selection line group 400 is connected to the data read line connected to the data terminal group DO-D7, and the bit selection line group 400 is the output of a switch group 500 constituted by eight 3-state buffers. A decoder 600 is connected to the input side of the switch group 500.
output is supplied.

When writing serial data from the Sx terminal to each memory cell, the first frame 100~ is written to the YO and Yl terminals.
2-bit data for selecting one of the third frames 300 is supplied, and the xO terminal, the XI terminal,
3-bit data specifying the bit position of the selected frame is supplied to the X2 terminal, and the level of the WRITE terminal is temporarily shifted to (11).

Furthermore, when reading parallel data from the DO to D7 terminals, the level of the WRITE terminal is fixed to '0', and 2 bits for selecting one of the first frame 100 to third frame 300 are sent to the YO and Yl terminals. data is supplied.

The operation of the memory device configured as described above will be explained based on the configuration diagram in FIG. 1 and the timing chart of the main parts shown in FIG. 2.

First, Figure 2A shows the clock signal waveform for receiving serial data, Figure 2B shows how the input data changes from the SX terminal, and Figure 2C, D, and E show the xO terminal and XI, respectively. Figure 2 F and G show the signal waveforms supplied to the YO and Yl terminals, respectively.

In the device shown in Fig. 1, in order to write serial data to the first frame 100, the level of the WRITE terminal is fixed to 1'', and the levels supplied to the xO terminal to x2 terminal, YO terminal, and Yl terminal are set. Figure 2 C-
It may be changed like E, F, G.

That is, before time t1 in Fig. 2, the levels of the XO terminal to X2 terminal, YO terminal, and Yl terminal are all 1'.
Therefore, the output levels of AND gate 608 and AND gate 3 are both "1", and the output level of NAND gate 385 forming data storage bit 380 of third frame 300 is 10'. Therefore, at this point, the data at the SX terminal is transferred to the inverter 38.
4 to the inverter 381. Time t! When the leading edge of the clock signal arrives at , the level of the XO terminal changes from 1' to 0' (FIG. 2C), thereby causing the output level of the AND gate 607 constituting the decoder 600 to change to 1'. Then, data is written to the data storage bit 370. Thereafter, serial data is sequentially written into each data storage bit of the third frame 300 until time t2.

When the leading edge of the clock signal arrives at time t2, the levels of the xO terminal to X2 terminal each become 1.
At this time, the level of the YO terminal shifts to 0' (FIG. 2F), and as a result, the output level of the AND gate 2 shifts to 1', and from this point until time t3, the level of the YO terminal shifts to 0' (FIG. 2F). Serial data is written to each data storage bit constituting two frames 200.

Furthermore, serial data is written into each data storage bit of the first frame 100 from time t3 to time t4.

On the other hand, in order to read data from the memory device shown in FIG. 1, it is sufficient to fix the level of the WRITE terminal to 'O' and then supply frame selection data to the YO and Yl terminals. For example, to read the parallel data stored in the first frame 100, it is sufficient to set the level of both the YO terminal and the Y1 terminal to 1'.
The output levels of the D gate 1 and the AND gate 12 shift to 1', and the parallel data stored in the first frame 100 is sent to the data terminal group DO-D7 via the 3-state buffers 113-183.

In this manner, in the memory device shown in FIG. 1, the reading of parallel data and the selection of bit positions when writing serial data are performed via a common line, that is, a line for reading parallel data. This greatly reduces the number of wiring in the device.

Effects of the Invention As is clear from the above description, the memory device of the present invention includes input switch means (for example, , 3-state inverter 114)
a frame (e.g., a first frame 100) configured by arranging a plurality of data storage bits (e.g., data storage bits 110), a decoder 600 for selecting a bit position of the frame, and a decoder 600 for selecting a bit position of the frame; A plurality of bit selection lines (a group of bit selection lines 400 in the embodiment) each connected to a bit, and a first switch means (first switch means) for outputting parallel data from the data storage bit to the bit selection line when reading data. (In one frame, it is composed of 3-state buffers 113 to 183.) and a second switch means (switch group 500) that connects the decoder to the bit selection line when writing data. A memory device capable of writing serial data and retrieving parallel data can be realized with a small amount of wiring, resulting in great effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention, and FIG. 2 is a timing chart of the main parts of FIG. 100...First frame, 110...Data storage bit, 114...3-state inverter. 113...8 state buffers, 200-...
2nd frame, 300...3rd frame,
400...Bit selection line group, 500...Switch group. 600...decoder.

Claims (1)

[Claims] (1) A frame configured by arranging a plurality of data storage bits, each including a unit memory cell and an input switch means for connecting the data input terminal of the unit memory cell to a common input line, and the bits of the frame. a decoder for selecting a position; a plurality of bit selection lines respectively connected to the data storage bit; a first switch means for outputting parallel data from the data storage bit to the bit selection line when reading data; A memory device comprising second switch means for connecting the output of the decoder to the bit selection line when writing.