JPH10112178A - Fifo memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify design work by making constitution using a hard macro- module. SOLUTION: When digital data is transferred from a first circuit 1 operating with a different clock to a second clock, a FIFO memory 10 having a function performing receipt and delivery of data is designed. A memory module 11 consisting of plural storing sections 11a-11f and a control module 12 consisting of plural control sections 12a-12f are arranged. Each control section is provided with a function storing a flag W (logical value 1) indicating a write-in place and a flag R (logical value l) indicating a read-out place, and a function in which whenever writing processing and reading processing are finished, these flags are transferred to a control section of a poststage. When the flag W catches up the flag R, a signal FULL indicating a full state is transmitted, when the flag R catches up the flag W, a signal EMPTY indicating an empty state is transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO memory, and more particularly, to a FIFO memory having a function of transferring data between two circuits when transferring digital data between two circuits having different operation speeds. .

[0002]

2. Description of the Related Art When digital data is transferred between circuits having different operation speeds, since the clock frequencies of the two are different, a FIFO (First In First Out) memory for temporarily storing data and mediating the transfer is provided. It must be provided in the middle. That is, when data to be transferred is output from the first circuit that operates on the first clock, the second circuit
The second circuit that operates with the clock cannot capture this data immediately, so it is necessary to temporarily store the data using a FIFO memory. FIFO
The data stored in the memory is taken into the second circuit in the order of storage in synchronization with the second clock.

A conventional FIFO memory generally uses a dual-port SRAM. Data output from the first circuit in synchronization with the first clock is written to a predetermined address through a first port in the dual-port SRAM, and the written data is transmitted to a second port. The data is read out to the second circuit in synchronization with the second clock. This dual port SRA
The write address and the read address for M are managed separately, and a pointer is provided for each address. When data is output from the first circuit, the data is written to the address indicated by the write pointer, and the value of the write pointer is updated after writing. On the other hand, data is read from the address indicated by the read pointer to the second circuit, and the value of the read pointer is updated after the read. In this way, the FIFO memory that mediates both circuits performs the first-in first-out processing of data.

[0004] Further, a general FIFO memory has a first
F indicating that the memory is full for the circuit of FIG.
It has a function of transmitting a ULL and a function of transmitting a signal EMPTY indicating that the memory is empty to the second circuit. This is because if the data fetch processing to the second circuit is delayed, the FIFO memory becomes full due to the data successively output from the first circuit, so that the signal FULL is transmitted to the first circuit. If the data output processing is interrupted, and conversely, if the data output processing from the first circuit is delayed, the data to be captured by the second circuit is in an empty state in which no data exists in the FIFO memory. , And the signal EMPTY to the second circuit to interrupt the data fetch process. Signal FULL
The signal EMPTY can be generated based on the difference between the value of the write pointer and the value of the read pointer.

[0005]

As described above, a conventional general FIFO memory is a dual-port SRAM.
This dual port SRAM
A dedicated control unit is required to control access to the system. The dedicated control unit is a circuit for managing the write pointer and the read pointer, and performing processing for generating the signal FULL and the signal EMPTY. However, a general dual-port SRAM can be designed by using a ready-made hard macro module prepared in a cell library. A module cannot be used, and a software macro module (netlist module) in which components such as a counter, a comparator, and a combinational logic circuit are combined must be newly designed each time. In recent years, it has been mainstream to efficiently design ICs by automatic placement and routing using an automatic mask layout tool, but it is not possible to design using only ready-made modules prepared in a cell library. This is a great obstacle to performing such an efficient design work.

For example, at the stage of performing a logic design of a circuit in which a FIFO memory is incorporated, it is necessary for a designer to perform a design by estimating delay characteristics of the FIFO memory. In addition, if automatic placement and routing using an automatic mask layout tool is performed based on this logical design and the delay characteristics in the actual layout are significantly different from the estimated values, it is necessary to perform the logical design again. Of course, in order to avoid having to perform such a redesign, it is possible to perform a logic design with a sufficient margin for estimating the delay characteristics, but the more margin, the more
Only a logical design that is inferior to the original effective ability can be performed.

In particular, in recent years, ASICs (Application
Demand for Specific Integrated Circuits (ICs) is increasing, and SOG-GAs (Sea Of
Designing an ASIC using a gate-gate array (gate-laying gate array) has been widely performed. In a circuit designed using such an SOG-GA, a FIFO memory having an arbitrary number of bits and an arbitrary number of words is required, and a FIFO memory having an arbitrary storage capacity is required. The task of designing a memory as a soft macro module requires a lot of labor and time. In particular, if it is necessary to realize a FIFO memory having a number of words other than the number represented by a power of 2 (2, 4, 8, 16, 32,...), The address pointer may be constituted by a simple counter. No, logic design has to be a very complex task.

SUMMARY OF THE INVENTION An object of the present invention is to provide a FIFO memory and a method for manufacturing the same, which can simplify the design work.

[0009]

[Means for Solving the Problems]

(1) The first aspect of the present invention is a method for transferring digital data from a first circuit operating on a first clock to a second circuit operating on a second clock, between the two circuits. A memory module in which a plurality of M storage units having a capacity corresponding to the number of bits of data to be transferred are arranged in a FIFO memory having a function of transferring data by
A control module comprising M control units provided corresponding to each storage unit is provided, and each control unit has a function of storing a write location flag W and a read location flag R, And a function of transferring the write location flag W and the read location flag R to a predetermined control unit at the first stage when a reset signal is supplied, so that the first When the data is output from the circuit in synchronization with the first clock, the memory module writes the output data to the storage unit corresponding to the control unit in which the write location flag W is stored at that time. The control unit that has performed the processing and has stored the write location flag W performs a process of transferring the write location flag W to the control unit at the subsequent stage, and the data synchronized with the second clock from the second circuit. The input request is Then, the memory module performs a process of reading data from the storage unit corresponding to the control unit in which the read location flag R is stored at that time and giving the data to the second circuit, and the read location flag R is stored. The control unit performs a process of transferring the read location flag R to the subsequent control unit. When each control unit stores the read location flag R, the control unit receives the transfer of the write location flag W from the previous stage. At the same time, a signal FULL indicating that the FIFO memory is full is transmitted to the first circuit. Conversely, when the write location flag W is stored, the read location flag R When receiving the transfer, a signal EMPT indicating to the second circuit that the FIFO memory is empty
The processing for transmitting Y is performed.

(2) The second aspect of the present invention is the above-mentioned first aspect.
In the FIFO memory according to the aspect, a storage unit having a capacity of L bits is configured by arranging L one-bit storage elements in the vertical direction, and arranging M storage units in the horizontal direction. To form a memory module having a capacity of L bits and M words, and to form a control module by arranging M control units in the horizontal direction at the same pitch as the storage unit. The control section and the control section are arranged adjacent to each other.

(3) The third aspect of the present invention is the above-mentioned second aspect.
In the FIFO memory according to the aspect, when the reset signal is applied, the first control unit that does not generate any of the write location flag W and the read location flag R, and when the reset signal is applied, the write control is performed. And a second control unit that generates both the location flag W and the reading location flag R, and (M-1) first control units are arranged, and one second control unit is arranged. Thus, a control module is configured.

(4) The fourth aspect of the present invention is the above-mentioned second aspect.
Alternatively, in the FIFO memory according to the third aspect, when each control unit stores the write location flag W, the control unit outputs a write enable signal WW to a storage element in a corresponding storage unit, When the flag R is stored, the read permission signal RR is output to the storage element in the corresponding storage unit.

(5) The fifth aspect of the present invention is the above-mentioned second aspect.
In the method for manufacturing a FIFO memory according to the aspect, each storage element and each control unit are prepared in the form of cells registered in a library as hard macro modules, and L cells for the storage elements are vertically arranged. A memory module having a capacity of L bits and M words is configured by arranging M cells in the horizontal direction, and M cells for the control unit are arranged in the horizontal direction at the same pitch as the cells for the storage elements. The control module is constituted by.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings.

§1. Introduction conventional general FIFO memory, briefly described conventional general FIFO structure of the memory. FIG. 1 is a conceptual diagram showing a general FIFO memory 3 used for mediating digital data transfer between a first circuit 1 and a second circuit 2 having different operation speeds. It is. Since the first circuit 1 operates with the first clock CK1 and the second circuit 2 operates with the second clock CK2, both circuits perform an asynchronous operation. In
It is necessary to mediate the FIFO memory 3 for absorbing the time difference. The FIFO memory 3 shown here is provided with a total of six storage units having a capacity corresponding to the number of bits of data to be transferred. For example, if the data to be transferred is 8
If the data is bit data, the six storage units A to F
Have a storage capacity for storing 8-bit data, and the FIFO memory 3 functions as a memory having a capacity of 8 bits and 6 words.

Here, the first circuit 1 to the second circuit 2
, The following processing is performed. First, the first circuit 1
Thereafter, data X1, X2, and X3 to be transferred are sequentially output at a timing synchronized with the first clock CK1. These data are sequentially stored in an empty storage unit in the FIFO memory 3. On the other hand, the second circuit 2
When there is a data fetch request from the FIFO memory 3, the data stored in the FIFO memory 3 are sequentially read out in the order in which they are stored at the timing synchronized with the second clock CK2.
In order to perform such first-in first-out processing, a write pointer Pwrite and a read pointer Pread are used. The write pointer Pwrite is a pointer that indicates a storage unit to which data output from the first circuit 1 is to be written.
The read pointer Pread is a pointer that indicates a storage unit from which data is to be read to the second circuit. For example, in the example shown in FIG. 1, data X is already stored in the storage units A, B, and C.
1, X2, X3 are written, and the write pointer Pwr
ite indicates the storage unit D to which data is to be written next. When the next data X4 is output from the first circuit 1, this data X4 is written to the storage unit D pointed to by the write pointer Pwrite, and the write pointer Pwrite points to the next storage unit E. Will be updated as follows. On the other hand, when reading data to the second circuit 2,
First, the data X1 is read from the storage unit A pointed to by the read pointer Pread, and the read pointer Pread is updated so as to point to the next storage unit B.

The FIFO memory 3 has a function of transmitting a signal FULL indicating that all storage units are full to the first circuit 1 and a signal EMPTY indicating that all storage units are empty. To the second circuit 2. For example, in the state shown in FIG. 1, new data X4, X4
When 5 and X6 are written, all the storage units become full, so that the signal FULL is transmitted to the first circuit 1.
When the signal FULL is transmitted, the first circuit 1 temporarily suspends the data transfer process. Conversely, in the state shown in FIG. 1, when all the stored data X1, X2, and X3 are read out without performing further data writing, all the storage units become empty, so the second Signal EMPTY is transmitted to circuit 2. Second circuit 2
Suspends the data fetch process when this signal EMPTY is transmitted.

Conventionally, a dual-port SRAM has been used to realize a FIFO memory having such a function. FIG. 2 is a block diagram showing a general configuration of a conventional FIFO memory. The main components of the FIFO memory are a dual-port SRAM 4 and a control unit 5. The dual-port SRAM 4 has a write port and a read port, and data output from the first circuit 1 is written from the write port at a timing synchronized with the first clock CK1, and the second circuit 2 The data to be taken into is read from the read port at a timing synchronized with the second clock CK2. Control part 5
Has a function of instructing a write address to a write port and instructing a read address to a read port. These addresses correspond to the write pointer Pwrite and the read pointer Pread in FIG. 1. The data applied to the write port is stored at the address location in the SRAM designated by the write address, and Data retrieved from the port will be retrieved from the address location in the SRAM specified by the read address. The control unit 5 performs a process of updating the write address or the read address every time the write process or the read process is performed, and when the difference between the two addresses satisfies a predetermined condition, the signal FULL or the signal EMPTY. The process of generating and transmitting is performed.

When designing such a conventional FIFO memory, a general-purpose dual-port SRAM prepared in a cell library as a hard macro module may be used as it is for the dual-port SRAM 4. Must be newly designed each time as a soft macro module in which components such as a counter, a comparator, and a combinational logic circuit are combined. As described above, a great deal of labor and time are required for the design work.

§2. FIFO Memory According to the Present Invention The basic configuration of the FIFO memory 10 according to the present invention is shown in the block diagram of FIG. The main components of the FIFO memory 10 are a memory module 11 and a control module 12
It is. The memory module 11 is a module in which a plurality of M storage units having a capacity corresponding to the number of bits of data to be transferred are arranged. In the illustrated example, six storage units 11 a having a capacity of 8 bits are used. To 11f constitute the memory module 11. On the other hand, the control module 12 is a module including M control units provided corresponding to these storage units, and in the illustrated example, is provided corresponding to the six storage units 11a to 11f, respectively. 6
The control modules 12a to 12f
Is configured.

The 8-bit data X1, X2, X3,... Output from the first circuit 1 are written to any of the six storage units 11a to 11f in the memory module 11 and stored therein. Data X1, X2, X3
The data are read out to the second circuit 2 in the order in which they are stored. At this time, the control module 12 instructs which storage unit to write to or from which storage unit to read. . In order to issue such an instruction, each of the control units 12a to 12f is provided with an area for storing a writing location flag W and a reading location flag R, respectively. In the illustrated example, each control unit is divided into upper and lower regions by broken lines, and the upper part is an area for storing the writing location flag W, and the lower part is an area for storing the reading location flag R. Here, both the write location flag W and the read location flag R are represented by a bit “1”, and an area in which a bit “0” is written indicates a state where no flag is stored, and a bit “1”. Indicates the state where the flag is stored.

Specifically, in the example shown in FIG.
The writing location flag W is stored in the control unit 12d, and the reading location flag R is stored in the control unit 12a. The write location flag W indicates a location where the data is to be written when the data is output from the first circuit 1.
The read location flag R indicates a location where the data should be read when the data is loaded into the second circuit 2.

When data is output from the first circuit 1 in synchronization with the first clock CK1, the memory module 11
Performs a process of writing the output data to the storage unit corresponding to the control unit in which the writing location flag W is stored at that time, and the control unit that has stored the writing location flag W A process of transferring the write location flag W to the subsequent control unit is performed. For example, when the data X4 is output from the first circuit 1 in the illustrated state, the data X4 is written to the storage unit 11d corresponding to the control unit 12d in which the write location flag W is currently stored. Will be. Then, the write location flag W is transferred from the control unit 12d to the control unit 12e at the subsequent stage (the upper part of the control unit 12d becomes bit "0" and the upper part of the control unit 12e becomes bit "1"). .

On the other hand, from the second circuit 2 to the second clock C
When there is a data input request in synchronization with K2, the memory module 11 reads data from the storage unit corresponding to the control unit in which the read location flag R is stored at that time and gives the data to the second circuit. Is performed, and the control unit storing the readout location flag R performs a process of transferring the readout location flag R to the control unit in the subsequent stage. For example, when data is taken into the second circuit 2 in the illustrated state, the data X1 stored in the storage unit 11a corresponding to the control unit 12a in which the readout location flag R is currently stored is stored in the second circuit 2. 2 will be read. Then, the read location flag R is transmitted from the control unit 12a to the control unit 12b in the subsequent stage.
(The lower part of the control unit 12a becomes bit “0” and the lower part of the control unit 12b becomes bit “1”).

As described above, the write location flag W and the read location flag R are always stored in any one of the control units 12a to 12f constituting the control module 12, and are synchronized with the first clock CK1. Each time the write processing is executed, the write location flag W is transferred to the subsequent control unit, and every time the read processing synchronized with the second clock CK2 is executed, the read location flag R is transmitted to the subsequent control unit. Is transferred.
In the illustrated example, the positions A, B, C, D,
Each stage is defined in the order of E and F, and each flag is transferred in the order of the control units 12a, 12b, 12c, 12d, 12e, and 12f (bit "1" is 1 in the figure).
It will gradually move to the right.) However, the position A is defined as a subsequent stage of the position F, and the control unit 12f
Thus, a circulation loop is formed in which the flags transferred from the control unit 12a return to the control unit 12a.

When the FIFO memory 10 is used for the first time, an initial setting is performed by giving a reset signal. That is, when a reset signal is applied to the FIFO memory 10, the write location flag W and the read location flag R are both stored in the control unit 12a, which is the first stage (in the figure, the upper left and lower left and right sides). First, a bit "1" is written in each case, and a bit "0" is written in all other squares.) However, the position of the first stage does not necessarily have to be position A, and may be defined at any position. In this initial setting state, all the storage units 11a to 11f configuring the memory module 11 are set.
Is treated as empty.

After the reset, the first data X1 output from the first circuit 1 is written to the storage unit 11a corresponding to the control unit 12a in which the writing location flag W is stored at that time. The write location flag W is set in the next control unit 1
2b. Subsequently, the data X2 output from the first circuit 1 is written in the storage unit 11b corresponding to the control unit 12b in which the writing location flag W is stored at that time, and the writing location flag W is The data is transferred to the control unit 12c. Further, when the data X3 is output from the first circuit 1, the data X3 is stored in the writing location flag W at that time.
Storage unit 11c corresponding to the control unit 12c in which is stored
And the write location flag W is transferred to the next control unit 12d. The state of each flag shown in FIG. 3 indicates the state at this time. As described above, if the write location and the read location of the data are determined by the write location flag W and the read location flag R stored in the control module 12, data can be transferred on a first-in first-out basis.

In this FIFO memory 10, when all the storage units 11a to 11f are full, a signal FULL is transmitted to the first circuit 1, and when all the storage units 11a to 11f are empty, the signal EMPTY is output. Is transmitted to the second circuit 2. This is because the control units 12a to 12f have the following functions. That is, each control unit 1
2a to 12f receive the transfer of the write location flag W from the preceding stage while storing the read location flag R, the first
FULL is transmitted to the circuit 1 of FIG. 1, and conversely, when the read location flag R is transferred from the preceding stage while the write location flag W is stored, the signal E is transmitted to the second circuit 2.
It has a function of transmitting MPTY.

This function will be specifically described based on the example of FIG. For example, in the state shown in FIG.
Without reading data to circuit 2
When new data X4, X5, and X6 are output from the circuit 1, the data X4, X5, and X6 are written into the storage units 11d, 11e, and 11f, respectively, and all the storage units become full. At this time, the data X6 is stored in the storage unit 11
At the time point when the data is written to f, the process of transferring the write location flag W stored in the control unit 12f to the subsequent stage is performed, and the write location flag W is cyclically transferred to the control unit 12a. Will be. Then, the control unit 12a transmits the signal FULL to the first circuit 1 because the control unit 12a has received the transfer of the write location flag W from the previous stage while storing the read location flag R. Upon receiving the transmission of the signal FULL, the first circuit 1 temporarily suspends the data transfer process. Thereby, it is possible to prevent the FIFO memory 10 from overflowing.

Conversely, in the state shown in FIG. 3, when all the stored data X1, X2, X3 are read out to the second circuit 2 without further data writing, the entire storage section Becomes empty. At this time, the data X3
Is read from the storage unit 11c, the control unit 12c
Is transferred to the subsequent stage, and the read location flag R is transferred to the control unit 12d. Then, the control unit 12d receives the transfer of the read location flag R from the previous stage when the write location flag W is stored, so that the second circuit 2d
To transmit the signal EMPTY. The second circuit 2
When the transmission of the signal EMPTY is received, the data fetch process is temporarily suspended. Thus, erroneous data reading from the FIFO memory 10 can be prevented.

§3. The configuration of the FIFO memory according to the present invention
Advantages of the FIFO memory 10 according to the total process of the present invention described above, the memory module 11 and control module 12
Can be configured as a combination of hard macro modules prepared in the cell library, and the design work can be simplified. Hereinafter, this design method will be described.

First, as shown in FIG. 4, the cells of the 1-bit storage element 21 prepared in the cell library are arranged in the horizontal direction by M words, and the write data buffer 22 and the read data The cells of the buffer 23 are arranged to form the unit row unit 20. Here, the cell 21 of the 1-bit storage element and the cell 2 of the write data buffer
2. The cells 23 of the read data buffer are all versatile cells, and existing cells in a general cell library can be used as they are (these cells have vertical dimensions in the drawing). Use the same). Subsequently, as shown in FIG. 5, by arranging L unit row units 20 in the vertical direction, a memory module having a storage capacity of L bits and M words can be configured. Here, one storage unit is formed by the cells 21 of the L storage elements in each column arranged in the vertical direction (for example, the L storage cells arranged in the first column in FIG. 5). The storage unit 11a shown in FIG.
Is formed).

Subsequently, as shown in FIG. 6, M control unit cells 31 are prepared, and these cells are arranged side by side at the same pitch as the M storage units in the first to Mth columns. By doing so, a control module can be configured, and each storage unit and each corresponding control unit are arranged adjacent to each other. The cell 31 of each control unit is an element having the function described in §2, and is not prepared in an existing general cell library used conventionally. Therefore, in practicing the present invention, it is preferable to design the cell 31 of the control unit having such a function as a new cell and newly register it in the cell library. Since the cells 31 of the respective control units have the same function (when resetting the write location flag W and the read location flag R by a reset signal, a special cell having an initial setting function is prepared. However, this will be described in an embodiment to be described later), but the cell 31 of a single control unit may be registered in the library regardless of the number of words of the FIFO memory to be actually designed.

Finally, as shown in FIG. 7, a first clock signal CK1 used in the first circuit 1 is supplied to a control module composed of M control unit cells 31 by a write clock. The second clock signal CK2 used as the second clock signal WCLK is used as the read clock RCLK.
And the signal F transmitted from the cell 31 of each control unit
The present invention may be configured such that UL is supplied to the first circuit 1, a signal EMPTY transmitted from the cell 31 of each control unit is supplied to the second circuit 2, and a reset signal RESET is supplied as necessary. Is completed.

By designing in this manner, a FIFO memory having an arbitrary number of bits L and an arbitrary number of words M can be designed by a hard macro module supplied as a cell library. The design can be performed by a simple arrangement work in which the cells are arranged vertically and horizontally and a simple wiring work between cells, so that the burden of the design work is greatly reduced.

[0036]

8 and 9 show circuit diagrams of specific circuits of a control unit which can be used in the present invention. The control unit 100 shown in FIG. 8 is a cell used for the n-th column (1 ≦ n ≦ M−1) of the FIFO memory having the storage capacity of M words, and the control unit 200 shown in FIG. Used in the M-th column (most significant word) of the FIFO memory having the storage capacity of The difference between the two is that the reset signal RE
This is only the operation when SET is given. That is,
The control unit 100 shown in FIG. 8 outputs a logical value “0” (bit indicating no flag) to the right terminals W (n) and R (n) when the reset signal RESET is supplied. The control unit 200 shown in FIG.
When T is given, a logical value “1” (bit indicating presence of a flag) is output to the right terminals W (M) and R (M).
In other words, when reset signal RESET is applied, control unit 100 shown in FIG. 8 generates neither write location flag W nor read location flag R, whereas control unit 200 shown in FIG. Then, both the writing location flag W and the reading location flag R are generated.
More specifically, for example, as shown in FIG. 3, when a FIFO memory having a storage capacity of 6 words (M = 6) is configured, the five control units 12a to 12e are configured as shown in FIG. The control unit 100 shown in FIG. 9 is used as the last control unit 12f.

Each of the circuits shown in FIGS. 8 and 9 is constituted by a combination of a logic gate and a sequential circuit. FIGS. 10 to 12 show three types of sequential circuits (each diagram (a)) used in these circuits and their truth tables (each diagram).
(b)). “X” in the truth table indicates an arbitrary logical value, and “Latch” indicates that the immediately preceding logical value is held.

The control units 100 and 200 include permission signal output units 110 and 210 and write location flag storage units 120 and 22.
0, full / empty signal generators 130 and 230, and read location flag storage units 140 and 240.
Here, the writing location flag storage units 120 and 220 are as shown in FIG.
Performs a function corresponding to the upper part of each of the control units 12a to 12f shown in FIG.
Performs a function corresponding to the lower part of each of the control units 12a to 12f shown in FIG.

That is, the write location flag storage unit 120,
The sequential circuit in 220 temporarily holds the logical value “0” or “1” and synchronizes with a first clock signal (write clock signal WCLK) provided from the first circuit side.
A process for transferring the held logical values from left to right in the figure is executed. For example, in the control unit 100 shown in FIG. 8, the logical value W (n-1) transferred from the previous stage is taken into the first-stage sequential circuit in synchronization with the falling edge of the write clock signal WCLK. Are taken into the second sequential circuit in synchronization with the following rising edge, and transferred to the subsequent stage as a logical value W (n) in synchronization with the next falling edge. Note that the logical value W (M) output from the control unit 200 shown in FIG. 9 provided in the Mth column is sent to the control unit 100 shown in FIG.
(N-1).

Similarly, read location flag storage sections 140 and 2
The sequential circuit in 40 temporarily holds the logic value “0” or “1”, and holds the held logic in synchronization with a second clock signal (read clock signal RCLK) given from the second circuit side. Performs processing to transfer values from left to right in the figure. For example, in the control unit 100 shown in FIG. 8, the logical value R (n-1) transferred from the previous stage is taken into the first-stage sequential circuit in synchronization with the falling edge of the read clock signal RCLK. The data is taken into the second sequential circuit in synchronization with the following rising edge, and is transferred to the subsequent stage as a logical value R (n) in synchronization with the next falling edge. The logical value R (M) output from the control unit 200 shown in FIG. 9 provided in the Mth column is sent to the control unit 100 shown in FIG. n
-1).

As described above, when the reset signal RESET is supplied to these circuits, the control unit 10 shown in FIG.
0 performs the process of generating the bit “0” as the logical values W (n) and R (n) and transferring the bit to the subsequent stage. The control unit 200 shown in FIG. A process of generating a bit “1” as (M) and transferring it to the subsequent stage is performed. Therefore, in the initial setting state immediately after giving the reset signal,
In the control unit 100 in the first column, the write location flag W and the read location flag R are held, that is, the logical value “1” is held in the sequential circuit.
The logic value “0” is held in each sequential circuit in the control unit 100 in the (M−1) th column and the control unit 200 in the Mth column. Thereafter, the write location flag storage units 120 and 220
The logical value “1” (write location flag W) held in
The data is transferred to the subsequent stage every clock cycle of write clock signal WCLK, and read location flag storage units 140, 2
Logical value “1” held in 40 (read location flag R)
Is transferred to the subsequent stage every clock cycle of the read clock signal RCLK.

The permission signal output units 110 and 210 store the write location flag W, that is, the sequential circuit in the write location flag storage units 120 and 220 outputs the logical value “1”.
Hold, the write enable signals WW (n), WW
(M) is output and the read location flag R is stored, that is, when the sequential circuits in the read location flag storage units 140 and 240 hold the logical value “1”, the read enable signal RR is output. (N) and a function of outputting RR (M). The write enable signals WW (n) and WW (M) and the read enable signals RR (n) and RR (M) are supplied to the memory elements in the storage unit of the corresponding column, and write or write to the column (word) is performed. The reading process will be executed. The buffers provided in the permission signal output units 110 and 210 function as drive buffers for the memory elements, and the driving capabilities of these buffers need to be determined according to the number of bits L of each storage unit.

The full / empty signal generators 130 and 230
When the read location flag R is stored, the signal FULL is generated when the write location flag W is transferred from the preceding stage. Conversely, when the write location flag W is stored, the signal FULL is generated. When receiving the read location flag R, the signal EM
A process for generating PTY is performed. In other words, the sequential circuit in the read location flag storage units 140 and 240 has the logical value “1”.
Is stored, the write location flag storage unit 1
When the logical value "1" is transferred from the preceding stage to the data storage units 20, 220, a signal FULL is generated, and the sequential circuit in the write location flag storage units 120, 220 holds the logical value "1". At the time of reading, the reading location flag storage units 140 and 24
It has a function of generating a signal EMPTY when a logical value “1” is transferred to 0 from the preceding stage. Note that the signal EMPTY is also generated immediately after giving the reset signal RESET.

FIG. 13 shows the control units 100 and 200 described above.
5 is a timing chart showing the operation of a FIFO memory configured using the above. At time t1, reset signal RE
Immediately after the SET is given, no data is written in any of the storage units, and the signal EMPTY becomes logic “1” and is activated. The periods T1 and T2 correspond to the data Data.
(W) shows the write operation timing, at time t2 corresponding to the rising edge of the write clock signal WCLK.
Writing is performed in synchronization with. Before time t2, the setup time (setup ti
A period T1 is secured as me), and a period T2 is secured after time t2 as a hold time. In the illustrated example, the FIFO memory is in a full state by this writing, and the signal FULL becomes logic “1” and is activated. In the following period T3, data Data (R) is read from the full-filled FIFO memory, so that at time t3, the signal FULL is output.
Becomes logic "0" and is inactivated. Time t
4, as a result of reading out all data, the signal EMP
TY is logic "1" and is activated. At the subsequent time t5, the next data Data (W) is written, and the signal EMPTY becomes logic "0" and is inactivated.

FIG. 14 shows that the control module is arranged by arranging (M-1) cells corresponding to the control unit 100 shown in FIG. 8 and arranging one cell corresponding to the control unit 200 shown in FIG. It is a block diagram showing the example which constituted. The width of the cells of the control unit 100 and the control unit 200 is
If the cell width of each storage element is equal to that of each storage element, the cells of each storage element and the cells of each control unit can be arranged in the horizontal direction at the same pitch. The input terminal positions of the write enable signal WW and the read enable signal RR in each storage element, and the write enable signal WW and the read enable signal RR in each control unit
If the positions of the output terminals are the same, the wiring is greatly simplified (the cells need only be arranged adjacently). Also, a terminal W (n) for transferring the writing location flag W and a terminal R for transferring the reading location flag R
Since the vertical position of (n) is common to the individual control units, the interconnection of these terminals is also greatly simplified (again,
It is only necessary to place the cells adjacently). Each clock signal WC
The same applies to the wiring for LK, RCLK, the signal FULL, and the signal EMPTY. However, the terminal W (M) of the control unit in the Mth column is connected to the terminal W (0) of the control unit in the first column, and the terminal R (M) of the control unit in the Mth column is connected to the terminal R (M). Wiring connected to the terminal R (0) of the control unit in the first column is separately required.

[0046]

As described above, according to the present invention, a FIFO module is constituted by a memory module including a plurality of M storage units and a control module including a plurality of M control units. Can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of data transfer using a general FIFO memory.

FIG. 2 is a block diagram showing a general configuration of a conventional FIFO memory.

FIG. 3 is a block diagram showing a basic configuration of a FIFO memory according to the present invention.

FIG. 4 is a diagram showing a first process for designing the FIFO memory shown in FIG. 3;

FIG. 5 is a diagram showing a second process for designing the FIFO memory shown in FIG. 3;

FIG. 6 is a diagram showing a third process for designing the FIFO memory shown in FIG. 3;

FIG. 7 is a diagram showing a fourth process of designing the FIFO memory shown in FIG. 3;

FIG. 8 is a circuit diagram showing an example of a circuit used as a first control unit in a FIFO memory according to the present invention.

FIG. 9 is a circuit diagram showing an example of a circuit used as a second control unit in the FIFO memory according to the present invention.

FIG. 10 is a diagram showing a first sequential circuit used in the circuit diagrams shown in FIGS. 8 and 9 and a truth table thereof.

FIG. 11 is a diagram showing a second sequential circuit used in the circuit diagrams shown in FIGS. 8 and 9, and a truth table thereof.

FIG. 12 is a diagram showing a third sequential circuit used in the circuit diagrams shown in FIGS. 8 and 9, and a truth table thereof.

FIG. 13 is a timing chart showing the operation of the FIFO memory configured using the circuits shown in FIGS. 8 and 9;

FIG. 14 is a block diagram illustrating a control module configured by arranging the control units illustrated in FIGS. 8 and 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st circuit 2 ... 2nd circuit 3 ... FIFO memory 4 ... Dual-port SRAM 5 ... Control part 10 ... FIFO memory 11 ... Memory module 11a-11f ... Storage part 12 ... Control module 12a-12f ... Control part 20 Unit cell unit 21 1-bit storage element cell 22 Write data buffer cell 23 Read data buffer cell 31 Control unit cell 100 First control unit 110 Enable signal output unit 120 Write Empty location flag storage unit 130 Full / vacant signal generation unit 140 Read location flag storage unit 200 Second control unit 210 Permit signal output unit 220 Write location flag storage unit 230 Full / vacant signal generation unit 240 Read Location flag storage units A to F: Position / storage unit for storing data EMPTY: Signal indicating empty status FULL: Indicates full status Signal Pread: Read pointer Pwrite: Write pointer RCLK: Read clock signal RESET: Reset signal R (n-1), R (n), R (M-1), R (M): Read location flag RR to be transferred (N), RR (M) ... read permission signal WCLK ... write clock signal W (n-1), W (n), W (M-1), W (M) ... write location flag WW to be transferred (N), WW (M) ... write enable signal X1 to X3 ... data to be transferred X (1), X (L) ... each bit of data to be transferred

Claims (5)

[Claims] 1. A function of transferring digital data between a first circuit operating on a first clock and a second circuit operating on a second clock when transferring digital data to the two circuits. A memory module having a plurality of M storage units each having a capacity corresponding to the number of bits of data to be transferred, and M control units provided corresponding to the storage units. A control module comprising: a control module having a function of storing a write location flag W and a read location flag R; and a function of transferring these flags to a control section at a subsequent stage. When a signal is applied, the write location flag W and the read location flag R are stored in a predetermined control unit at the first stage, and the data is transmitted from the first circuit in synchronization with the first clock. Comes out Then, the memory module performs a process of writing the output data to the storage unit corresponding to the control unit in which the writing location flag W is stored at that time, and stores the writing location flag W. The control unit performs a process of transferring the write location flag W to a subsequent control unit. If a request for data input synchronized with the second clock is issued from the second circuit, the memory module will The control unit that reads data from the storage unit corresponding to the control unit in which the read location flag R is stored and provides the read data to the second circuit,
A process of transferring the read location flag R to a subsequent control unit is performed. When each control unit stores the read location flag R,
When the write location flag W is received from the previous stage, the first
A signal FULL indicating that the FIFO memory is in a full state is transmitted to the circuit of FIG. A function of transmitting to the second circuit a signal EMPTY indicating that the FIFO memory is empty. 2. The FIFO memory according to claim 1, wherein a storage unit having a capacity of L bits is formed by arranging L one-bit storage elements in a vertical direction, and forming the storage unit in a horizontal direction. A memory module having a capacity of L bits and M words is arranged by arranging M units in a matrix, and a control module is constituted by arranging M units in the horizontal direction at the same pitch as the storage unit. A FIFO memory, wherein a storage unit and each control unit corresponding to the storage unit are arranged adjacent to each other. 3. The FIFO memory according to claim 2, wherein when the reset signal is applied, the first control unit generates neither the write location flag W nor the read location flag R; And a second control unit for generating both the write location flag W and the read location flag R, the (M-1) first control units are arranged, and the second By arranging one control unit,
A FIFO memory comprising a control module. 4. The FIFO memory according to claim 2, wherein each of the control units stores a write location flag W.
Write enable signal WW for the storage element in the corresponding storage unit
And outputting a read enable signal RR to a storage element in a corresponding storage unit when the read location flag R is stored. 5. The method of manufacturing a FIFO memory according to claim 2, wherein each storage element and each control unit are prepared in the form of a cell registered in a library as a hard macro module, and a cell for the storage element is provided. Are arranged in the vertical direction and in the horizontal direction to form a memory module having a capacity of L bits and M words, and the cells for the control unit are arranged at the same pitch as the cells for the storage elements. Characterized in that a control module is configured by arranging M pieces in a horizontal direction in the FIF.
Manufacturing method of O memory.