JPH04360425A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain serial/parallel conversion and parallel/serial conversion in the unit of optional bits by storing an input data in the unit of optional bits and writing/reading the data in a set clock timing. CONSTITUTION:An input data DIN is fetched sequentially to a shift register 5 via a buffer 4 in the unit of N bits in the timing signal from an input decoder 1 driven by an input clock. Then an input enable signal is fed to the input decoder 1 and the storage data in the register 5 is fetched in a latch 6 in the unit of N bits and written one by one bit each to N sets of memory planes of a memory cell array 7. The read is controlled by a parallel output clock fed to an output decoder 2 and a parallel output enable signal from a control circuit 3 and N bits data are once read from the memory cell array 7 and outputted to an output buffer 8. Thus, the data is processed in the unit of optional parallel bits and the processing speed is improved and the peripheral circuit is simplified.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to a semiconductor memory device capable of converting serial input data to arbitrary bits of parallel data, and conversely, capable of converting arbitrary bits of parallel input data to serial data.

0002

2. Description of the Related Art Conventional semiconductor memory devices of this type generally have parallel input/parallel output or serial input/serial output of the same number of bits. This is because in conventional devices, parallel data is input divided into constituent bits of the storage device, stored internally, and arbitrarily output in bits. For this reason, the storage devices on the system bus, such as the CPU, could be of parallel input/output format.

0003

However, in data communications, data is often handled as serial data rather than as parallel data. Here, serial data is data in arbitrary bit units that is sequentially sent out in time series using a reference clock to form a series of data.

[0004] When serial data configured in this manner is input to a conventional storage device, some kind of serial/parallel conversion is required. In this case, if the serial data is stored as is in the storage device and output, the processing speed will be slow, so serial/parallel conversion will be required again after the data is output from the storage device. Therefore, in order to use conventional storage devices, an external interface circuit is always required.

The present invention has been made to solve the above-mentioned problems, and is capable of converting serial input data into parallel output data with an arbitrary number of bits, or converting parallel input data with an arbitrary number of bits into serial output data. The purpose is to provide a convertible semiconductor memory device.

[0006]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a first buffer for storing N-bit serial data, N memory planes, and a second buffer for storing N-bit parallel data. The N-bit serial data taken into the first buffer is written to each of the N memory planes by a first clock timing, and the N-bit serial data taken into the first buffer is written to each of the N memory planes by a second clock timing. The N-bit data written in each of the buffers is read out to the second buffer.

Further, the semiconductor memory device of the present invention includes a first buffer for storing N-bit serial data, N memory planes, and a second buffer for storing N-bit parallel data. , writes the N-bit parallel data taken into the second buffer into each of the N memory cell arrays at a first clock timing, and writes it to each of the N memory planes at a second clock timing. The stored N-bit data is read out to the first buffer.

[0008]

According to the present invention, input data is stored in each memory cell array in arbitrary bit units. The clock timings for writing and reading can be set asynchronously. Therefore, serial/parallel conversion and parallel/serial conversion can be realized in arbitrary bit units.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic structure of a semiconductor memory device according to an embodiment of the present invention. Further, FIG. 2 shows a timing chart of various signals applied.

In the embodiment shown in FIG. 1, serial data input in units of N bits is stored in N memory planes 7-1 to
One bit is stored in each memory cell array 7 consisting of 7-N, and when output, it is read out as N-bit parallel data at a time.

Input data DIN is sequentially written into an N-bit shift register 5 via an input buffer 4. The write timing of the input buffer 4 is controlled by an input decoder 1 driven by a serial input clock. The accumulated data of the N-bit shift register 5 is
One bit is written to each of the N memory planes of the memory cell array 7 via the input latch 6.

For reading, an output buffer 1 is provided, and an output decoder 2 is driven by a parallel output clock from a corresponding address in the memory cell array 7.
Reading is performed under the control of a control signal from.

The timing of the input decoder 1 and the output decoder 2 is controlled by a control circuit 3, to which a serial input enable signal and a parallel output enable signal are applied.

Next, the detailed operation of the apparatus shown in FIG. 1 will be explained with reference to the timing chart shown in FIG.

First, input data DIN is sequentially fetched into the N-bit shift register 5 via the input buffer 4 in units of N bits by a timing signal from the input decoder 1 driven by a serial input clock. Next, by applying the serial input enable signal to the input decoder 1 via the control circuit 3, the input data stored in the N-bit shift register 5 is taken into the input latch 6 in units of N bits, and simultaneously One bit is written to each of the N memory planes of the memory cell array 7. Such a write operation to the memory cell array 7 is sequentially repeated with the serial input data divided into N bits.

On the other hand, the read operation is controlled by a parallel output clock applied to the output decoder 2 and a parallel output enable signal inputted to the control circuit 3.
A total of N bits of data are read bit by bit at a time to the output buffer 8 having an N-bit configuration, and outputted as N-bit parallel data DOUT1 to DOUTN.

The serial input clock and parallel output clock for writing and reading data are as follows:
Each can be configured to operate asynchronously.

In the embodiment shown in FIGS. 1 and 2, serial data input is converted to parallel data input, but by reversing the operation timing of input and output, parallel data input can be converted to serial data input. It is also possible to convert it into an input.

[0020]

As described above in detail based on the embodiments, the present invention performs serial/parallel conversion or parallel/serial conversion inside the storage device, so an external interface circuit is not required. Processing is possible with any parallel bits on the internal system bus. Therefore, it is possible to realize a semiconductor memory device that can improve the processing speed within the system and simplify external peripheral circuits.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the timing of various signals applied to the device in FIG. 1;

[Explanation of symbols]

1 Input decoder 2 Output decoder 3 Control circuit 4 Input buffer 5 N-bit shift register 6 Input latch 7 Memory cell array 8 Output buffer

Claims (2)

[Claims] Claim 1: A first buffer that stores N bits of serial data (N is a positive integer), N memory planes, and a second buffer that stores N bits of parallel data; At a first clock timing, the N-bit serial data taken into the first buffer is written to each of the N memory planes, and at a second clock timing, it is written to each of the N memory planes. A semiconductor memory device characterized in that the N-bit data stored in the second buffer is read out to the second buffer. 2. A first buffer that stores N bits of serial data (N is a positive integer), N memory planes, and a second buffer that stores N bits of parallel data; The N-bit parallel data taken into the second buffer is written to each of the N memory planes by a first clock timing, and written to each of the N memory planes by a second clock timing. A semiconductor memory device characterized in that N-bit data stored in the memory is read into the first buffer.