JP2001167569A - Fifo memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means to settle the problem that the reading circuit of a conventional FIFO memory device cannot designate the addresses other than #0 address on a line that is shifted from a memory array to a read register nor read out the same line in plural times and four of eight lines become the blacking sections to deteriorate the picture quality when the image data are enlarged into a large 8-line image from a comparatively small 4-line image, for example, in an image processing mode. SOLUTION: The read circuits (1, 2, 3) of a serial access memory of a FIFO which carries out asynchronous read/write operations are provided with a means 5 which performs the read resetting operations in each prescribed timing to read recorders 3 (33, 34...3n) which select read registers 2 (201, 202...20n) and means (#T, L/STR, 28) which inhibit temporarily the read transfer operations to the read registers 2 from a memory array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO type serial access memory widely used as a storage device, particularly as an image processing memory, and more particularly to a FIFO memory device provided with a means for reading the same data a plurality of times.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional technique in which a FIFO [First-in First-ou] for asynchronously performing read and write operations is used.
t] Serial Access Memory
3 is a schematic circuit configuration diagram of FIG. In all the drawings, the same reference numerals denote the same or corresponding members or functional blocks. In FIG. 3, when a data input 11 / DIN is input first, a row decoder [Row-Decoder] 10 and a write clock
[Write-Clock] 14, Write reset [Write-Reset] 15, the output of the write decoder [Write-Decoder] 13 passes through the serial write register [Serial-Write-Register] 12 of the next stage, The data input 11 is written into the memory array [Memory-Array] 1 as appropriate. Then, the data written in the memory array 1 is transferred to the read clock [Read-
Clock] 4 and read reset [Read-Reset] 5, the output of the read decoder [Read-Dec-oder] 3 is transmitted through the serial read register [Serial-Read-Register] 2 at the next stage.
The data transferred from the memory array 1 to the register 2 is sequentially output as a data output 9 through a data output buffer 8 as a data output 6 or 7. In other words, a write register 12 and a decoder 13 dedicated to writing and a read register 2 and decoder 3 dedicated to reading are provided for a memory area common to read and write, and data is transferred to the memory area via these registers and decoder. Is accessed.

FIG. 4 is a block diagram showing a circuit configuration of a memory device which performs a FIFO operation as an example of the prior art [conventional example], particularly a configuration of a read circuit. First, each first
NMOS [nChannel-Metal Oxide Se
In Fig. 4, FET ・ Field-Effect Trans
is turned on) 211, 212, 213, 214, 21n are turned on, and the data from the memory array 1 is used to form a static RAM.
1,202, ..., 20n. Next, when there is a read reset signal 5 · STR, a surge absorbing circuit [diode
52, 54], the NOR 56, the inverter 57, the NOR 31 and the inverter 32, and the pointer (read reset signal 5.STR) from the shift register [Shift-Register] 33 according to the serial read clock [Serial ReadClock].
Each of the shift registers 34,..., 3n is sequentially shifted, and each shift corresponds to the nMO constituting the second gate.
S221, 222,..., 22n are turned on, and the static memories 201 and 20 are turned on.
The data stored in the 2,..., 20n [SRAM] is read out as the data output Dout or the data output / Dout having the opposite phase to the data output Dout, and after a short delay after the output from the last-stage shift register 3n. , The first group of gates is turned on again, and the previous operation is repeated. Therefore, the data from the same memory array 1 stored in the static memories 201, 202,..., 20n [SRAM] cannot be read again. That is, in the conventional example, in the read operation in the read cycle, first, upon receiving the read reset signal 5 · STR, the internal address is initialized to address 0, and then the data is sequentially read in synchronization with the serial read clock 4 · RCK. The output Dout (or / Dout) is output from the register 2. Note that the write operation is not directly related to the present invention, and is therefore omitted.

Further, as a reference example, JP-A-6-2750
No. 69, title of invention Serial memory can be seen. The purpose of this reference example is to provide a serial memory capable of performing FIFO and LIFO operations. Its configuration is to internally convert serially input data into parallel data and write the data into a memory array in units of a plurality of bits. In a serial memory that internally converts data read in units of a plurality of bits into serial data and outputs the data, the order of parallel conversion for serial input data and the order of serial conversion for parallel data read from a memory array can be selectively reversed. The first means (serial / parallel conversion circuit, decoder, write counter) and the second means (parallel / serial conversion circuit, decoder, read counter) are employed, and the access addresses to the memory array are read and written in ascending order. Can be reversed in descending order It has adopted the re-controller. The gist of this reference example also directly falls outside the scope of the present invention.

[0005]

As described above, in the FIFO having the conventional configuration, the address is 0 from the outside.
There is a problem that it is not possible to specify an address other than the address, and it is not possible to read the same line a plurality of times, which has been a major bottleneck in image processing. For example, in a case where image data is enlarged to a large screen of eight lines rather than a relatively small screen of four lines, four lines out of eight lines become a blacking interval, and a problem that image quality often deteriorates often occurs. It was a situation. Therefore, in the present invention, an externally controllable reset terminal [means for introducing the line reset signal L / STR] is added to the address pointer of the read register, the simplest circuit is added, and the same data is output during this output operation. Elucidating the phenomenon that the image will not be coarse if written twice, the FIF adapted to this
It is an object to provide an O memory device.

[0006]

According to a first aspect of the present invention, there is provided a read circuit for selecting a read register in a read circuit of a FIFO serial access memory performing asynchronous read and write operations. A FIFO memory device comprising: means for resetting a read of a decoder at a predetermined timing; and means for temporarily inhibiting read transfer from a memory array to a register. As described above, according to the first aspect of the present invention, the read decoder is reset every time a signal for temporarily inhibiting the read transfer from the memory array to the register is output. It has a special effect that it can be performed on the same line.

According to a second aspect of the present invention, in the FIFO memory device according to the first aspect, the means for resetting the read decoder at a predetermined timing is a latch circuit with a read reset. 2. The FIFO memory device according to claim 1, wherein: Thus, according to the invention of claim 2 of the present invention, it is possible to obtain an optimum circuit configuration for exhibiting the effect of claim 1, and a remarkable feature that operation reliability is improved is recognized.

According to a third aspect of the present invention, in the FIFO memory device according to the second aspect, a circuit for obtaining a logical sum of a read reset signal for performing a read reset and the line reset signal is provided between the memory array and the read decoder. A first gate group for controlling the input of data from the memory array to the static memory group disposed in the unit, and outputting the data stored in the static memory group to the outside from the static memory group Means for storing data from the memory array in the static memory group simultaneously by opening the first gate group for a certain period of time by the logical sum output, and calculating by a serial clock. Means for sequentially opening the second gate group one by one for a predetermined time by a read decoder, and outputting data output to the outside. At the same time, after the read of the static memory at the last address of the read decoder is performed, the line reset signal is given to prohibit the transfer of data read to the next line, and the first line of the previously read line is continued. 3. The FIFO memory device according to claim 2, further comprising means for re-reading data from the memory. Thus, according to the invention of claim 3 of the present invention, the effectiveness that the same line can be reread reliably and at high speed can be exhibited.

According to a fourth aspect of the present invention, in the FIFO memory device according to the third aspect, an output of the counting means for arbitrarily twice or more arbitrarily inhibiting transfer to data read to the next line for at least two times. 4. The FIFO memory device according to claim 3, further comprising means for obtaining a logical product of the logical sum of the line reset signal and the line reset signal, and supplying an output signal thereof to an input stage of the circuit for obtaining the logical sum. Thus, according to the invention of claim 4 of the present invention, since the same line can be read a plurality of times consecutively, it can be said that there is a place where it is possible to obtain fine image data and benefit the world.

[0010]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an electronic circuit having a read function of a FIFO memory according to an embodiment of the present invention. By the way, in the circuit configuration of the present invention shown in FIG. 1, when compared with FIG. 4 of the conventional example, the portion surrounded by a gray frame is a circuit created by the present invention. That is, (1) a signal input circuit including a surge absorbing circuit which is provided with a line reset signal L / STR reaching an input stage to the NOR 56, denoted by 500, and (2) a signal input circuit, denoted by 200,
From the output stage of the inverter 57 to the NAND 22 via the inverter 28
And (3) a signal feedback circuit from the output stage of the inverter 21 to the input stage of the NOR 31 indicated by reference numeral 300. (4) Although not shown, a time measuring means [for example, a timer, a computer, etc.] is provided further upstream of the signal input circuit 500, and the read reset signal L /
Both signals are introduced into the input stage of a circuit for adjusting the STR transmission time point (the time point t9 of the first RCK from the time point t8 in FIG. 2 to be described later), for example, a circuit that takes the logical product of the two signals, and the output stage thereof is connected. Means for providing to the input stage of the signal input circuit 500 are provided.

FIG. 2 is a timing chart showing the operation and function of each signal pulse in the electronic circuit of the present invention shown in FIG. The vertical axis shows the voltage of the pulse signal, and the horizontal axis shows the transition of time. Also, 0 line, 1 line described at the top of FIG.
Lines, two lines,... Refer to horizontal lines selected by the row decoder 10 in FIG. 3 and horizontal lines of stored data strings. (A) to (o) show the names and functions of the respective pulse signals. Therefore, the read operation of the present invention will be described with reference to FIGS. First, it is assumed that predetermined data is transferred from the memory array 1 to the serial read register 2 and stored therein. Read reset signal 5 ・ S in synchronization with serial read clock 4 ・ RCK
If TR is set at "H" level [High Level], the internal address is initialized to address "0", and first, # 0 of line 0 is synchronized with the serial read clock 4 • RCK.
The [0th] pointer [shift register 33] is selected, that is, the gates of the nMOSs 221 and 222 are turned on (time t2).

Hereinafter, addresses 1 (time t3), addresses 2,
.., N (time t4) [Shift register 34,... 3n] are serially accessed. An "H" pulse is output at #T [Tth] within the time from the time (t4) when the selection of the n-th address is completed (t4) to the time (t6) (time t5). At this time,
are turned on, and transfer the read data of the first line from the memory array 1. Thereafter, the data of the first line is read out serially with addresses 0, 1,..., N (time t6 to t8). After the end of the address n (time t8), the line reset signal 50 · L / STR
Is synchronized with the serial read clock 4 · RCK.
When the "H" level is given (time point t9), # 0 to "n" in FIG.
The pointers nMOS 211, nMOS 212,... Are initialized, and the data at this time retains data of one line. If a read operation is performed in such a state (time t10 to t12), the same line, for example, one line can be read twice. And (4)
If the means described in (1) is applied, it is possible to read data of the same line a plurality of times.

[0013]

As described above in detail, according to the present invention, in addition to the conventional FIFO operation, the data of the same line can be realized by the simplest method, and the image can be enlarged or enlarged. Image change can be easily realized. That is, according to the first aspect of the present invention, the read decoder is reset every time a signal for temporarily inhibiting the read transfer from the memory array to the register is output. It has a special effect that it can be performed. According to the second aspect of the present invention, it is possible to obtain an optimal circuit configuration for exhibiting the high cost of the first aspect, and a remarkable effect of improving the operation reliability is recognized. According to the present invention, the same line can be re-read reliably and at high speed, and the same line can be read a plurality of times in succession. It can be said that there is a place where it is possible to acquire various image data and benefit the world.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an electronic circuit that performs a read function of a FIFO memory according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation and function of each signal pulse in the electronic circuit of the present invention shown in FIG.

FIG. 3 is a schematic circuit configuration diagram of a FIFO serial access memory;

FIG. 4 is a block diagram showing a configuration of an electronic circuit in a conventional FIFO.

[Explanation of symbols]

1 Memory Array 2 Serial Register 3 Read Decoder 4 Read Lock [RCK] 5 Read Reset [STK] 6 Data Output [Dout] 7 Negative Phase Data Output [/ Dout] 8 Data Output Buffer 9 Output Data [DOUT] 10 Row Decoder 11 Data input [DIN] 12 Serial write register 13 Write decoder 14 Write clock [WCK] 15 Write reset [STW] 21,23,24,25,26,27,28,32,57 Inverter (phase inverter) 22 NAND ( NOR circuit (Negative AND circuit) 31,56 NOR (Negative OR circuit) 33,34,3n Shift register (Latch circuit with reset) 201,202,20n Static memory (SRAM) 211,212,213,214,21n nMOS (First gate) 221,222,223,224,22n nMOS (second gate) 51, 52, 53, 54 Diode 55 DC constant voltage # 0, # 1, # n0-n address #T Data transfer signal t1, t2, t3, t4, t5, t6, t7, t8, t9 , t10, t11, t12, t13, t14

Claims (4)

[Claims] 1. An FIF for performing asynchronous read and write operations
The read circuit of the O serial access memory includes means for resetting a read decoder for selecting a read register at a predetermined timing, and means for temporarily inhibiting read transfer from the memory array to the register. FIFO memory device. 2. The FIFO memory device according to claim 1, wherein the means for resetting the read decoder at a predetermined timing is a latch circuit with a read reset. FIFO memory device. 3. The FIFO memory device according to claim 2, wherein a circuit for performing an OR operation of a read reset signal for performing a read reset and the line reset signal, and a static memory disposed at an intermediate portion between the memory array and the read decoder. A first group of gates for controlling input of data from the memory array to a group, and a second group of gates for outputting data stored in the static memory group to the outside from the static memory group. Means for opening the first gate group by the logical sum output for a predetermined time and simultaneously storing data from the memory array in the static memory group, and the second decoder by means of a read decoder operated by a serial clock. Means for sequentially opening the gate groups one by one for a fixed time and outputting data output to the outside; After the static memory of the last address of the decoder is read, the line reset signal is given to prohibit the transfer of the data to the next line to be read, and the read from the beginning of the previous read line is continued again. 3. The FIFO memory device according to claim 2, further comprising means for performing. 4. The FIFO memory device according to claim 3, wherein an output of a counting means for arbitrarily arbitrarily inhibiting transfer of data reading to the next line to data reading two or more times and the line reset signal are provided. 4. The FIFO memory device according to claim 3, further comprising means for taking a logical product and providing an output signal thereof to an input stage of the circuit for obtaining the logical sum.