JPH0230220A - Serial/parallel conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to attain low power consumption by reading out a digital data of a serial data storage means and storing dividedly in plural latch means in a parallel conversion means. CONSTITUTION:A serial digital data is given to a serial data storage means 240 and written sequentially in an address location outputted from an address generating means 250. A serial data stored in the serial data storage means 240 is read out and latched in plural latch means in the parallel conversion means 260 in the timing coincident with a readout timing separately and the result is outputted as a parallel data.

Description

[Detailed Description of the Invention] [Summary] Regarding a serial/parallel conversion circuit that converts serial digital data into parallel digital data, an object of the present invention is to provide a serial/parallel conversion circuit with a smaller circuit scale and lower power consumption. a serial data storage means for sequentially writing and storing serial digital data; an address generation means for changing a data writing/reading address for the serial data storage means for one bit of the serial digital data; and a serial data storage means. and parallel conversion means for dividing and holding the serial digital data read from the means into a plurality of latch means.

[Industrial application field]

The present invention relates to a serial/parallel conversion circuit that converts serial digital data into parallel digital data.

For example, in a digital data communication device, a serial/parallel conversion circuit (hereinafter referred to as an S/P conversion circuit) or parallel A /serial conversion circuit (hereinafter referred to as a P/S conversion circuit) is always used in an interface portion of a digital data communication device.

There is always a strong demand for such communication devices to be small in scale and low in power consumption.

[Conventional technology]

FIG. 3 is a block diagram illustrating a conventional example, FIG. 4 is a diagram illustrating a configuration example of a shift register circuit in the conventional example, and FIG. 5 is a diagram illustrating an example of use of a serial/parallel conversion circuit.

FIG. 5 shows an example in which the S/P conversion circuit 22 and the P/S conversion circuit 12 are used in the receiving section 2 and transmitting section 1 of a digital data communication device.

In addition to the S/P conversion circuit 22, the reception unit 2 of the digital data communication device includes an interface circuit (hereinafter referred to as INF) 21 that interfaces with the transmission path (a), and the S/P conversion circuit 2.
2, which serves as an interface for outputting the data converted into parallel data.

On the other hand, in addition to the P/S conversion circuit 12, the transmitting unit 1 includes an INF II that serves as an interface for inputting parallel data, and an INF 13 that serves as an interface for sending digital data converted into serial data to a transmission line (al). ing.

FIG. 3 shows the configuration of the above-mentioned S/P conversion circuit 22,
Its configuration is as shown in FIG.
21(n) connected in series to form a shift register, and each register 22H1) to 22H in the shift register circuit 221.
21 A launch circuit 22 having latches 222 (1) to 222(n) that respectively hold the outputs of (n) in correspondence with each other.
2, a shift register circuit 221 and a latch circuit 222
A timing generator (hereinafter referred to as TIMING G) that generates the shift clock ■ and rough clock ■ used in
(referred to as IEN) 223.

Each register 221 (1) in the shift register circuit 221 -
221(n) constitutes a shift register, and the capacity of one register 22Hi) is 8 bits.

That is, 8-bit serial digital data is
21, it is converted into 8-bit parallel data and output at the timing of the shift clock (2), and the 8-bit parallel data is held in the corresponding latch 222(i) at the timing of the latch clock (2).

By repeating this process for each frame of digital data, it becomes possible to convert all the serial data input via the transmission line (al) into parallel data.

Therefore, the number of registers 221 (1) to 221 (n) and latches 222 (1) to 222 (n) are installed according to the number of bits to be transmitted.

[Problem to be solved by the invention]

Until now, it has been common to use a shift register circuit 221 consisting of a plurality of registers as the S/P conversion circuit 22, as in the conventional example described above.

However, in this case, as the number of transmission points increases, the number of registers increases accordingly, resulting in a corresponding increase in circuit scale and power consumption, which is a problem.

An object of the present invention is to provide a serial/parallel conversion circuit with a reduced circuit scale and low power consumption.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 240 is a serial data storage means for sequentially writing and storing serial digital data, and 250 is a serial data storage means for serially writing/reading addresses for the serial data storage means 240. 260 is an address generation means for changing one bit of digital data, and 260 is a parallel conversion means for dividing and holding the serial digital data read from the serial data storage means 240 into a plurality of latch means. This is a means to solve this problem.

[For production]

When serial digital data is manually input to the serial data storage means 240, it is sequentially written to address positions output from the address generation means 250.

When reading the serial digital data stored in the serial data storage means 240, the parallel conversion means 26
0 is divided into a plurality of latch means and held, and by outputting it, it is converted into parallel digital data with a small increase in circuit scale up to serial digital data with a number of bits corresponding to the capacity of the serial data storage means 240. It becomes possible to do so.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses a memory (RAM) that can write/read serial digital data as the serial data storage means 240 explained in FIG.
) 240 a.

A memory (RAM) 24 serves as address generation means 250.
An address counter 250a that generates a write/read address of 0a and outputs a write enable signal (hereinafter referred to as WE) for the memory (RAM) 240a, and an address counter 25 as a parallel conversion means 260.
A decoder 261 that converts the address output from 0a into parallel data, and a plurality of latch circuits 262 that latch serial digital data read from the memory (RAM) 240a at the timing of the output of the decoder 261 and convert it into parallel data. This is an example configured with a parallel converter 260a consisting of (1) to 262 (n).

It is assumed that the S/P conversion circuit 22a of this embodiment is also installed in the receiving section 2 of the digital data communication device shown in FIG. 5, as in FIG.
Serial digital data is transmitted through the

This serial digital data is input to the memory (RAM) 240a via the NF21, and is sent to the memory (RAM) 240a.
M) 240a sequentially writes this serial digital data to the address position from the address counter 250a.

A gate circuit 27 is provided between the NF 21 and the memory (RAM) 240a, and this gate circuit 27 has three
It consists of a state buffer 271 and a driver 272.

The 3-state buffer 271 is the address counter 250a.
The gate is opened by a write enable signal output from the memory (RAM) 240a to the memory (RAM) 240a, and serial digital data is sent to the input/output terminal of the memory (RAM) 240a.

The write enable signal is turned off at the timing when serial digital data writing to the (RAM) 240a is completed, and then the address counter 250a is turned off.
With the address output from a as the read address,
The data written to the memory (RAM) 240a is read out through the latch circuit 262(1) through the driver 272.
262 (n).

On the other hand, the read address is converted by the decoder 261, and the latch circuits 262(1) to 262(n) output the launch signal in order, and the read data input via the driver 272 at that timing corresponds to the launch signal. The data is sequentially latched and held in the latch circuits 262(1) to 262(n).

Then, the data held in the latch circuits 262 (1) to 262 (n) is simultaneously converted into parallel data by lNF2.
3 to OUT#1 to OUT#n.

The method of converting serial data to parallel data in this way is P, which converts parallel data to serial data.
The present invention can also be applied to the /S conversion circuit 11.

That is, it is possible to simultaneously read data stored in multiple areas of the memory (RAM) 240a, hold it in a corresponding latch circuit, and convert it into serial data by sequentially accessing the latch circuits. Become.

In either case, memory (RAM) 240a
The circuit scale is influenced by the capacity of the memory (RAM) 240a, and even if the number of transmission bits increases, as long as it is within the capacity of the memory (RAM) 240a, it is possible to reduce the increase in the circuit scale.

〔Effect of the invention〕

According to the present invention as described above, there is no need to increase the circuit scale as the number of bits increases, and a smaller serial/
A parallel conversion circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a block diagram explaining a conventional example, and FIG. 4 is a shift register circuit in the conventional example. FIG. 5 is a diagram illustrating an example of the configuration of the serial/parallel conversion circuit. In the figure, 1 is a transmitter, 2 is a receiver, 11.13.
21.23 is INF, 12 is P/S conversion circuit, 22
, 220.220a is an S/P conversion circuit, 27 is a gate circuit, 221 is a shift register circuit, 221 (1) to 221 (n) are registers, 222,
262 (1) to 262 (n) are launch circuits, 222
(1) ~222(n) are latches, 223 is TIMIN
G GEN. 240 is a serial data storage means, 240a is a memory (RAM), 250 is an address generation means, 250a is an address counter, 260 is a parallel conversion means, 260a is a parallel conversion unit, and 261 is a decoder. A detailed block diagram of the present invention is shown in FIG. 1.
FIG. 4 is a diagram explaining an example of the configuration of the system register circuit in the conventional example.

Claims (1)

[Claims] A circuit for converting serial digital data into parallel data, the circuit comprising: serial data storage means (240) for sequentially writing and storing serial digital data; address generating means (250) for changing a read address for one bit of the serial digital data; and dividing the serial digital data read from the serial data storage means (240) into a plurality of latch means. A serial/parallel conversion circuit comprising: parallel conversion means (260) for holding data.