JPS5978395A - Circuit and method of driving matrix type liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention provides: (a) a drive circuit for an IJ type liquid crystal display device;
In particular, the present invention relates to a drive circuit and a drive method for an IJ type liquid crystal display device for image display.

FIG. 1 is a diagram showing the configuration of an IJ type liquid crystal display device, in which 101 is a liquid crystal panel, 102 is a scanning line, and 103 is a diagram showing the configuration of an IJ type liquid crystal display device.
1 is a data line, 104 is a scanning side drive circuit, and 105 is a data side drive circuit. Conventionally, the data side drive circuit 105 serially transfers an input data signal using an N-stage shift register, converts it into a liquid crystal drive signal after the transfer is completed, and drives N data lines in parallel. In order to serially transfer an M-bit image signal using such a conventional N-stage shift register, convert it into a liquid crystal drive signal, and drive the data line, (1) the shift register for data transfer must be
(II) Using N shift registers to transfer data at M times the transfer speed.

When the method (1) is used, the number of elements constituting the soft register increases, and the power consumption during data transfer also increases. Therefore, this drive circuit is integrated circuit (hereinafter referred to as
It is abbreviated as IC. ), the chip size and power consumption of the IC will increase, resulting in a product with high cost and high power consumption. Furthermore, when the method (11) is used, not only an expensive and complicated manufacturing process is required to speed up the IC, but also power consumption becomes large.

The present invention solves the above-mentioned drawbacks, and its purpose is to provide a data-side drive circuit and drive method for image display that can be manufactured at low cost and operate with low power consumption.

A feature of the present invention is to avoid serially transferring an M-bit image data signal in N stages, write it in the first N stage memory sequentially, and then write the contents of the first memory in synchronization with the trigger signal. The data side drive circuit is configured to capture data into the second N-stage memory, further generate a gradation signal according to the contents of the second memory, convert it to a liquid crystal drive signal, and drive the N data lines. be. Hereinafter, the present invention will be described in detail based on Examples.

In FIG. 2, numeral 200 is a data bus that supplies an M-bit image data signal, which changes N cycles within one cycle, as shown at 621 in FIG. The M-bit image data signal is written into a first memory corresponding to an address determined by the outputs of the N-stage shift registers 201 to 205. 251 to 255 in Figure 2
indicate output signals of shift registers 201 to 205, respectively. The output signals 251 to 255 are normally a logic 0" and are sequentially a logic 1" only once every - period to transfer the contents of the data bus 200 to the first memories 211 to 21.
Write it in 5.

The timing chart in FIG. 6 shows this situation, and 301.302, 303, 304.305 are shift registers 251, 252.253, 254.
255 output signal, 311, 312, 513, 3
14' and 315 are the first memories 211 and 315, respectively.
The contents of data stored in 212, 213, 214, and 215 are shown.

Note that diagonal lines indicate a state in which the data is uncertain.

In FIGS. 2 and 3, the image data signal carried on the data bus 200 is sent to the memory 20 at timing T1.
1, it is written to the memory 212 at timing T2, and to the memory 216 at timing T3. Thereafter, the image data is sequentially written to the memory, and at the timing TN, the image data is written to the memo IJ-215, and one cycle of the image data writing operation to the memory 1 is completed. The image data for one period described above corresponds to the image data for one scanning line shown in FIG. Further, the number N of cycles within the - period is equal to the number N of data lines in FIG.

A 21st signal 260 is a trigger signal that controls the transfer of data in the first memories 211 to 215 to the second memories 221 to 225, and the signal waveform is shown in FIG.
is shown. The data in the first memory is written all at once to the second memory while the trigger signal 522 is at logic II II, and 622 is at logic tl On.
During a certain period, the data in the second memories 221 to 225 remain stable as shown at 323. Each of the second memories 221 to 225 has M-bit data 27
1 to 275, and this M-bit data and a basic pulse train 261, which is a component of the grayscale signal, are synthesized by grayscale signal generation circuits 251 to 265 to generate grayscale signals 281 to 285 at each stage. is made. 262 is a signal that provides a voltage level to turn on the liquid crystal, and 263 is a signal that provides a voltage level to turn off the liquid crystal.
5 is generated.

FIG. 4 shows a specific example of the circuit configuration of one stage of the drive circuit of the present invention. The figure shows an example where the number of bits M of the image data supplied to the data bus is M=2, and both the first memory and the second memory are configured with 2 bits P,/l. .

In FIG. 4, 401 is a shift register, 402 is a transfer lock, 403 is an output signal of 401, and 403 specifies the address of the first memory. 412,413
are the first memories, each consisting of two inverters and two transfer gates. Image data D supplied to the 2-bit data bus 411
, and D2 are written to the first memory when shift register output 405 goes high. 422 is a second memory, which is connected to two inverters 424, 425 and 2.
It is composed of transmission gates 426 and 427. 423 is also a second memory, and its configuration is the same as 422.

421 consists of a pair of trigger signals T and 〒, T
The data in the first memories 412, 413 is transferred to the second memories 422, 423 during the period when is high. 461
is a 4-channel multiplexer which combines the 2-bit output signals 428 and 429 of the second memory (o,
One of the four types of gradation signals 432 to 435 is selected according to o), (o, 1), (1to)+(', 1).

The gradation signal 436 generated in 431 as described above is 2
The signal is converted into a liquid crystal drive signal 451 by a liquid crystal drive signal generation circuit consisting of transmission gates 441 and 442. Here, 443 and 444 are the voltage level VON that turns on the liquid crystal, and the voltage level V that turns it off, respectively.
OFF is given.

FIG. 5 shows another specific example of the circuit configuration. The difference between the example in the same figure and the example in FIG.
24 and two inverters 525 and 526.

The clocked inverter 524 is active while the trigger signal T is high, and is inactive when T is low.

In order to write data into the second memory 522 normally, the output impedance of the clocked inverter 524 needs to be set sufficiently smaller than the output impedance of the inverter 526. In FIG. 5, the same symbols as those in FIG. 4 represent the same components as explained in FIG.

By configuring the data side drive circuit as described above and driving the data line by the method described above, the drive circuit of the liquid crystal image display device can be simplified and the I
When converting to C, the chip size becomes significantly smaller, and
Power consumption during operation is significantly reduced. Therefore, by applying the drive circuit and drive method of the present invention, it is possible to realize a liquid crystal display device with low cost and low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the outline of the structure of a matrix type liquid crystal display device. FIG. 2 is a diagram for explaining the present invention in detail. FIG. 6 is a diagram for explaining how signals change in each part in FIG. 2. FIG. 4 and FIG. 5 are diagrams specifically showing a configuration example of the drive circuit of the present invention. Above 4ρ2 (Fig. 5

Claims (3)

[Claims] (1) An N-stage shift register, a first N-stage memory that is addressed by the output signal of the N-stage shift register, and a second N-stage memory that writes the contents of the first N-stage memory in synchronization with a trigger signal. an N-stage memory, an N-stage gradation signal generation circuit that generates a gradation signal for each stage from data in each stage of a second N-stage memory, and an output signal from the N-stage gradation signal generation circuit. A drive circuit for an IJ type liquid crystal display device, characterized by comprising an N-stage liquid crystal drive circuit that generates a liquid crystal drive signal and drives a liquid crystal panel. (2) The IJ type liquid crystal display device according to claim 1, wherein each stage of the first N-stage memory and the second N-stage memory is composed of a plurality of bits of memory. drive circuit. (3) M applied to the data bus in a time series of N cycles
The bit image data is sequentially written to the first M-bit memory at the address specified by the L-register output (shifted in N stages), and after the writing to the first M-bit memory is completed, the second The contents of the first M-bit memory are transferred to the second M-bit memory, the contents of the second M-bit memory are converted to a gradation signal, and the gradation signal is further converted to a liquid crystal drive signal to drive the liquid crystal. M) A method for driving an IJ type liquid crystal display device.