JPS62172392A - Display driving circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a display drive circuit that drives an XY dot matrix type flat display element.

[Background technology] Recently, X-Y dot matrix type flat display devices (flat display devices) such as EL and PDP have been attracting attention. Logic circuits are being integrated into integrated circuits. FIG. 5 is a block circuit diagram of a conventional display drive circuit implemented as an IC.
a data storage circuit 2 which is controlled based on the scan control output and outputs the output of the data storage circuit 2;
Output gate circuit 3 for applying voltage to the flat display element via
It is made up of. Here, the display data is input as serial data to the data input terminal Di of the data conversion circuit 1, and the data conversion circuit 1 consisting of a shift register transfers the serial data based on the transfer lock input to the clock terminal CL. This converts the data into parallel data and stores it in the data storage circuit 2 consisting of a latch.
A drive signal was applied to the flat display element via an output gate circuit 3 and an output buffer circuit 4 which were controlled by the output of a logic circuit for scan control. In the figure, Do
is the serial data output terminal, LE is the latch enable terminal, OE is the output enable terminal, O0 to 01
．． is the output terminal. By the way, in such a conventional example, in order to serial-to-parallel convert and store n-bit information in the data storage circuit 2 consisting of an n-bit latch, the data conversion circuit 1 consisting of an n-bit shift register is required. Normally, an n-bit shift register is constructed by arranging n stages of 70 7-lips in parallel using two stages of latches. The drive circuit required 30 latches. Therefore, as n becomes larger, the number of latches required increases significantly, and in the case of one chip, obstacles during device fabrication such as miniaturization of minimum line width and increase in device area become large, resulting in high cost. There was a problem.

[Object of the Invention] The present invention has been made in view of the above points, and its object is to reduce the number of latches,
It is an object of the present invention to provide a flat display element driving circuit which can reduce the element area without reducing the minimum line width and reduce the cost when integrated into a single chip.

[Disclosure of the Invention] (Example) Figures 1 to 3 show an example of the present invention.
In the display drive circuit similar to the conventional example shown in the figure, the data conversion circuit 1 is formed by a 4-bit shift register SR, and 8-bit serial data is converted into parallel data every 4 bits, and 4-bit latches LA, . A conversion control circuit 5 is provided to store data in a data storage circuit 2 consisting of an LA2, and the conversion control circuit 5 includes inverter circuits IN, .
7-lip 70-tub FF, -FF, and AND circuit A1
In the embodiment, 8-bit serial data is converted to parallel data using a shift register SR with 1/2 the number of bits (4 bits). , shift register SR when converting n-bit serial data to parallel data
The number of bits may be set to n/ω bits (where W is an integer of 2 or more). Note that since +1 is generally a power of 2, a power of 2 may be used as ■. Also, if n/v is not an integer, the nearest integer (〉n
/l11).

The operation of the embodiment will be described below. Serial data D is now input to the data input terminal Di of the shift register SR. -D7 is sequentially taken into the shift register SR in synchronization with the transfer lock Vc. Also, latch LA
,, LA2 receives the shift register SR outputs R0 to R1 in synchronization with the conversion control circuit 5 outputs QA and Q[+. FIG. 3 shows a time chart and a data storage state, and in the illustrated example, data is transferred at the falling edge of the transfer lock. Now, the data to be captured by the latch is transferred to all the registers of the shift register SR at the falling edge of the third clock pulse of the transfer lock Vc and at the falling edge of the seventh clock pulse. Therefore, the latch enable signal Q is output from the conversion control circuit 5 between the fall of the third clock pulse and the fall of the fourth clock pulse, and the latch enable signal Q is output from the fall of the seventh clock pulse until the fall of the fourth clock pulse. The latch enable signal Qa is sent from the conversion control circuit 5 until the clock pulse falls.
is output, and 8-bit serial data D0 to D7 are sequentially fetched into latches LA, LA, every 4 bits.

By the way, the conversion control circuit 5 is formed using three 7-lip 70-tube FFs, ~FFi, using latches, and although the number of latches is increased by the additional circuit, the number of latches used in this additional circuit is The number of latches is smaller than the reduction in the number of latches when the shift register SR is changed from 8 bits to 4 bits, and the number of latches can be reduced overall. In this case, the decrease IN of the latch is
N = n (n/2 + 0.og2n) = n/
2 + (log2n However, 0, 0g2n is the number of latches in the conversion control circuit 5. Therefore, if m = 2 and an n/2-bit shift register SR is used, an 8-bit display drive circuit uses one, 16-bit shift register SR. The number of latches can be reduced by 4 in a 64-bit display drive circuit, and 26 in a 64-bit display drive circuit.
Cost can be reduced. Further, in the embodiment, the conversion control circuit 5 is built in, but it is not necessarily necessary to build it in, and if H4 is not included, the number of latches can be further reduced. In the embodiment, the conversion control circuit 5 is formed by a counter circuit, but it goes without saying that it may be realized by other circuit configurations.

In addition, a latch control signal Vc is introduced from the outside,
For example, as shown in Figure @4, the inverter IN2.7 inverter IN2.7nd circuit A 4 t AS and OR circuit OR.

A second conversion control circuit 6 consisting of
By inputting to the latch enable terminal of A,
An 8-bit display driver circuit can be used as a 4-bit display driver circuit. Similarly, n-bit display drive circuits are set to n/2, n/3,...rl.
Needless to say, the present invention can be used as a /Φ bit display drive circuit.

[Effects of the Invention] As described above, the present invention includes a data conversion circuit consisting of a shift register that converts display data consisting of n-bit serial data into parallel data, and a data storage circuit consisting of a latch that stores the parallel data. , an output that is controlled based on the scan control output and applies the data storage circuit output to the flat display element via the output buffer circuit? -) circuit, the data conversion circuit is formed by an n/m bit (however, m is an integer of 2 or more) shift register, and the n-bit serial data is transferred to n/m bits.
It is equipped with a conversion control circuit that converts each bit into parallel data and stores it in the data storage circuit.Since serial data can be converted into parallel data using a shift register with a small number of bits, the data conversion circuit The number of latches can be reduced, and in the case of one chip, the element area can be reduced without miniaturizing the minimum line width, and the cost can be reduced.

[Brief explanation of drawings]

! @Figure 1 is a block circuit diagram of one embodiment of the present invention, Figure 2 is a circuit diagram of the same essential parts as above, Figure 3 is an explanatory diagram of the same operation as above, Figure 4 is a circuit diagram of essential parts of another embodiment, FIG. 5 is a block circuit diagram of a conventional example. 1 is a data conversion circuit, 2 is a data storage circuit, 3 is an output gate circuit, 4 is an output buffer circuit, and 5.5a is a conversion control circuit. Agent Patent Attorney Ishi 1) Ai Figure 7 4

Claims (1)

[Claims] (1) A data conversion circuit consisting of a shift register that converts display data consisting of n-bit serial data into parallel data, a data storage circuit consisting of a latch that stores the parallel data, and a data storage circuit controlled based on the scan control output. In a display drive circuit equipped with an output gate circuit that applies a storage circuit output to a flat display element via an output buffer circuit, the data conversion circuit is
However, the present invention is characterized in that it is formed by a shift register (m is an integer of 2 or more) and is equipped with a conversion control circuit that converts n bits of serial data into parallel data every n/m bits and stores it in the data storage circuit. Display drive circuit.