JPH0815393A - Data i/o circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit requiring a plurality of inputs under the test mode of an LSI in which the production cost is reduced by decreasing the number of I/O terminals thereby decreasing the area of element. CONSTITUTION:The data I/O circuit for semiconductor integrated circuit comprises a latch circuit group A where latch circuits 5a, 3a are connected in series with an input PAD 1c, and a latch circuit group B where latch circuits 5b, 3b are connected in series with the input PAD1c. The latch circuits 5a, 5b are fed with clock signals CLK1, CLK2, respectively, at a different timing. The latch circuits 3a, 3b are fed with a clock signal CLK at a same timing. When different data are fed to an I/O pad at a corresponding timing, different data are taken into the latch circuits 5a, 5b and then they are taken into the latch circuits 3a, 3b at the same timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output circuit of a semiconductor integrated circuit used in a test mode, for example, in a functional operation test of the semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional circuit will be described with reference to FIG. FIG.
In the test mode for checking the operation of the LSI,
The data input to the input PADs 1a and 1b inside the SI pass through the paths 2a and 2b, respectively, and are latched by the latch circuits 3a and 3b by the CLK signal, respectively.
The signals from a and 4b were used as data used in the test mode or the like. As described above, when there are two terminals used in the test mode, it is necessary to incorporate two independent input PADs into the integrated circuit, resulting in an increase in element area. Then input PAD
JP-A-2-105452 describes that a plurality of internal circuits are connected to one input PAD in order to reduce the number of input PADs and one input PAD is used in a time division manner by switching by switching means. There is one.

[0003]

Conventionally, when there are 2N input terminals used in the test mode, L is accordingly changed.
The number of PADs incorporated in SI was also required to be 2N.
Further, in the case of the switching method by the switching means, there is a problem that different data cannot be given to the internal circuit at the same time (at the same rising timing) and the content of the test is limited.

Therefore, the present invention provides a data input / output circuit of a semiconductor integrated circuit which can perform the same test as when the test pads are connected to the individual internal circuits and can reduce the number of input / output pads. The purpose is to do.

[0005]

In order to solve the above problems, the present invention provides first data in which first and second data latch circuits are connected in series between a first internal circuit and a data input / output pad. Latch means is provided, and second data latch means in which third and fourth data latch circuits are connected in series is provided between the second internal circuit and the data input / output pad, and the first and third data latch circuits are provided. The data latch timing was shifted.

[0006]

In the first and third data latch circuits, the conventional clock is latched at the timing of the clock with some delay. Therefore, if different data is supplied to the same input / output pad at a timing corresponding to the fetch timing, different data is fetched in the first and third data latch circuits. The data fetched by the first and third data latch circuits is fetched by the second and fourth data latch circuits at the same timing, and a data input / output pad is provided for each conventional internal circuit. You can test as if you were there.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment to which the present invention is applied will be described with reference to FIGS. In FIG. 1, a first latch circuit group A in which a first latch circuit 5a and a second latch circuit 3a are connected in series with respect to the input PAD1c, and a first latch circuit 5b with respect to the input PAD1c, A second latch circuit group B in which the second latch circuit 3b is connected in series is provided. Clock signals CLK1 and CLK2 having a delay are supplied to the first latch circuit 5a and the first latch circuit 5b. The clock signal CLK having the same timing is supplied to the second latch circuit 3a and the second latch circuit 3b. The first latch circuit group A is connected to the internal circuit 7a, and the second latch circuit group B is connected to the internal circuit 7b. FIG. 2 shows the timing of the clock signal input to this latch.

For example, the data A externally input to the PAD 1c is latched at 5a at the rising edge of CLK1. Next, the data input to the PAD 1c is changed to B before the rising edge of CLK2, and CLK2 is raised when the latch circuit 5b sufficiently satisfies the setup time with respect to the rising edge of CLK2. Then, the data A is stored in the latch circuit 5a, and the data B is stored in the latch circuit 5b.

While both CLK1 and CLK2 are "H" and the data A and B are stored in each other, the data A and B are sent to the latch circuits 3a and 3b through the paths 6a and 6b, respectively. Latch circuit 3 that holds data by CLK, which is an internal execution cycle
In order to store data in a and 3b, as shown in FIG.
CLK rises before LK1 falls. Then
The data A and B input at different timings are CLK
It becomes a signal of the same cycle that changes according to, and it can be used as data suitable for the execution cycle inside the LSI.

Here, it is assumed that there is a sufficient hold time for the switching timing of the data A and B with respect to the rising edge 10a of CLK1 and CLK2 for the data B.
It is assumed that there is a sufficient setup time for the rising edge of and the data A and B have sufficient setup time for being latched in the latch circuits 3a and 3b by CLK through the paths 6a and 6b. Further, the latch circuits (3a, 3b, 5a, 5b) are low-pass high latch circuits that pass the data input when the clock is "L" and latch the data in response to the rising edge of the clock.

In the above embodiment, the first latch circuit group is used.
Although the example in which the two latch circuit groups A and B of the second latch circuit group B are connected to one pad is shown, the same holds true even if three or more latch circuit groups are connected in parallel. Needless to say, it works.

[0012]

As described above, by adding another latch circuit before the circuit that first latches the data input from the outside, the conventional LSI chip can be connected from two input terminals. Two PAs on top
The data input to D can be input from one PAD.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 3 is a circuit block diagram showing a conventional example.

[Explanation of symbols]

 a-c LSI internal input PAD 2a-d, 4a-b, 6a-b Data transmission path 3a-b, 5a-b Latch circuit 10a-c Clock switching timing CLK Internal execution cycle CLK1, CLK2 Latch circuit control clock

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Claims (1)

[Claims] 1. A data input / output circuit for connecting at least two first and second internal circuits to one data input / output pad, the data input / output circuit being provided between the first internal circuit and the data input / output pad. A first data latch circuit is provided in which first and second data latch circuits are connected in series, and third and fourth data latch circuits are connected in series between the second internal circuit and the data input / output pad. 2. A data input / output circuit for a semiconductor integrated circuit, wherein the data latch means of 2 is provided and the data latch timings of the first and third data latch circuits are shifted.