JP2000275304A - Logic integrated circuit and semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the overhead for delay and area of a logic integrated circuit. SOLUTION: A semiconductor device is a system LSI which can carry out tests by using a hierarchized BIST(built-in self test) method utilizing the framework of automatic diagnosis at every block and is provided with a control section 12 which controls tests, a test pattern generator 13, a test output compressor 14, a plurality of flip flop circuits 15 for scanning, etc., in each split block IP1 and IP2 in addition to an internal logic circuit 11. An inter-block buffer 21 having a function of independently scanning the two systems of blocks IP1 and IP2 at testing time and another function of passing by the blocks IP1 and IP2 at normal time is connected between the blocks IP1 and IP2 in such a way that the output from the flip flop circuit 15a corresponding to the preceding-stage block IP1 becomes the input of the flip flop circuit 15b corresponding to the poststage block IP2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit technology for a semiconductor device, and more particularly, to a hierarchical BIST (Built-In) for each block accompanying an increase in the scale of an LSI and system LSI.
The present invention relates to a logic integrated circuit suitable for a self-test method and a technique effective when applied to a semiconductor device using the same.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, in a system LSI, a block (IP:
For example, there may be a technique in which the test is divided into individual properties and a test is performed by the BIST method for each layer using the framework of the automatic diagnosis.

[0003] As a technique related to such a test of a system LSI or the like, for example, May 30, 1997
Published by Press Journal, Inc. “Monthly Semi
conductor World extra number ULSI test technology ".

[0004]

By the way, in the above system LSI and the like, the connection between the blocks is
It is necessary to realize a function of passing between blocks and a function of latching a control signal. In this case, since a flip-flop having these functions is required for each block, delay overhead and area overhead may be increased.

For example, in an LSI comprising a plurality of IPs, as shown in FIGS.
An inter-block buffer is inserted between them, and a flip-flop circuit 15a for scanning the output IP1 and an input I
The connection / disconnection of the P2 scan flip-flop circuit 15b is controlled by a control signal Control. For this reason, an inter-block buffer having a large driving force has to be connected to the outside of IP1 and IP2, resulting in very large overhead in terms of delay and area.

Therefore, an object of the present invention is to devise a configuration of an inter-block buffer so that two systems of blocks can be independently scanned, thereby reducing delay overhead and area overhead. An integrated circuit and a semiconductor device using the same are provided.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the logic integrated circuit according to the present invention has a function of passing between blocks (normal time) and a hierarchical BI
At the time of the test by the ST method, an inter-block buffer having a function of independently scanning two blocks is provided.

[0010] In this configuration, the inter-block buffer is integrated into one cell and further taken into the output block. The block is IP
It consists of

Specifically, the inter-block buffer is configured such that flip-flop circuits which receive an input signal and a scan input signal and output an output signal and a scan output signal are cascaded in two stages. A signal is connected so as to be an input signal of a subsequent flip-flop circuit, an output signal from a preceding flip-flop circuit is extracted from a connection node of a cascade-connected latch circuit in two stages, or a data path and a scan path are connected. And when the input signal is passed through, the signal is transmitted only through a buffer having a large driving force.

A semiconductor device according to the present invention includes a plurality of blocks formed on a single semiconductor chip using the logic integrated circuit.

Therefore, according to the logic integrated circuit and the semiconductor device using the same, two blocks can be independently scanned, so that delay overhead and area overhead can be reduced. That is, since the function of independently scanning two blocks is integrated in the inter-block buffer, delay overhead is reduced. Furthermore, since it also serves as an inter-block buffer, the area overhead can be reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1) FIG. 1 is a schematic functional block diagram showing a main part of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 3 and 4 are signal waveform diagrams showing operations during normal operation and during test.

First, an example of the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG.

In the semiconductor device according to the first embodiment, for example, a hierarchical BI using an automatic diagnosis framework for each block is used.
It is a system LSI that can be tested by ST method,
It is composed of a plurality of divided IP1, IP2,
The IP2 includes, in addition to the internal logic circuit 11, a control unit 12 for controlling a test, a test pattern generator 13 for generating a test pattern, a test output compressor 14 for collecting and compressing a test output, and a sequential circuit. A plurality of flip-flop circuits 15 for scanning are provided. FIG.
Exemplarily shows two IP1 and IP2.

For example, as shown in FIG.
An inter-block buffer 21 including a scan flip-flop circuit 15 and the like is inserted therebetween, and the output side IP1
Flip-flop circuit 15a corresponding to
And a flip-flop circuit 15b for scanning corresponding to IP2 on the input side are integrated into one cell, and are taken into IP1 on the output side. That is, IP1 and IP1
Flip-flop circuits 15a and 15b connecting
Are integrated.

The inter-block buffer 21 has a function of independently scanning the two systems of IP1 and IP2 during a test and a function of passing between IP1 and IP2 at normal times. For example, as shown in FIG. Flip-flop circuits 15a and 15b that receive an input signal and a scan input signal as input and output an output signal and a scan output signal are cascaded in two stages, and an output signal from the flip-flop circuit 15a corresponding to the preceding stage IP1 is transmitted to the succeeding stage. It is connected so as to be an input signal of the flip-flop circuit 15b corresponding to IP2.

Flip-flop circuit 1 corresponding to IP1
5a is an input signal D, an inverted scan input signal / SiD1
Are respectively input and the scan test clock signal M
1 and SWi controlled by input control inverters A1 and A2, a latch circuit L1 connected to the inverters A1 and A2, and a scan test clock signal C2 and / C2 connected to the latch circuit L1. A pass transistor PT1 to be controlled, a latch circuit L2 connected to the pass transistor PT1,
The buffer circuit B1 is connected to the latch circuit L2 and outputs an inverted scan output signal / SoD1. When the input control inverter A1 is at the scan test clock signal M1 = "H", the input control inverter A2 is at the scan test clock signal SWi = "H".
Inverter output at each time.

Flip-flop circuit 1 corresponding to IP2
5b is a flip-flop circuit 15a corresponding to IP1.
And an inverter A3, A4 with input control, which are respectively controlled by a control signal Control and a scan test clock signal SWi, which receive an input signal based on an output signal from the controller and an inverted scan input signal / SiD2. A latch circuit L3 connected to the inverters A3 and A4, and a scan test clock signal C connected to the latch circuit L3.
2, a pass transistor PT2 controlled by / C2, a latch circuit L4 connected to the pass transistor PT2, and an inverted scan output signal / SoD2 and an inverted output signal / Q connected to the latch circuit L4. Buffers B2, B3, etc. Inverter A3 with input control receives control signal C
When control = “H”, inverter A with input control
Reference numeral 4 denotes an inverter output when the scan test clock signal SWi = "H". In addition, the inverted output signal /
As the buffer B3 that outputs Q, a high-drive buffer having a large driving force for transmission is used.

Next, the operation of the first embodiment will be described with reference to FIG. 3 and FIG.

In the normal use state (FIG. 3), the output from IP1 is passed to IP2 so that it must be passed through.
Therefore, the flip-flop circuit 15 corresponding to IP1
a, in the flip-flop circuit 15b corresponding to IP2, the scan test clock signal M1 = "H";
This can be realized by setting SWi = “L”, C2 = “H”, and setting the control signal Control = “H”.

In the setting state of each signal, in the flip-flop circuit 15a corresponding to IP1, the input signal D is output as an inverter by the inverter A1 with input control, and the latch circuit L1, the pass transistor PT1, and the latch circuit The signal is output to the flip-flop circuit 15b corresponding to IP2 via L2.

Further, in the flip-flop circuit 15b corresponding to IP2, an output signal from the flip-flop circuit 15a corresponding to IP1 is used as an input signal, and this input signal is output as an inverter by an inverter A3 with input control. L3, pass transistor P
T2, the inverted output signal passed through the latch circuit L4 /
Q is output via a high-drive buffer B3. This inverted output signal / Q is an inverted signal delayed with respect to the input signal D.

At this time, the inverted scan input signal / SiD
1, / SiD2 is "Don't Care", the inverted scan output signal / SoD1 is a signal delayed with respect to the input signal D, and the inverted scan output signal / SoD2 is a further delayed inverted signal. The inverted scan output signal / SoD2 has the same phase and the same timing as the inverted output signal / Q.

At the time of testing (FIG. 4), each block of IP1 and IP2 is tested by hierarchical BIST using an automatic diagnosis framework. At this time, IP1, I
Each scan chain of P2 needs to operate independently. For this reason, the control signal Control
= L, two blocks can be independently scanned by a scan signal.

That is, in the flip-flop circuit 15a corresponding to IP1 and the flip-flop circuit 15b corresponding to IP2, the scan test clock signal M
1, SWi and C2 are applied with predetermined clock signals, respectively, and the control signal Control = “L”
Can be realized. Here, each of the scan test clock signals M1, SWi, and C2 is generated with one clock, three clocks, and four clocks in one cycle corresponding to the time width of four clocks, and the clock of M1 is generated. The SWi clock is generated in the non-existing portion.

In the setting state of each signal, in the flip-flop circuit 15a corresponding to IP1, the input inverted scan input signal / SiD1 is inverter-outputted by the inverter A2 with input control, and further latched by the latch circuit L1. After passing through the pass transistor PT1, the signal is latched by the latch circuit L2, and the latched inverted scan output signal / SoD1 is output.

At this time, the inverted scan input signal / SiD
1 and the inverted scan output signal / SoD1 are represented by the inverted scan input signal / SoD corresponding to each rising edge (black circle) of the scan test clock signal SWi.
At each rising edge (open circle) of the scan test clock signal C2, the inverted scan output signal / So
The input signal D (“Don't Care” at other timings) output as D1 and determined at the rise of the scan test clock signal M1 is inverted at the rise of the scan test clock signal C2. Is output as

Similarly, in the flip-flop circuit 15b corresponding to IP2, the input inverted scan input signal / SiD2 is inverter-outputted by the inverter A4 with input control, further latched by the latch circuit L3, and passed through the pass transistor PT2. After that, the signal is latched by the latch circuit L4, and the latched inverted scan output signal / SoD2 is output.

At this time, the inverted scan input signal / SiD
2 and the inverted scan output signal / SoD2 do not depend on the input signal D, and the inverted scan input signal / SiD2 corresponding to each rising edge of the scan test clock signal SWi is the scan test clock signal C2. Is output as an inverted scan output signal / SoD2 at each rising edge of.

As a result, the two blocks of the flip-flop circuit 15a corresponding to IP1 and the flip-flop circuit 15b corresponding to IP2 can be independently scanned by the inverted scan input signals / SiD1 and / SiD2. As described above, each IP shifts the scan data by the scan flip-flop circuit or shifts the input signal to BIST by shifting the input signal.
The control pattern is transmitted to the control unit 12 of the
By transmitting data by scan-shifting data such as a result, a test can be performed for each block.

Therefore, according to the semiconductor device of the first embodiment, the flip-flop circuit 15a corresponding to IP1
As in the flip-flop circuit 15b corresponding to IP2, an inter-block buffer 21 composed of a flip-flop circuit for scanning or the like is inserted between IPs, and has a function of independently scanning two blocks in the inter-block buffer 21. Since they are integrated, the overhead of delay can be reduced. Further, since the buffer 21 also serves as the inter-block buffer 21, the area overhead can be reduced.

(Embodiment 2) FIG. 5 is a circuit diagram showing an inter-block buffer in a semiconductor device according to Embodiment 2 of the present invention.

The semiconductor device according to the second embodiment is a system LSI capable of performing a test by the hierarchical BIST method using an automatic diagnosis framework for each block, similarly to the first embodiment, The first embodiment is different from the first embodiment in that
Scan flip-flop circuit 15 inserted between
The connection mode of the inter-block buffer 21a is different from that of the first embodiment in that an output signal from the preceding flip-flop circuit 15a is extracted from a connection node of a latch circuit cascaded in two stages.

That is, as shown in FIG. 5, for example, as shown in FIG. 5, the inter-block buffer 21a of the second embodiment includes a latch circuit L1 of a flip-flop circuit 15a corresponding to IP1.
Output from the flip-flop circuit 15b corresponding to IP2
And the input-controlled inverter A3 of the flip-flop circuit 15b corresponding to IP2 is replaced with a pass transistor PT3.

Also in this configuration, at the time of a test, the control signal Control is set to "L" so that I
The flip-flop circuit 15a corresponding to P1 outputs an inverted scan output signal / SoD1 in response to the input inverted scan input signal / SiD1.
The flip-flop circuit 15b corresponding to IP2 can also output the inverted scan output signal / SoD2 in response to the input inverted scan input signal / SiD2.

Therefore, according to the semiconductor device of the second embodiment, as in the first embodiment, the function of independently scanning two systems of blocks is integrated in the inter-block buffer 21a. Delay and area overhead can be reduced. In particular, as compared with the first embodiment, by connecting the output of the latch circuit L1 to the input of the latch circuit L3, the overhead of the delay of two stages of the inverter can be further reduced, and the inverter A3 with input control can be connected to the pass transistor PT3. , The area overhead can be further reduced.

(Embodiment 3) FIG. 6 is a circuit diagram showing an inter-block buffer in a semiconductor device according to Embodiment 3 of the present invention.

The semiconductor device according to the third embodiment is a system LSI that can be tested by the hierarchical BIST method using an automatic diagnosis framework for each block, similarly to the first and second embodiments, and is divided. Multiple IP1, IP2
The difference from Embodiments 1 and 2 is that
The connection form of the inter-block buffer 21b including the scan flip-flop circuit 15 and the like inserted between the IP1 and the IP2 is different, the data path and the scan path are separated, and a buffer having a large driving force is used when the input signal is passed through. This is the point that transmission is made only through the transmission.

That is, as shown in FIG. 6, for example, as shown in FIG. 6, in the flip-flop circuit 15a corresponding to IP1, the inter-block buffer 21b of the third embodiment includes an input of the input-controlled inverter A1 of the input signal D and a latch circuit. A buffer B5 with input control of high driving force is connected between the output of buffer B4 with input control connected to the output of L2 to form a signal path from the input of input signal D to the output. The path is connected to the input of the input-controlled inverter A3 of the flip-flop circuit 15b corresponding to IP2 and the output of the input-controlled buffer B6, thereby forming a data path separated from the scan path. The buffers B4 to B6 with input control function as buffers when the control signals Ctrl1 to Ctrl3 are "H", respectively.

In this configuration, when the data from IP1 is normally passed to IP2, the control signal C
trl1 = “H”, Ctrl2 = “L”, Ctrl3 =
The data is set to “L”, and data is transmitted to IP2 only through the buffer having a large driving force of the buffer B5 with input control. As a result, the delay can be minimized as much as no extra buffer is passed on the way. When scanning the test data, the control signal Ctrl1
= “L”, Ctrl2 = “H”, Ctrl3 = “L”, the inverted scan input signal / SiD1 and the inverted scan output signal / S
oD1 and / SoD2 can be scanned respectively.

Therefore, according to the semiconductor device of the third embodiment, as in the first and second embodiments, the function of independently scanning two blocks in the inter-block buffer 21b is integrated. Therefore, the delay and the overhead of the area can be reduced. In particular, as compared with the first and second embodiments, the data path and the scan path are separated, and the data is normally transmitted only through the buffer B5 with input control, so that the delay is minimized by the amount not passing through the extra buffer. Can be minimized.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible. For example, the present invention is particularly applicable to a large-scale system LSI.
However, the present invention can be widely applied to all LSIs using the hierarchical BIST method.

[0046]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In addition to the function of passing between blocks,
By providing an inter-block buffer having a function of independently scanning two systems of blocks, the two systems of blocks can be independently scanned, so that delay overhead can be reduced.

(2) In the above (1), the function of independently scanning the two systems of blocks also serves as an inter-block buffer, so that the area overhead can be reduced.

(3) According to the above (1) and (2), it is possible to reduce the delay and the overhead of the area in the semiconductor device by the hierarchical BIST system for each block accompanying the increase in the scale and the system LSI. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic functional block diagram illustrating a main part of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating an inter-block buffer.

FIG. 3 shows a semiconductor device according to the first embodiment of the present invention;
It is a signal waveform diagram which shows operation | movement at the time of normal.

FIG. 4 shows a semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a signal waveform diagram showing an operation at the time of a test.

FIG. 5 is a circuit diagram showing an inter-block buffer in the semiconductor device according to the second embodiment of the present invention;

FIG. 6 is a circuit diagram showing an inter-block buffer in the semiconductor device according to the third embodiment of the present invention;

FIG. 7 is a schematic functional block diagram showing a main part of a semiconductor device which is a premise of the present invention.

FIG. 8 is a circuit diagram showing an inter-block buffer in the semiconductor device on which the present invention is based;

[Explanation of symbols]

 1, 2 IP 11 internal logic circuit 12 control unit 13 test pattern generator 14 test output compressor 15, 15a, 15b flip-flop circuit 21, 21a, 21b inter-block buffer A1-A4 inverter with input control L1-L4 latch circuit PT1 ~ PT3 pass transistor B1 ~ B3 buffer B4 ~ B6 buffer with input control

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toyoto Ikeya 6-16-6 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Yasuo Sato 6-16 Shinmachi, Ome-shi, Tokyo F3 term in the Hitachi, Ltd. Device Development Center Co., Ltd. (Reference) 2G032 AA01 AA04 AC10 AK12 AK16 AK19 5B048 AA20 CC11 CC18 DD10 5F038 CD08 CD09 DF14 DF16 DT02 DT04 DT06 DT07 DT08 DT18 EZ20 5J0500 BB00 001 LZ05

Claims (8)

[Claims] 1. A logic integrated circuit comprising a plurality of divided blocks and capable of performing a test by a BIST method using an automatic diagnosis framework for each block, wherein two blocks of the blocks are independently scanned. A logic integrated circuit comprising an inter-block buffer having a function and a function of passing between blocks. 2. The logic integrated circuit according to claim 1, wherein
A logic integrated circuit, wherein the inter-block buffer is integrated into one cell. 3. The logic integrated circuit according to claim 2, wherein
The logic integrated circuit, wherein the inter-block buffer is fetched by the output-side block. 4. The logic integrated circuit according to claim 1, wherein:
The logic integrated circuit, wherein the block comprises an IP. 5. The logic integrated circuit according to claim 1, wherein:
The inter-block buffer has an input signal and a scan input signal as inputs, and an output signal and a flip-flop circuit for outputting a scan output signal are cascaded in two stages, and an output signal from the preceding flip-flop circuit is connected to the subsequent flip-flop. A logic integrated circuit, which is connected to be an input signal of a circuit. 6. The logic integrated circuit according to claim 5, wherein
The output signal from the preceding flip-flop circuit is 2
A logic integrated circuit which is extracted from a connection node of a latch circuit cascaded in stages. 7. The logic integrated circuit according to claim 1, wherein:
The logic integrated circuit according to claim 1, wherein the inter-block buffer has a data path and a scan path separated from each other, and is transmitted only through a buffer having a large driving force when an input signal is passed. 8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
A semiconductor device using the logic integrated circuit according to any one of claims 1 to 3, wherein the plurality of blocks are formed on one semiconductor chip.