JP3501885B2 - Scan test circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan test circuit incorporated in a semiconductor integrated circuit (hereinafter referred to as an IC) for implementing a scan path method, and more particularly to a C test circuit.
The present invention relates to a scan test circuit used in an IC developed by a MOS cell-based design method.

[0002]

2. Description of the Related Art Recently, a scan test circuit has begun to be widely adopted up to a consumer IC level as a method for designing testability. FIG. 3 is a block diagram showing an outline of the configuration of a conventional scan test circuit used in an IC developed by the CMOS cell-based design method. The scan test circuit shown in FIG. 3 is used for a test of a scan path system, enables the test to be performed for each functional block, and improves the test efficiency and the fault coverage. 4 and 5 are gate-level circuit diagrams of the selection circuit which is a component of the scan test circuit shown in FIG.

In FIG. 3, 1 _n is a first input terminal 5 _n , a second input terminal 6 _n , a selection signal input terminal 7 _n, and an output terminal 4.
A selection circuit having _n (hereinafter referred to as MPX), 2 _n is a D flip-flop circuit (hereinafter referred to as DFF circuit) having a data input terminal 9 _n , a data output terminal 10 _n, and a clock input terminal 8 _n . Is an internal logic circuit for processing data provided from the DFF2 _n . Here, the subscript n is an arbitrary integer and indicates what stage the DFF circuits connected in series are, or what stage the DFF circuits are related to. Figure 3 shows the DFF up to the third stage
The circuit 2 ₃ is shown.

Normal data D _n is applied to the first input terminal 5 _n of MPX1 _n . The second input terminal ₆₁ of the first MPX1 ₁ is given a serial test data STEST. The second input terminal 6 _n after the second stage MPX1 ₂
Is connected to the output terminal 10 _n-1 of the preceding DFF circuit 2 _n-1 . The selection signal Sen given to MPX1 _n selection signal input terminal 7 _n, the output terminal 4 _n of MPX1 _n,
One of the data input to the first input terminal 5 _n or the second input terminal 6 _n is output.

The output terminal 4n of the MPX 1n is connected to the input terminal 9n of the DFF circuit 2n. Also, DFF
The output terminals 101 to 10n of the circuits 21 to 2n are connected to the internal logic circuit 3, and the held test data or normal data is output from the DFF circuits 21 to 2n in synchronization with the clock.

Next, the operation of the scan test circuit will be described with reference to the block diagram shown in FIG. During normal (implementation), normal data to be processed by the internal logic circuit 3 is input from the first input terminals 5 _{1 to} 5 _{n of} the scan test MPX _{1 1} to 1 _n . At this time, the MPX1 ₁ to 1 _n are controlled by the selection signal Sen input to the selection signal input terminals 7 _{1 to} 7 _n so as to select the first input terminals 5 _{1 to} 5 _n . for that reason,
Ordinary data D ₁ to applied to the first input terminals 5 _{1 to} 5 _n
D _n is output from MPX1 ₁ to 1 _n output terminals 4 ₁ to 4 _n of. DFF circuit 2 output terminals 4 ₁ to 4 _n is connected
_{1 to} 2 _n perform normal operation such that the normal data D _{1 to} D _n are latched and output to the internal logic circuit 3. Therefore,
During normal operation, the normal data D _{1 to} D _n are respectively M
It is supplied to the internal logic circuit 3 through the PX1 ₁ to 1 _n and the DFF circuits 2 ₁ to 2 _n in synchronization with the clock.

On the other hand, in the scan test, first, at the first timing synchronized with the clock, the first bit of the serial test data Stest is MPX1 for the scan test.
It is input to the second data input terminal 6 _{1 1.} At this time M
The PX1 ₁ is controlled to select the second input terminal 6 ₁ by the selection signal Sen input to the selection signal input terminal 7 ₁ . Therefore, the data received by the second input terminal 6 ₁ is output to the output terminal of MPX1 ₁ . The first bit of the test data Stest output from the output terminal 4 ₁ is DF
The data is latched by the F circuit 2 ₁ and output from the data output terminal 10 ₁ of the DFF circuit 2 ₁ in synchronization with the clock.

Next, at the second timing synchronized with the clock, the second bit of the test data Stest is MP
It is input to the second data input terminal 6 ₁ of X1 ₁ . Since the second data input terminal 6 ₁ is selected by the selection signal Sen, the second bit of the test data Stest is DFF.
The data is latched by the circuit 2 ₁ and applied to the second data input terminal 6 ₂ of the MPX 1 ₂ in the next stage. Further, MPX1 ₂ second data input terminal 6 ₂ is, because it is selected by the selection signal Sen, the second bit of the test data Stest from MPX1 _second output terminal 4 ₂ is output. At this time, the DFF circuit 2
The first bit of the test data Stest being latched by ₂ is applied to a second input terminal 6 ₃ of the next stage MPX1 _3.

Further, at the third timing synchronized with the clock, the third bit of the test data Stest is M
It is input to the second data input terminal 6 ₁ of PX1 ₁ . Since the second data input terminal 6 ₁ is selected by the selection signal Sen, the third bit of the test data Stest is DF
It is latched by the F circuit 2 ₁ and given to the _second data input terminal 6 ₂ of the MPX 1 ₂ in the next stage. Further, MPX1 ₂ second data input terminal 6 ₂ is, because it is selected by the selection signal Sen, test data from the MPX1 _second output terminal 4 ₂ STEST
The third bit of is output. At this time, the second bit of the test data Stest latched by the DFF circuit 2 ₂ is given to the second input terminal 6 ₃ of the MPX 1 ₃ at the next stage. At the same time, the first bit of the test data Stest latched by the DFF circuit 2 ₃ is the M bit of the next stage.
Given to PX.

In this way, each bit of the test data Stest is sequentially transferred from the DFF circuit 2 ₁ to the DFF circuit 2 _n , and when all the test data Stest are latched by the DFF circuits 2 ₁ to 2 _n , the test is performed. Carry out. DFF circuit 2
_{1 to} 2 _n are serially connected to check the operation of all DFF circuits, and to check the normal operation of the internal logic 3 efficiently and accurately. A method of partially testing a large-scale integrated circuit by the above procedure is called a scan test.

Next, the configuration and operation of the selection circuits 1 ₁ to 1 _n will be described with reference to FIGS. 4 and 5. MP shown in FIG.
X is two inverters IN1 and IN2, four P-channel MOS transistors Q1 to Q4 and four N-channel MO.
It is composed of S transistors Q5 to Q8. Transistor Q1 having a gate connected to the first input terminal 5
And a transistor Q2 having a gate connected to the selection signal input terminal 7 are connected in series between the input terminal of the inverter IN2 and the power supply terminal 11. Further, the transistor Q3 having a gate connected to the second input terminal 6 and the transistor Q4 having a gate connected to the output terminal of the inverter IN1 that outputs the negation of the selection signal Sen are connected to the power supply terminal 11 and the input of the inverter IN2. It is connected between the terminals. On the other hand, N-channel MOS transistors Q5
Q8 is connected differently from P-channel MOS transistors Q1 to Q4. That is, the selection signal input terminal 7
Transistor Q5 having a gate connected to and a transistor Q5 having a gate connected to the first input terminal 5
7 is connected in series between the input terminal of the inverter IN2 and the node N1. A transistor Q8 having a gate connected to the output terminal of the inverter IN1 that outputs the negation of the selection signal Sen and a transistor Q6 having a gate connected to the second input terminal 6 are provided between the node N1 and the ground potential point 12. Are connected in parallel.

Next, the operation of MPX will be described with reference to FIG. First, normally, the selection signal Sen input to the selection signal input terminal 7 is set to the low level. At this time, the transistors Q2 and Q8 turn on, and the transistors Q4 and Q8
Since 5 is turned off, the data Din input from the first input terminal 5 is output from the output terminal 4 of the MPX via the inverter IN2. Therefore, according to the normal data Din,
Either one of the current path formed by the transistors Q1 and Q2 or the current path formed by the transistors Q7 and Q8 becomes conductive. Therefore, the output of the inverter IN2 is
The same data as the normal data Din appears at the output terminal 4.

When the current path formed by the transistors Q7 and Q8 is in the conductive state, the transistor Q6 is turned on / off according to the test data Sin, so that the inverter
The current flowing between IN2 and the ground potential point 12 may change.

During the scan test, the selection signal Sen input to the selection signal input terminal 7 is set to the high level. At this time, the transistors Q4 and Q5 are turned on and the transistors Q2 and Q8 are turned off, so that the second input terminal 6
Data Sin that is input via the inverter I N2 from
It is output from the output terminal 4 of the MPX. Therefore, according to the data Sin input for the test, the transistor Q
3, Q4 current path or transistor Q5
Either one of the current paths formed by Q6 becomes conductive. In the MPX shown in FIG. 4, all transistors have the same size. That is, the MPX shown in FIG.
The transistors Q1 to Q8 have the same value obtained by dividing the gate width W by the gate length L.

When the current path consisting of the transistors Q5 and Q6 is in the conducting state, the transistor Q7 is turned on / off in accordance with the normal data Din, so that the inverter is turned on.
The current flowing between IN2 and the ground potential point 12 may change.

The MPX shown in FIG. 5 is a single inverter.
IN3 and two P-channel MOS transistors Q12, Q
14 and two N-channel MOS transistors Q11, Q
It is composed of 13. First input terminal 5 and output terminal 4
Are connected via a transmission gate composed of transistors Q11 and Q12. The gate of the transistor Q11 is connected to the output terminal of the inverter IN3, and the gate of the transistor Q12 is connected to the selection signal input terminal 7.

The second input terminal 6 and the output terminal 4 are
It is connected through a transmission gate composed of transistors Q13 and Q14. The gate of the transistor Q13 is connected to the selection signal input terminal 7, and the gate of the transistor Q14 is connected to the output terminal of the inverter IN3.

In FIG. 5, the selection signal Sen is normally set to the low level. At this time, the transistor Q1
1, Q12 is turned on, and the transistors Q13, Q14 are turned off, so that the data Din passes through the transmission gate formed by the transistors Q11, Q12.

During the scan test, the selection signal Sen is set to the high level. At this time, the transistors Q13, Q
14 is turned on and the transistors Q11 and Q12 are turned off, so that the data Sin passes through the transmission gate formed by the transistors Q13 and Q14. In the MPX shown in FIG. 5, all the transistors Q11
~ Q14 are the same size .

[0020]

Since the conventional scan test circuit is constructed as described above, the P-channel and N-channel MOS transistors must be provided in order to ensure a sufficient speed for the data input at the normal time. Size W /
Although L can be optimally selected, timing verification can be performed by virtual delay simulation before layout, and circuit countermeasures can be taken in advance, but scanning is not required so much for input, but scanning is performed. DFF circuit 2 _n-1 of the output terminal 10 _n-1 and MPX to have to have the same speed as the normal operation even in the test
There is a problem that the hold time of the DFF circuit may not be secured unless the delay element is purposely inserted between the 1 _n second input terminal 6 _n . Where n is 1
It is an arbitrary natural number above.

Particularly in the case of an IC having a large number of DFF circuits, this causes an increase in the number of elements, which causes a problem that the layout correction work takes time due to an increase in chip size or occurrence of a timing error after layout.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a scan test circuit capable of reducing the correction work after layout without increasing the number of elements as compared with the prior art. To aim.

[0023]

A scan test circuit according to a first aspect of the present invention includes a plurality of flip-flop circuits each having a data input terminal and a data output terminal connected to an internal logic circuit, and the plurality of flip-flop circuits. A first input terminal connected to said data output terminal of the corresponding one of the circuits or directly provided with test data;
It has a second input terminal for receiving normal data supplied to the internal logic circuit at the time of non-test, a selection signal input terminal, and an output terminal, and the first or first selection signal is input by the selection signal input terminal. A plurality of selection circuits that selectively output the data received at the two input terminals from the output terminals, and the plurality of selection circuits are provided between the first input terminal and the output terminal, respectively. A first gate circuit for selectively passing data received at the first input terminal, and data received at the second input terminal provided between the second input terminal and the output terminal. A second gate circuit that selectively passes therethrough, and a first value obtained by dividing a gate width of a first insulated gate field effect transistor that constitutes the first gate circuit by a gate length is the second value .
Is smaller than a second value obtained by dividing the gate width of the second insulated gate field effect transistor forming the gate circuit by the gate length .

A scan test circuit according to a second invention is the scan test circuit according to the first invention, wherein:
The value of 1 is less than or equal to half of the second value .

[0025]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. A scan test circuit according to the first embodiment of the present invention will be described below with reference to FIG. The relationship between the MPX, the DFF circuit and the internal logic circuit forming the scan test circuit is as shown in FIG.

That is, the MPX1 _n has the first input terminal 5 _n to which the normal data D _n is applied, the second input terminal 6 _n to which the test data Stest is applied, and the selection signal input terminal 7 _n to which the selection signal Sen is applied. And an output terminal 4 _n . DFF
The circuit 2 _n has a data input terminal 9 _n , a data output terminal 10 _n, and a clock input terminal 8 _n . The internal logic circuit 3 is an IC
The data provided inside the DFF circuit 2 _n is processed. FIG. 3 shows a portion in which the value of n is 1 to 3, and MPX and DF that configure other scan paths.
The description of the stage of the F circuit is omitted.

FIG. 1 is a circuit diagram showing the configuration of the MPX according to the first embodiment. In FIG. 1, IN4 is an inverter having an input terminal connected to the selection signal input terminal 7 and an output terminal for outputting the negation of the selection signal Sen received at the input terminal, and IN5 is given to the input terminal and the input terminal. An inverter having an output terminal connected to the output terminal 4 for outputting the negation of the signal, Q21 is a drain and a power supply terminal 11
A P-channel MOS transistor having a source connected to the first input terminal and a gate connected to the first input terminal 5, Q22
Is a P-channel MOS transistor having a drain connected to the input terminal of the inverter IN 5 , a source connected to the drain of the transistor Q21, and a gate connected to the selection signal input terminal 7, and Q23 is a drain and power supply terminal 1
A P-channel MOS transistor having a source connected to 1 and a gate connected to the second input terminal 6, Q2
4 is a P-channel MOS transistor having a drain connected to the input terminal of the inverter IN 5 , a source connected to the drain of the transistor Q 23, and a gate connected to the output terminal of the inverter IN 4, and Q 25 is the source and the input of the inverter IN 5. The drain connected to the terminal and the first input
N-channel MO with gate connected to input terminal 5
An S transistor, Q26 is an N-channel MOS transistor having a drain connected to the source of the transistor Q25, a source connected to the ground potential point 12, and a gate connected to the output terminal of the inverter IN4. Q27 is a source and an inverter IN5. An N-channel MOS transistor having a drain connected to the input terminal and a gate connected to the selection signal input terminal 7, Q28 is a transistor Q2
7 is an N-channel MOS transistor having a drain connected to the source of No. 7, a source connected to the ground potential point 12, and a gate connected to the second input terminal 6.

P-channel MOS transistors Q21 and Q
22 and the N-channel MOS transistors Q25 and Q26 form a first gate circuit CR1 that controls passage of the data Din from the first input terminal 5 to the output terminal 4. In addition, P-channel MOS transistors Q23 and Q2
4 and N-channel MOS transistors Q27 and Q28 form a second gate circuit CR2 that controls passage of data Sin from the first input terminal 5 to the output terminal 4.

The gate width W _{p of the} transistor Q21 constituting the first gate circuit CR1 and the transistor Q22
Is the gate width W _p of which is set to the same value, the gate length L _p of the gate length L _p and the transistor Q22 of the transistor Q21 is set to the same value. Similarly, the transistors Q25 and Q26 have the same gate width W _n and the same gate length L _n , the transistors Q23 and Q24 have the same gate width W _p ′ and the same gate length L _p ′, and the transistors Q27 and Q28 have the same gate width W _p ′ and the gate length L _p ′. The gate width W _n 'and the gate length L _n ' are set to be the same.

Further, it is set so that Wp / Lp = Wn / Ln and Wp ′ / Lp ′ = Wn ′ / Ln ′. Furthermore, Wp / Lp> Wp '/ L
It is set to be p '. As described above, the size (gate width / gate length) of the transistor forming the second gate circuit CR 2 through which the test data S in passes.
The first gate circuit CR 1 through which the normal data D in passes
When the test data is prepared, the time for transmitting the test data between the DFF circuits connected in series by the MPX can be delayed by setting the size smaller than the size of the transistor configuring It is no longer necessary to insert a delay circuit between the DFF circuits that are provided. Even in the case of an IC with many DFF circuits, it is possible to suppress the increase in the number of elements and the chip size, and by suppressing the insertion of the delay circuit, it is possible to suppress the occurrence of timing errors after the layout and perform the layout correction work. it is possible to reduce the time <br/> to.

In order to secure a sufficient delay time in accordance with the time required for the DFF circuit to fetch data, the size of the transistor forming the second gate circuit CR 2 is set to the first gate. It is desirable to set the size to 1/2 or less of the size of the transistor that constitutes the circuit CR 1 .

Embodiment 2. Next, a scan test circuit according to a second embodiment of the present invention will be described with reference to FIG. MPX and D that make up the scan test circuit
The relationship between the FF circuit and the internal logic circuit is as shown in FIG. 3, as in the first embodiment.

FIG. 2 is a circuit diagram showing the structure of the MPX according to the second embodiment. In FIG. 2, IN6 is an inverter having an input terminal connected to the selection signal input terminal 7 of the MPX and an output terminal for outputting the negation of the signal received at the input terminal, and Q31 is connected to the output terminal of the inverter IN6. An N-channel MOS transistor having a gate and one current electrode connected to the first input terminal 5 of the MPX and the other current electrode connected to the output terminal 4 of the MPX, Q32 is a gate connected to the selection signal input terminal 7. And a P-channel MOS transistor having one current electrode connected to the first input terminal 5 and the other current electrode connected to the output terminal 4, Q33 is a gate connected to the selection signal input terminal 7 and the second of the MPX. An N-channel MOS transistor having one current electrode connected to the input terminal 6 and the other current electrode connected to the output terminal 4, Is a P-channel MOS transistor having a gate connected to the output terminal of the input terminal IN6, one current electrode connected to the second input terminal 6, and the other current electrode connected to the output terminal 4.

The P-channel MOS transistor Q32 and the N-channel MOS transistor Q31 form a transmission gate CR3 that controls passage of the data Din from the first input terminal 5 to the output terminal 4. The P-channel MOS transistor Q34 and the N-channel MOS transistor Q33 form a transmission gate CR4 that controls passage of the data Sin from the second input terminal 6 to the output terminal 4.

Wp / Lp of the transistor Q32 forming the transmission gate CR3 and Wn / Ln of the transistor Q31 are set to be the same, and Wp '/ Lp' of the transistor Q34 forming the transmission gate CR4 is set. W of transistor Q33
It is set so that n '/ Ln' is the same. Furthermore, it is set so that Wp / Lp> Wp '/ Lp'. As described above, the size (gate width / gate length) of the transistor forming the transmission gate CR 4 through which the test data S in passes is determined by the normal data D in
By setting the size smaller than the size of the transistor constituting the transmission gate CR 3 through which the test data passes, the time for transmitting the test data between the DFF circuits connected in series by the MPX is set when the test data is prepared. D can be delayed and connected in series
There is no need to insert a delay circuit between the FF circuits. DF
Even in the case of an IC with many F circuits, it is possible to suppress the increase in the number of elements and the chip size, and by suppressing the insertion of the delay circuit, it is possible to suppress the occurrence of timing errors after the layout and perform the layout correction work. it is possible to shorten the time it takes.

In order to secure a sufficient delay time according to the hold time of the DFF circuit, the size of the transistor forming the transmission gate CR 4 should be the same as the size of the transistor forming the transmission gate CR 3. It is desirable to set it to 1/2 or less.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a selection circuit in a scan test circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a selection circuit in a scan test circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional scan test circuit.

FIG. 4 is a circuit diagram showing a configuration of a selection circuit in a conventional scan test circuit.

FIG. 5 is a circuit diagram showing a configuration of another selection circuit in the conventional scan test circuit.

[Explanation of symbols]

1 ₁ to 1 ₃ selection circuit, 2 ₁ to 2 ₃ D flip-flop circuit, 3 an internal logic circuit, CR1 first gate circuit, C
R2 Second gate circuit, CR3, CR4 Transmission gate.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 63-263480 (JP, A) JP-A 2-152316 (JP, A) JP-A 2-154443 (JP, A) JP-A 2- 303066 (JP, A) JP 5-152443 (JP, A) JP 5-191220 (JP, A) JP 5-126917 (JP, A) JP 6-140890 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/28

Claims (2)

(57) [Claims] 1. A plurality of flip-flop circuits each having a data input terminal and a data output terminal connected to an internal logic circuit, and connected to the data output terminal of a corresponding one of the plurality of flip-flop circuits. Or a selection signal having a first input terminal to which test data is directly applied, a second input terminal for receiving normal data to be supplied to the internal logic circuit when not tested, a selection signal input terminal, and an output terminal. A plurality of selection circuits that selectively output the data received by the first or second input terminal from the output terminal in response to a selection signal input from an input terminal; A first gate circuit provided between a first input terminal and the output terminal for selectively passing data received at the first input terminal; and A second gate circuit provided between the second input terminal and the output terminal and selectively passing the data received at the second input terminal, the first gate circuit constituting the first gate circuit. Insulated gate field effect transistor gate
A first value obtained by dividing the width by the gate length is used for the second insulated gate field effect transistor forming the second gate circuit.
A scan test circuit, characterized in that it is smaller than a second value obtained by dividing the gate width by the gate length . 2. The first value is one half of the second value.
The scan test circuit according to claim 1, wherein: