JP2849007B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a self-test circuit formed in a chip, and more particularly to a large-scale semiconductor integrated circuit having a means for switching between a test mode and a normal mode and a means for selecting a test object. (LSI, the same applies hereinafter).

[0002]

2. Description of the Related Art In LSI, it is common to perform a function test of a chip-mounted block at the time of shipment or mounting. In addition, in order to facilitate the generation of a test pattern, a self-test circuit is formed by adding a multiplexer to the input / output side of a block in which failure detection is difficult, so that the block can be directly accessed from outside the chip.

FIG. 4 is a diagram showing the basic configuration of this type of self-test circuit. Reference numeral 10 denotes a first multiplexer, 11 denotes a block to be tested, 12 denotes another chip-mounted block, 13 denotes a second multiplexer, and 14 denotes an input. A buffer, 15 is a test buffer, 16 is an output buffer, and 17 is an external connection pin.

The first multiplexer 10 includes a normal mode signal (data signal) directly from outside the chip or from another block in the chip, and an input buffer 14.
, And a binary test switching signal derived from the test buffer 15.
One of the two mode signals is selected by the TST and input to the test target block 11. This test switching signal TS
T is also input to the second multiplexer 13, and the selection is switched in synchronization with the first multiplexer 10.

When the normal mode is selected, the output of the test target block 11 is guided to the external buffer 16 via the other block 12 and the second multiplexer 13. On the other hand, when the test mode is selected, the output of the test target block 11 is guided to the external buffer 16 via the second multiplexer 13. In the illustrated example, when the test switching signal TST is a “1” signal (High signal), the test mode is set to “0” (Lo).
(w signal), the mode is the normal mode.

[0006]

As described above, conventionally,
In order to facilitate test pattern generation, multiplexers 10 and 13 are added to the input / output side of the test target block 11 at a portion where failure detection is difficult to form a self-test circuit, and that portion can be directly accessed from outside the chip. I was However, in the self-test circuit having the above configuration, it is necessary to provide the pin 17 for inputting the test switching signal TST exclusively for the test, which is an overhead in LSI design. In particular, this is a very serious problem for products having a limited number of pins.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor integrated circuit having a configuration that does not require a dedicated test pin.

[0008]

According to the present invention, a system clock for managing the operation of a semiconductor integrated circuit is used for switching a test mode.
A data signal input from outside the chip was used for selecting a plurality of test target blocks.

[0009]

That is, according to the configuration of the present invention , a plurality of test target blocks, test target selecting means for selecting a specific test target block, and an operation mode of the selected test target block are set to one of a normal mode and a test mode. A semiconductor integrated circuit formed in a chip by a self-test circuit having mode switching means for switching to one side,
The test target selecting means includes a signal generation circuit that generates a reset signal that becomes active when power is turned on, a reset signal as a clock input, an externally input system clock as a data input, and a system clock level at the time of the reset signal input. A flip-flop that outputs a corresponding binary signal, and an address output corresponding to a specific test target block is made active by a combination of at least two external data signals, and a logical operation is performed between the activated address output and the flip-flop output Selected by
The selected block to be tested into test mode.
Select block test switching signal, and
A mode switching means for inputting a normal mode signal and a test mode signal and outputting one of the input signals to a plurality of test circuits.
It is output so that it can be switched for each block to be tested,
Selected block for the selected test target block
A multiplexer for outputting a test mode signal based on the test switching signal .

[0011]

The output level of the F / F is determined by the system clock level when the reset signal output from the signal generation circuit is input. Since this reset signal becomes active only when the power is turned on, the output level of the F / F is continued until the next reset signal becomes active.

[0012]

By inputting at least two external data signals to the matrix circuit, an address corresponding to a specific test target block is made active, and further, a logical operation of the active address and the F / F output is performed.
By doing so, the output of the multiplexer for the test target block is switched. Therefore, even when a plurality of test target blocks are formed, the function test of each block can be performed.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
4 shows an example of an input-side configuration of a self-test circuit. It is assumed that a plurality of test target blocks and a multiplexer for switching the input are formed in the chip.

In this embodiment, in order to switch the mode of a specific test target block 11 (conventional product), a self-test circuit including a power-on reset circuit 1, an F / F 2, a matrix circuit 3, and a multiplexer 4 is configured. . Reference numeral 17 denotes an external connection pin (a component having the same function as that of the related art), which guides external signals such as a system clock and external data into the chip via buffers. Further, a test signal and a normal signal are input to the multiplexer 4 as in the conventional circuit.

The power-on reset circuit 1 has a power-on reset signal (hereinafter, referred to as a single pulse) when the power is turned on.
A reset signal is generated, and the reset signal is guided to a clock input terminal of an F / F2 (D-type F / F, the same applies hereinafter). The system clock used as the clock of the on-chip circuit is branched and input to the data input terminal of the F / F2. This system clock is composed of a binary level pulse train, and its arrangement can be arbitrarily changed from outside the chip. In such a configuration, F / F2
Is determined by the system clock level when the reset signal is input. Since the reset signal becomes active only when the power is turned on, the output level of the F / F 2 is continued until the next reset signal becomes active. In this embodiment, the output of this F / F2 is used as a test switching signal.
Used as TST1.

The matrix circuit 3 specifies one block from a plurality of blocks to be tested, and selects a block for switching the test mode of the specified block.
A circuit for generating a Kkutesuto switching signal SEL. The specific configuration, for example, as shown in FIG. 2, and the decoder 21 having an address corresponding to a particular block under test by branching enter at least two external data signals (not shown) active, and active AND gate which takes the logical product of the changed address and the test switching signal TST1
Address that has become active.
Is changed by the test switching signal TST1 to the matrix circuit 3
And outputs the selected block test switching signal SEL.
Select block test output from matrix circuit 3
Conversion signal SEL is led to the multiplexer 4, the output switching is performed.

The above is an example of a configuration in which a plurality of blocks to be tested are formed. In the case of a single block, the matrix circuit 3 is not necessarily required. At this time, the output TST1 of the F / F 2 is directly guided to the multiplexer 4.

FIGS. 3A and 3B are operation timing diagrams according to the above-described configuration. FIG. 3A shows an example in which a test mode is selected, and FIG. Referring to these figures, by switching the system clock level at the time of activation of the power-on reset circuit 1 to one of the binary levels, the binary level of the test switching signal TST1 corresponds to the binary level. It has become. That is,
As shown in FIG. 3A, by setting the system clock level to “High” when the power is turned on, the entire chip enters the test mode. On the other hand, as shown in FIG. Set the system clock level to "Low"
By doing so, the entire chip can be operated in the normal mode.

Therefore, by switching the output of the multiplexer 4 using the test switching signal TST1, it is possible to switch between the test mode and the normal mode without providing a dedicated test pin.

In this embodiment, the test switching signal TST1
Although a D-type F / F is used as the F / F for outputting, the other type of F / F having the same function can of course be used instead.

[0023]

As described above, according to the present invention, a signal generation circuit is formed inside a chip, a reset signal is input as a clock, and a system clock is used as a data input. Since the switching is performed, it is possible to switch the test mode without increasing the number of dedicated test pins as in the related art. In the case of a semiconductor integrated circuit, the addition of an electronic circuit is extremely easy and inexpensive, but it is extremely difficult to reduce the number of pins in terms of both technology and cost. There is something.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a self-test circuit in an LSI according to an embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a matrix circuit used in the present embodiment.

3A is a diagram illustrating an operation timing when a test mode is selected according to the present embodiment, and FIG. 3B is a diagram illustrating an operation timing when a normal mode is selected.

FIG. 4 is a basic configuration diagram of a conventional self-test circuit in LSI.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Power-on reset circuit (signal generation circuit), 2 ... Flip-flop, 3 ... Matrix circuit, 4,10,13
... Multiplexer, 11 ... Test target block 17 ... External connection pins.

Claims (1)

(57) [Claims] 1. A plurality of test target blocks, a test target selecting unit for selecting a specific test target block, and a mode switching unit for switching an operation mode of the selected test target block to one of a normal mode and a test mode. A self-test circuit having a self-test circuit formed in a chip, wherein the test target selecting means generates a reset signal that becomes active when power is turned on, and inputs a clock to the reset signal. And a flip-flop that outputs a binary signal corresponding to the system clock level when the reset signal is input, and a specific test block by a combination of at least two external data signals. Make the corresponding address output active and The selected tape by logical operation of the flip-flop output is the address output
Select block to set test block to test mode
A clock test switching signal, and the mode switching means
A mode circuit for inputting a normal mode signal and a test mode signal, and outputting one of these input signals to the plurality of test circuits.
The output is switchable for each target block.
For the selected test target block,
The test mode signal based on the lock test switching signal
A semiconductor integrated circuit, comprising: a multiplexer that outputs a signal.