JPH06201794A - Test circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To realize a multifunctional test mode without using a plurality of test terminals. CONSTITUTION:Data values are set up in a test register 4 through a data bus 5, and the output of the test register 4 is decoded by a decoder 9 to generate a plurality of testenable signals 10 for realizing a multifunctional test mode. In this case, a test terminal 6 is only one, and the data are taken in the test register 4 through a signal in which the test signal and a light signal at a light terminal 7 are gated. The generated testenable signals 10 are 2n pieces when the number of registers is regarded as (n).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test circuit.

[0002]

2. Description of the Related Art In recent years, the number of pins, the number of functions, and the degree of integration of semiconductor devices have been remarkably increased. On the other hand, as the functionality becomes higher, the test method becomes more complicated, and a plurality of dedicated terminals are required to improve the test efficiency.

FIG. 2 is a test circuit diagram of a conventional semiconductor device. As shown in FIG. 2, when n dedicated test terminals 1 are provided, the signals TEST1 to TEST of the test terminals 1 are transmitted.
The combination of n enables the decoder 2 to set 2n test modes. Signal TES of test terminal 1
Depending on the combination of T1 to TESTn, any of the test enable signals 3 becomes active via the decoder 2. This signal is used as a control signal for multiplexing or the like to test the signal between the mega cells closed inside the semiconductor device.

[0004]

When testing a high-performance semiconductor device in this manner, it is considered that at least two or more test terminals are required, and the waste of the number of pins described above cannot be tolerated. From the recent situation, they tend to conflict with each other.

The present invention solves the above problems and provides a test circuit for a semiconductor device which does not require a plurality of test terminals.

[0006]

In order to achieve the above object, the present invention has a function of providing a test register in a semiconductor device and passing a decoder with the value of the test register to generate a test enable signal. The value of the data bus is used as the data of the test register, so that it can be set only when the test pin is enabled.
A signal obtained by gating the write signal and the test signal is used as the gate signal of the test register.

That is, the test circuit of the semiconductor device of the present invention has a plurality of megacells, and the signal lines connected between these megacells without going out of the chip, and the signal lines are connected to the outside of the semiconductor device. It has a multiplex and a test terminal to control it so that it can be inspected by.

[0008]

According to the present invention, the data bus value is used as the data of the test register and the test enable signal is generated through the decoder in accordance with the number of registers, so that a large number of test terminals for gates are used. The mode can be set.

[0009]

1 is a test circuit diagram of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, 4 is a test register composed of a plurality of registers, 5 is a data bus connected to the data terminal of the test register 4, 6 is a test terminal, 7 is a write terminal, 8 is a test terminal 6 and a write terminal. A gate circuit having 7 as an input, 9 a decoder having an output signal of the test register 4 as an input, and 10 a test enable signal generated by decoding the output signal of the test register 4 at the output of the decoder 9.

Test register 4 via data bus 5
Set the data values D ₀ , ..., D _n to the test register 4
The decoder 9 decodes the output of 1 to generate a plurality of test enable signals 10 and realize a multifunctional test mode. At that time, the number of test terminals 6 is one, and the test signal TEST from the test terminal 6 and the write signal NWR from the write terminal 7 are gated by the gate circuit 8. The data values D ₀ , ..., D _n are taken in through. The generated test enable signal 10 is 2n when the number of registers in the test register 4 is n.
That is, it is possible to set 2n different test modes.

[0012]

According to the test circuit of the semiconductor device of the present invention, it is sufficient that the test terminal inputs the test-triggering signal and does not need a plurality of test terminals, but only one. In addition, a number of test modes corresponding to the number of registers in the test register can be realized, and a multi-function test can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a test circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of a test circuit of a conventional semiconductor device.

[Explanation of symbols]

 1 Test Terminal 2 Decoder 3 Test Enable Signal 4 Test Register 5 Data Bus 6 Test Terminal 7 Write Terminal 8 Gate Circuit 9 Decoder 10 Test Enable Signal

Claims (1)

[Claims] 1. A test register composed of a plurality of registers, to which data is input via a data bus, a decoder for decoding an output of the test register to generate a test enable signal, and a test signal to be input. A test circuit for a semiconductor device, comprising: a test terminal for setting that the test register is in a testable state.