KR100396789B1 - Function change circuit for semiconductor memory device - Google Patents

Abstract

The present invention relates to a circuit for changing a function of a semiconductor memory device, and in particular, to perform analysis and product verification of the device through a test mode after fabricating the semiconductor memory device to shorten the analysis and test time of the device as compared to the conventional method. There is a purpose. According to the present invention for this purpose, the test mode signals T1 to Tn, the clock TCLK, and the reset signal TRST are calculated by calculating the address ADDR, the address strobe signals RASB and CASB, and the control signals CSB and WEB. A test mode decoder 310 for outputting, a counter 320 for counting the clock TCLK, outputting the count signals Q1 to Q3, and clearing a count value by the reset signal TRST; The logic gate unit 330 selects and inputs one of the input signals Vi31 to Vi33 according to the output signal of the counter 320.

Description

FUNCTION CHANGE CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and in particular, to a function change circuit.

As shown in the circuit diagram of FIG. 1, a conventional fuse option circuit includes a metal switch 110 for selecting a ground voltage Vss or an operating voltage VPERI, an input signal Vi1, and the metal switch 110. And a NAND gate 120 for outputting the output of the NAND gate, and an inverter 130 for outputting the final output signal Vo1 by inverting the output of the NAND gate 120.

Referring to the operation of the embodiment of the prior art as follows.

When the switch 110 is connected to the ground voltage Vss, the NAND gate 120 always outputs a high signal regardless of the level of the input signal Vi1.

Therefore, the output signal Vo1 of the inverter 130 is always maintained at a low level.

When the switch 110 is connected to the operating voltage Vperi, the level of the output signal of the NAND gate 120 is determined according to the level of the input signal Vi1.

Therefore, the output signal Vo1 level in the inverter 130 inverting the output signal of the NAND gate 120 is output at the same level as the input signal Vi1.

That is, in the case of the metal option, which is an embodiment of the prior art, the function of the circuit is determined by modifying the metal layer through a layout operation according to a situation.

Figure 2 also shows the case of a fuse option as another embodiment of the prior art.

That is, another embodiment of the prior art applies an NMOS transistor in which a ground voltage Vss is applied to a gate of a PMOS transistor MP1 to which an operating voltage Vperi is applied to a source, and a source is connected to a ground voltage Vss. The inverter 210 applies an initialization signal INT to the gate of the MN1 and connects a connection point between the other terminal of the fuse F1 connected to the drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1. Is connected to the drain of the NMOS transistor MN2 having an input terminal and a source grounded thereto, and the output terminal of the inverter 210 is connected to the gate of the NMOS transistor MN2, and an input signal Vi2 is supplied to one input terminal. ) Is connected to the other input terminal of the NAND gate 220 to which the NAND gate 220 is applied, and the output terminal of the NAND gate 220 is connected to the input terminal of the inverter 230 to output the signal Vo2 from the inverter 230. do.

Referring to the waveform diagram of FIG. 3, an operation process of another embodiment of the related art is as follows.

First, when the fuse F1 is connected, when the initialization signal INT1 becomes a high pulse, the NMOS transistor MN1 is turned on so that the potential of the node N1 becomes low as shown in FIG. 3 (b). As the inverter 210 inverts the level signal, the potential of the node N2 becomes high as shown in FIG. 3 (c).

Subsequently, when the initialization signal INT transitions to the low level, the PMOS transistor MP1 is turned on by the ground voltage Vss, and the potential of the node N1 becomes high level. ) Is at the low level.

Accordingly, since the NAND gate 220 outputs a high signal regardless of the level of the input signal Vi2, the inverter 230 maintains the output signal Vo2 at a low level at all times.

That is, the above operation performs the same function as when the switch 110 is connected to the ground voltage Vss in FIG.

On the contrary, when the fuse F1 is blown, as shown in FIG. 3A, when the initialization signal INT becomes high level, the potential of the node N1 becomes low level and the node N2 is inverted by the inverter 210. The level of becomes high level.

Thereafter, even when the initialization signal INT is at a low level, the operating voltage Vperi is not applied to the node N1 and the NMOS transistor MN2 remains turned on by the high signal from the inverter 210. The potential of N1 is always kept at a low level as shown in Fig. 3 (d), and the potential of node N2 is always kept at a high level as shown in Fig. 3 (e).

Therefore, since the output signal at the AND gate 220 is determined by the level of the input signal Vi2, the output signal Vo2 at the inverter 230 is output at the same level as the input signal Vi2.

That is, the above operation performs the same function as when the switch 110 is connected to the operating voltage Vperi in FIG. 1.

In other words, the fuse option, which is another embodiment of the prior art, is a method of changing the function of the circuit by cutting off the fuse F1 after the device is manufactured without the need for layout work.

However, the prior art has to modify the metal layer or cut the fuse to change the circuit function of the semiconductor device.

In particular, one embodiment of the prior art is to re-fabricate the semiconductor device when modifying the metal layer, another embodiment is not applicable to the product once packaged when the fuse is cut.

Therefore, the conventional technology has a problem in that a large amount of time is required when a function change of a circuit is required during analysis or testing of a semiconductor device.

Accordingly, an object of the present invention is to provide a function change circuit of a semiconductor device invented to perform analysis and product verification of the device through a test mode after fabricating the semiconductor memory device to improve the conventional problems.

That is, the present invention repeatedly inputs the test mode entry key address used in the test mode, changes the value of the internal register according to the number of times, and changes the internal function or adjusts the set value according to the value. The analysis and test time of the semiconductor memory device can be shortened as compared with the logic function change or the setting value change method through the modification of wiring.

1 is a circuit diagram for a metal option in one conventional embodiment.

2 is a circuit diagram for a fuse option in another conventional embodiment.

3 is a waveform diagram of each part according to whether a fuse is cut in FIG.

4 is a circuit diagram for an embodiment of the present invention.

FIG. 5 is a waveform diagram of each part in FIG. 4; FIG.

Explanation of symbols on the main parts of the drawings

310: test mode decoder unit 320: counter unit

321 to 323: flip-flop 330: logic gate portion

331 to 333 NAND gates 334 to 336 Inverters

In order to achieve the above object, the present invention provides a test circuit of a semiconductor memory device for analyzing and testing a semiconductor memory device, in which a fabrication process is completed, by combining a test mode command, that is, a control signal of an external input, with a test mode signal and a clock. A test mode decoder unit for outputting a signal, a counter unit for counting the clock signal to designate an internal setting value, and selecting and inputting an input signal corresponding to a currently determined test mode among a plurality of input signals according to the internal setting value Characterized in that it comprises a logic gate portion to make.

In addition, in the present invention, the counter unit may be configured by replacing the register unit to directly store internal setting values.

Hereinafter, the present invention will be described in detail with reference to the drawings.

Fig. 4 is a block diagram of an apparatus according to an embodiment of the present invention, as shown here, which calculates an address ADDR, an address strobe signal RABB, CASB, and a control signal CSB, WEB, and a test mode signal T1. Tn, a test mode decoder 310 for outputting the clock TCLK and the reset signal TRST, and counting the clock TCLK and outputting the count signals Q1 to Q3 to output the reset signal TRST. The logic unit which selects and inputs one of a plurality of input signals Vi31 to Vi33 according to the counter unit 320 that clears the coefficient value by means of an output signal (Q1 to Q3) of the counter unit 320. It consists of a part 330.

The counter 320 connects the output terminal Q1 of the flip-flop 321 to which the clock TCLK is applied to the clock terminal to the clock terminal of the flip-flop 322, and outputs the output terminal (of the flip-flop 322). Q2) is connected to the clock terminal of the flip-flop 323 to generate the output signal Q3 from the flip-flop 323, and the reset signal TRST is commonly applied to the cree terminals of the flip-flops 321 to 323. Configure.

The logic gate unit 330 includes NAND gates 331 to 333 to NAND each of the output signals Q1 to Q3 and the input signals Vi31 to Vi33 of the counter unit 320, and the NAND gates 331 to 333. Are inverted, respectively, and inverters 334 to 336 which generate the final output signals Vo31 to Vo33, respectively.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

Typically, a memory device is fabricated and then tested to verify and validate the device through a test mode.

First, when testing a memory device, the test mode decoder 310 calculates an address ADDR, an address strobe signal RABB, CASB, and a control signal CSB, WEB to determine which test mode to proceed. The test mode signals T1 to T3 are output, and the clock signal TCLK and the reset signal TRST are simultaneously output.

Here, the two signals TCLK and TRST generated by the address ADDR become high pulses each time the test mode entry commands CSB, WEB, RASB, and CASB are applied.

At this time, when the clock TCLK as shown in FIG. 5 (a) is input, the counter 320 operates the flip-flop 321 at each rising edge of the clock TCLK to divide the divided signal as shown in FIG. 5 (c). Q1) and the flip-flop 322 is operated at each rising edge of the division signal Q1 to generate the divided signal Q2 as shown in FIG. 5 (d), and the flip-flop 323 generates the division signal Q2. It is operated for each rising edge of Δ) to generate a divided signal Q3 as shown in FIG.

Here, since the driving of the flip-flops 321 to 323 included in the counter 320 can be adjusted according to the number of test mode entry commands CSB, WEB, RASB, and CASB from the outside, it is stored in the counter 320. Can be changed.

As a result, the logic gate unit 330 applies each of the input signals Vi31 to Vi33 to each of the output signals Q1 to Q3 of the counter 320 and the NAND gates 331 to 333, and then the NAND gate ( Inverting the output signals 331 to 333 of the inverters 334 to 336 generates the final output signals Vo31 to Vo33, which are generated by the output signals Q1 to Q3 of the counter unit 320. The signals Vi31 to Vi33 input to the gates 331 to 333 can be selected.

After that, when the address ADDR is input, the test mode decoder 310 outputs the reset signal TRST as a high pulse, so that the flip-flops 321 to 323 provided in the counter 320 are cleared and the count value ( Q1 to Q3) are initialized.

That is, the logic gate part 330 of the input signals Vi31 to Vi33 is changed by changing the values Q1 to Q3 stored in the counter part 320 according to the number of test mode entry commands CSB, WEB, RASB, and CASB externally. You can select the signal to be input.

Accordingly, the present invention may replace the functions of the metal option of FIG. 1 and the fuse option of FIG.

For example, tRWL = 1clk or 2clk adjustment, self-refresh frequency adjustment, etc. by the conventional fuse option may be replaced.

On the other hand, the counter 320 is implemented as a down counter to reduce the count value (Q1 ~ Q3) according to the number of pulses of the clock (TCLK), but on the contrary, it is implemented as an up counter to count values (Q1 ~ Q3) ) Can be increased.

In addition, the present invention may be configured to directly store a coefficient value by using an address ADDR which is implemented as a register instead of the counter 320 and is not used in a test mode entry coding command.

As described in detail above, the present invention can change the option of the internal circuit by setting the test mode after packaging of the semiconductor memory device, thereby reducing the development time through analysis or testing of the semiconductor device.

Claims (3)

In the test circuit for the analysis and testing of the semiconductor memory device is completed manufacturing process, A test mode decoder for outputting a test mode signal and a clock signal by combining control signals of an external input; A counter unit for counting a clock of the test mode decoder unit to calculate an internal setting value and clearing the internal setting value by a reset signal of the test mode decoder unit; And a logic gate unit for selecting one input signal corresponding to the test mode determined by the test mode decoder unit among a plurality of input signals according to an internal setting value of the counter unit. The function change circuit of claim 1, wherein the test mode decoder unit is configured to output a clock pulse each time a test mode command is input and output a reset signal for a predetermined time by a test mode address. In the test circuit for the analysis and testing of the semiconductor memory device is completed manufacturing process, A test mode decoder for outputting a test mode signal and a clock signal by combining control signals of an external input; A register for storing internal setting values according to external addresses; And a logic gate section for selecting one of a plurality of input signals in accordance with an internal setting value of the register section so as to conform to the test mode determined by the test mode decoder.