JPS6180068A - Test signal generation circuit - Google Patents

Abstract

PURPOSE:To make it possible to forcibly generate a test signal from the outside only at the time of testing without impairing the function at the time of usual operation, by using an output port having function to be originally achieved at the time of usual operation and a test terminal in common. CONSTITUTION:At the time of the usual operation of a semiconductor integrated circuit, the input signal 1 supplied from an internal circuit to a same phase type output buffer and the output signal 6 obtained by inverting an output signal by an inverter 5 always have the relation of an inverse phase and no test signal 8 is generated from an AND gate 7. When the signal with logical zero generated from a driver having driving capacity sufficiently larger than that of the output buffer 2 is forcibly applied to a terminal 4 in such a state that a reset signal is applied at the start time of a test and the signal 1 is set to logical 1, the output of the inverter 5 comes to a high level. Therefore, the input signal of the AND gate 7 is also 1 and AND logic can be taken, the test signal 8 comes to an active state and the start of test operation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a test signal generation circuit that generates a test signal to be generated when testing a semiconductor integrated circuit or the like.

(Prior Art) When manufacturing semiconductor integrated circuits equipped with microcombiners, microcontrollers, etc., rigorous tests are conducted to ensure that the internal circuits operate normally. In order to improve the defect detection rate and test efficiency in this case, a semiconductor integrated circuit is often equipped with eight test circuits, and during the test, the VC is tested in a special operation mode different from the normal operation. Therefore, in order to distinguish between normal operation and operation during a test, a test terminal is specially provided, and a signal is applied from this test terminal to cause the test circuit to switch between active during testing and inactive during normal operation in many cases. However, with this method, when the semiconductor integrated circuit is used for normal operation, it is necessary to secure extra terminals that are completely meaningless. In recent years, as the performance of microcombi devices has improved, the number of sophisticated ports that microcombi devices have to interface with the outside has tended to increase, and one pin is exclusively used as a test terminal. This is a serious drawback in effectively utilizing the limited number of nine terminals.

(Purpose of the Invention) The present invention has been made in view of the above points, and is designed to share a terminal with an output board that has a function that should be performed during normal operation, and to be forced from the outside only during testing without impairing the function during normal operation. An object of the present invention is to provide a test signal generation circuit that generates a test signal automatically.

(Structure of the Invention) A test signal generation circuit of the present invention is an electronic circuit incorporating an in-phase output circuit having a function of deriving an input signal in phase to an output terminal as an output signal. t or output signal) and the output signal (
The circuit is constructed by including a gate circuit which inputs an inverted signal of the input signal (input signal) and supplies the test signal internally only when the entire external test signal is applied to the output terminal. It can also be configured as a 7'Cd Noah gate.

(Example〕 The present invention will be described in detail below using the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The signal 1 generated in the semiconductor integrated circuit circle is connected to the in-phase type output cover, NOR 2, and is also connected to the two-manufactured AND gate 7.
connected to the input of The output signal 3 of the in-phase output buffer 2 is connected to the output terminal 4 of the semiconductor integrated circuit and also to the input of the inverter 5. Connected.t
The output signal of the two-manual AND gate 7 is supplied as a test signal 8 to the internal gate of the semiconductor integrated circuit.

Next, the operation will be explained separately during normal use and during testing. During normal operation of a semiconductor integrated circuit, the input signal 1 supplied from the internal circuit to the common-mode output buffer 2 and the output signal of the common-mode output buffer 2 is inverted by the inverter 5, and the next output signal 6 is always in an opposite phase relationship. Since the human input signal 1 and the output signal 6 are supplied to the AND gate 7, the AND logic cannot be established, and the output signal of the AND gate 7, that is, the test signal 6, cannot be in the active state. Since the test signal 8 is not generated, it is possible to continue normal operation without being drawn into a test operation state during normal operation.

Next, the test operating state will be explained.

Generally, in a semiconductor integrated circuit, a reset signal is applied from a separately provided reset input terminal that initializes the internal circuitry installed when the power is turned on or when a test is started. At this time, of course, the ninth output port that interfaces with the outside must be set to a predetermined state, and for convenience, the signal l supplied from the internal circuit must be set to a logical 1.
``Therefore, the output signal of the in-phase output buffer 7 is also 1'', and
Since '1'' is input to inverter 5, its output is '
Assume that it is "0". In this state, if a logical ``0'' signal generated from a driver such as an LSI tester with a sufficiently large driving capacity (low signal impedance) is forcibly applied to the terminal 4, the in-phase The “1#” (no-hey-repel) signal output from the output cover and NOOR 2 and the ’O” (low level) signal applied from the outside will collide, but the signal level at that time is determined by the ratio of their signal impedances. Ninth, since the low level applied from the outside overcomes the high level output from the in-phase output buffer 2 and becomes the low level,
The output of the inverter 5 becomes no-repel. Therefore, the signals 1 and 6 input to the AND gate 7 are both l'lt#, and since the AND logic can be taken, the test signal 8 is Iii'
@ It becomes possible to start the next state strike operation in the moving state.

Figure wc2 is a circuit diagram of a second embodiment of the present invention, and the difference from the embodiment shown in Figure 1 is the AND gate 7 in Figure 1.
When the signal 1 supplied from the reset input/input application common gate circuit is '0', and therefore the output signal of the common mode output buffer is '0', the external This is to realize the operation of forcibly outputting the test signal 1 (l) to the NOR gate 9 and generating the test mode.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. The difference from the embodiment shown in FIG.
This is only the part that is directly input to the external power of the AND gate 7.

FIG. 4 is a circuit diagram of a fourth embodiment of the present invention, which differs from the embodiment shown in FIG. This is only the part that is directly input to the external power of 1) 7 gates 9.

The basic operation of the embodiment shown in FIGS. 2 to 4 is the same as that of the embodiment shown in FIG. 1, and a detailed explanation thereof will be omitted.

(Effects of the Invention) As is clear from the above explanation, according to the test signal generation circuit of the present invention, a test operation state can be generated in an electronic circuit by simply adding a simple circuit, and there is no need to provide an independent test terminal. Therefore, it is possible to make effective use of a limited number of terminals, which has a large effect.

[Brief explanation of the drawing]

1 to 4 are a circuit diagram of a first embodiment, a second embodiment, a third embodiment, and a fourth embodiment of the present invention, respectively. 1... Signals generated inside the semiconductor integrated circuit, 2
・・・・・・In-phase type output cover, Noah, 3・・・・・・In-phase type output cover. Noah's output signal, 4...Semiconductor integrated circuit terminal, 5.11...In 7(-/, 6.12・mountain・
・Inverter output signal, 7...Two-person gate, 8゜10...Test signal, 9...
・Two person Kaagate. Figure 2 Figure 4

Claims (3)

[Claims] (1) In an electronic circuit incorporating an in-phase output circuit that has a function of deriving an input signal in phase to an output terminal as an output signal, the in-phase signal and the output signal of the input signal (or output signal) of the in-phase output circuit 1. A test signal generating circuit comprising a gate circuit which inputs an inverted signal of (or an input signal) and supplies a test signal internally only when an external test signal is applied to the output terminal from the outside. (2) The test signal generating circuit according to claim (1), wherein the gate circuit is an AND gate. (3) The test signal generation circuit according to claim (1), wherein the gate circuit is a NOR gate.