JPH0225109A - Lsi - Google Patents

Abstract

PURPOSE:To eliminate the need for an external mounted circuit to make the polarity of signal coincident with that of an external circuit and to reduce number of externally mounted components by incorporating an input buffer and an output buffer whose polarity is to be set freely to an LSI. CONSTITUTION:A signal inputted to an input terminal 6 is used in the inside of an LSI 1 as an output signal 21 through an input buffer 2. In this case, since the buffer 2 is constituted as an exclusive OR circuit, when an output signal 41 of a register 4 is logical '0' the logical value of the signal given to the terminal 6 is outputted as it is as an output signal 21 of the buffer 2. When the output signal 41 of the register 4 is logical '1', the logical value of the signal given to the input terminal 6 is inverted and outputted as the output signal 21 of the buffer 2. Thus, an externally mounted circuit to make the signal polarity coincident with that of an external circuit 6 is not required and number of externally mounted components is decreased.

Description

[Detailed Description of the Invention] The present invention is an LSI (Large 5cal In
The present invention relates to LSI used in information processing devices and the like.

Conventionally, this type of LSI has been configured to include a logic circuit and an input/output (interface) circuit that is provided around the logic circuit and sends and receives input/output signals between the logic circuit and external circuits. Ta. The input/output circuit consisted of a drive circuit, a negative circuit (inverter), and the like.

However, in the conventional LSI input/output circuit described above, the input/output polarity is determined at the time of LSI design.
After the LSI was completed, there were cases where the signal inertia did not match with other LSIs or external circuits. Therefore, in order to match the signal polarity, an external circuit such as a negative circuit is required, which has the drawback of increasing the number of parts and M4 time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an LSI that does not require an external circuit for matching signal polarity with an external circuit.

Structure of the Invention The LSI of the present invention includes a logic circuit and its surroundings,
An LSI comprising an interface circuit for transmitting and receiving input/output information between the logic circuit and an external circuit, the interface circuit having a memory means that can be rewritten from the outside, and a memory means in which the information stored in the memory means is in a first state. and transmitting means for transmitting an inverted value of the input information as output information when the storage means indicates a second state, and transmitting a non-inverted value of the input information as output information when the stored information in the storage means indicates a second state. shall be.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an LSI according to the present invention. In FIG. an output buffer 3 consisting of an logical OR circuit, and a register 4 for setting the polarity of the input signal.
, a register 5 that sets the polarity of the output signal, an input terminal 6 connected to one input of the input buffer 2, an output terminal 7 connected to the output of the output buffer 3, and registers 4 and 5. On the other hand, it is configured to include a shift input terminal 8 for inputting data by a shift operation. In this embodiment, for the sake of simplicity, a case will be described in which there is only one input signal and one output signal.

It is possible to configure the input buffer 2 and output buffer 3 of the LSII by exclusive OR circuits using well-known techniques. Further, the shift input terminal 8 is conventionally provided for the well-known scan path test in which the LSI is tested by connecting the registers in the LSII like a shift register.

In such a configuration, the signal input to the input terminal 6 is
It is used inside the LSII as an output signal 21 through an input buffer 2. In this case, input buffer 2
is constituted by an exclusive OR circuit, so when the output signal 41 of the register 4 has a logical value of "0", the logical value of the signal input to the input terminal 6 is directly used as the output signal 21 of the manual buffer. is output as Further, when the output signal 41 of the register 4 has the logical value rl, the logical value of the signal input to the input terminal 6 is inverted and output as the output signal 21 of the input buffer.

On the other hand, the input signal 31 of the output buffer 3 is outputted to the output terminal 7 through the output buffer 3. In this case, since the output buffer 3 is also composed of an exclusive OR circuit like the input buffer 2, the output signal 5 of the register 5
When 1 is the logical value "0", the logic f1a of the input signal 31 of the output buffer 3 is outputted to the output terminal 7 as is (that is, a non-inverted value). Also, the output signal 5 of register 5
When 1 is the logical value “1”, the logical value of the input signal 31 of the output buffer 3 is inverted and outputted to the output terminal 7.

Here, arbitrary values can be set in the registers 4 and 5 via the shift input terminal 8.

Therefore, by setting arbitrary values in the registers 4 and 5, it is possible to freely set the polarity of the input terminal 6 and output terminal 7 of the LSII. This eliminates the need for an external circuit such as a negative circuit.

As explained above, the present invention eliminates the need for an external circuit to match the signal polarity with an external circuit by incorporating an input buffer and an output buffer into the LSI that can freely set the polarity. Therefore, external attachment has the effect of reducing the number of parts and preventing an increase in delay time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an LSI according to an embodiment of the present invention. Explanation of symbols of main parts 1...LSI 2...Input buffer 3...Output buffer 45...Register

Claims (1)

[Claims] (1) An LSI having a logic circuit and an interface circuit provided around the logic circuit for transmitting and receiving input/output information between the logic circuit and an external circuit, the interface circuit having an externally rewritable storage means. , when the information stored in the storage means indicates the first state, the inverted value of the input information is sent as output information, and the information stored in the storage means is in the second state.
and sending means for sending out a non-inverted value of input information as output information when the state of
.