JPS59211317A - Flip-flop - Google Patents

Abstract

PURPOSE:To attain the initial value setting in high speed in constituting a shift register by providing a signal path where it is brought in the through-state from a data input terminal to a data output terminal. CONSTITUTION:A latch circuit comprising transmission gates 21, 22 and inverters 31, 32 and a latch circuit comprising transmission gates 23, 24 and inverters 33, 34 are controlled by a clock signal from a terminal 11 at the steady-state thereby allowing an input signal from a terminal 10 to be transmitted to a terminal 13. Transmission gates 25, 26 bypasses the transmission gates 21, 23 by receiving a signal from a terminal 12 at the initial value setting so that the input signal is transmitted to the terminal 13 independently of the clock signal. Since the input value to the terminal 10 is transmitted to the final stage as it is in constituting the shift register, the initial value setting is executed in high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to the structure of a D-type flip-flop used in an integrated circuit.

(2) Prior Art Conventionally, when a multi-stage shift 1/registor is constructed using this type of flip-flop and housed in a large-scale integrated circuit, it is necessary to determine the value of each flip-flop in order to test the integrated circuit. The following method was used.

The first method is to determine the first input of the multi-stage shift register, input a pulse indicating the number of stages of the shift register, and initialize all shift 1 registers, so that the initial values of all flip-flops are Shift until confirmed] / Requires clock pulses equal to the number of register stages,
There is a drawback that it takes a long time to complete the initial settings.

The second method is to use the VC terminal for this initial setting, but if the set or reset function is required for operations other than the initial setting, the VC-
has the disadvantage of requiring logical processing.

The third method is to provide a flip-flop with input terminals for the first and second clock phases, use these two as input terminals of the integrated circuit, and simultaneously turn on the transmission gates in the flip-flop from the outside to control the flip-flop. There is a method of passing the initial value to the final stage by passing the loop from input to output, but this requires careful consideration of the load capacity of the two wires used as a clock inside the integrated circuit. This has the disadvantage of requiring two clock input terminals.

(3) Purpose of the Invention The present invention is based on the trap of providing a through-signal path from the data input terminal to the output terminal completely independently of the clock signal in a configuration in which a D-type flip 70 horn is used as a multi-stage shift register. The object of the present invention is to provide a flip-flop that eliminates the above drawbacks.

(4) Structure of the Invention According to the present invention, it has one data input terminal, one input terminal, and one company period setting signal input terminal,
It has a first inverter for inverting the first clock phase to obtain a second clock phase when the first clock phase is the signal of the clock input terminal, and the first inverter receives the take input signal as an input and outputs the first clock. a first transmission gate that is switched in phase; a second inverter that receives the output signal of the first transmission gate; a third inverter that receives the second inverter output signal; a second transmission gate which receives the output signal as an input and whose output is connected to the first transmission gate output and is switched at a second clock phase; a third transmission gate switched by a third transmission gate;
a fourth inverter that receives the output signal of the transmission gate as input; a fifth inverter that receives the fourth inverter output signal as input; and a fifth inverter that receives the fifth inverter output signal and whose output is the third transmission gate output. A MOS consisting of a fourth transmission gate connected and switched at the first clock phase.
) In a flip-flop that relies on transistors, the first transmission gate and the input/output are connected in parallel, and the fifth transmission gate is switched by a signal from the initialization signal input terminal.
A flip-flop is obtained having a sixth transmission gate in which the input and output of the transmission gate and the third transmission gate are connected in parallel and are switched by a signal from the initialization signal input terminal.

(5) Detailed description of this invention Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention includes a data input terminal 10, an input DaA terminal 11 of clock 1a, an initialization signal terminal 12, a take output terminal 13, and a first transmission terminal -:1. -) 2L A first launch consisting of a second inverter 31, a third inverter 32, ', 'pJ2 transmission gate 22, a third transmission gate, a fourth inverter,
a second latch consisting of a fifth inverter, a fourth transmission gate, an inverter for inverting a clock signal, and a first latch;
．． The fifth transmission gate is connected in parallel with the third transmission gate, respectively.
．． Including the sixth transmission gate and t.

the first impact; The second latch constitutes a D-type flip-flop that is triggered at the falling edge of the clock signal. In the configuration shown in FIG. 1, when a signal for determining an initial value is input to the initial setting signal input terminal, the signal at the data input terminal is inverted as shown in FIG. 2, that is, the same signal is output completely independent of the clock phase.

FIG. 2 shows an example in which a multi-stage shift register is constructed using the embodiment array of the present invention shown in FIG. Data input terminal 50, clock input terminal 51, and initial setting signal terminal 5
2, a data output terminal 53, and N flip-flops 1 to N shown in FIG. Normally, to initialize this type of N-stage shift register, N clocks are input and input data is sequentially read. However, in the embodiment of the present invention shown in FIG. 2, by inputting an initialization signal to the initialization input terminal, the value at the data input terminal is transmitted to the data output terminal regardless of the clock phase.

(6) Effects of the Invention As explained above, the present invention provides a through-signal path from the data input terminal to the data output terminal, completely independent of the clock signal, so that the input data can be transmitted completely independently of the cyclic phase. By transmitting this to the output, there is an effect that the initial setting can be performed in less than one period of the clock.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram partially showing an embodiment of the present invention, and Fig. 2 is a circuit diagram in which the flip 70 tubes shown in Fig. 1 are used as a multi-stage shift register. . 10...Data input terminal, 11...Clock input terminal, 2...Initial setting signal input terminal, 13...Data output terminal, 21... ...
First transmission gate 1.22... Second transmission gate, 23... I Third transmission gate, 24...
...Fourth transmission gate, 25...Fifth transmission gate, 26...Sixth transmission gate, 30...
...First inverter, 31...Second inverter, 32...Third inverter, 33...
...Fourth inverter, 34...Fifth inverter, 41...First phase clock signal, 42...Second phase clock Signal, 50...
...Data input terminal, 51...Clock input terminal, 52...Initial setting signal input terminal, 53
...Data output terminal. one

Claims (1)

[Claims] 1 which has a data input terminal, a clock input terminal, and an initialization input terminal, and obtains a second clock phase by inverting the first clock phase when the first clock phase is used as a signal of the clock input terminal. a first transmission gate that receives a data input signal as an input and is switched at a first clock phase; a second inverter that receives an output signal of the first transmission gate as an input; a third inverter that receives the output signal as an input; a second transmission gate that receives the third inverter output signal and whose output is connected to the first transmission gate output and is switched at a second clock phase; a third transmission gate that receives the output signal of the second inverter as input and is switched at the second clock phase; a fourth inverter that receives the output signal of the third transmission gate; The fifth input
and a fourth transmission gate that receives the fifth inverter output signal, has an output connected to the third transmission gate output, and is switched at the first clock phase. In the flip-flop, a fifth transmission gate is connected in parallel to the first transmission gate and is switched by a signal from the initial setting signal input terminal, and a fifth transmission gate is connected in parallel to the third transmission gate and is switched by a signal from the initial setting signal input terminal. A flip-flop characterized in that it has a sixth transmission gate that is switched by a signal.