JPS605492A - Address buffer circuit of semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate the effects of the phase difference of input signals and the noises without increasing the number of external signal terminals, by obtaining an OR of the pulse signal every address input terminal to produce the trigger signal for a piece of address latch circuit and to input the trigger signal to a trigger input terminal of each address latch circuit. CONSTITUTION:A circuit group 7 is provided to each address input terminal, and an AO address input terminal 17 is connected to the input terminal of the 1st circuit group 7. At the same time, the A1 and A2 address input terminals 18 and 19 are connected to the input terminals of the 2nd and 3rd circuit groups 7 respectively. A wired OR4 is obtained among output terminals 8-11 of the 1st- 4th circuit groups 7, and the output terminal of the OR4 is connected to a trigger input terminal. The group 7 detects the changing point of an address input signal to produce a trigger signal 12 which fetches the address information to an address latch circuit 6. Then the data input signal of the circuit 6 is fetched to the address latch circuit by the signal 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address buffer circuit for a semiconverting memory device.

[Background of the invention]

Conventionally, address buffer circuits used in semiconductor memory devices generally have the following two methods.

(The address input terminal is connected to the address decoder IOJ path via the buffer cable circuit.

(2) The address input terminal is provided with a buffer path, and the trigger signal for capturing the address signal in the latch circuit is provided with an external 7 input terminal, and the address signal is input by inputting an external trigger signal +5. is taken into the launch circuit,
The output terminal of the latch circuit was used as a decoder circuit.

In the method described above, since the address input signal (i) is directly transmitted to the decoder, the phase shift and fiber of the address input signal are likely to cause information destruction in the memory 1 and 11 operation.

Method (2) increases the number of input terminals by one. Furthermore, it is necessary to match the phases of the address signal for the latch circuit and the latch circuit trigger signal.

[Purpose of the invention]

The purpose of this @mei is to eliminate the above-mentioned conventional problems, and to create a semi-diagrammatic memory g direct address that has the effect of eliminating the phase difference of the input signal and the effects of noise by increasing the number of external signal terminals. The purpose of the present invention is to provide a buffer circuit.

[Summary of the invention]

The feature of the present invention is that a pulse signal is generated for each address signal terminal in the address input/Nl sofa by using the rising and falling change points of the address input signal,
The pulse signals generated for each address input medium are logically ORed to make one pulse signal, and this one
This signal is used as a common latch signal for the latch circuits provided for each valley address input terminal, and address information is taken into each latch circuit when the address input signal changes. Since the pulse signal generated for each address terminal is logically set to 01, even if there is a phase difference in the address signal, the pulse signal that is effective as a common latch signal for the circuit is the address input. Pulses (fi
Therefore, the address manual signal phase difference does not change by 1 after the address latch circuit.

[Laughter example of invention]

Next, a practical example of "Unexploded tsu" will be explained in detail using drawings.

Figure 1 shows 14 bits (16 bits) at a time for single cabinet.

The input terminal of the circuit group 7 is fitted to the input terminal A of the buffer circuit 10, and the positive output terminal of the buffer circuit 1 is connected to a matching circuit (when the two input terminals match, the output terminal A is at level 6,
If there is a discrepancy, output 1 person and bell) 3 1 person power/X: ″1
The other input terminal is connected to the output terminal of the delay circuit 2, and the input terminal of the delay circuit 20 is connected to the negative output of the buffer circuit 1. Further, as for the output terminal of the circuit group 7, one of the output terminals of the coincidence circuit 3 is connected.

The circuit group 7 configured in this way is prepared for each address input terminal, and the AO address input terminal 17 is connected to the first circuit group 7.
0 input terminal, Al address input terminal 18 is connected to second circuit group 70 input terminal #, continuation, A2 address input terminal 1
9 is connected to the input terminal of the third circuit group 7, and A
The third address input terminal 20 is connected to the input terminal of the fourth circuit 6+7, and the output terminals 8, 9, 10.11 of the first to fourth circuit group 7 are wired OR4. The output terminal is connected to the four address latch circuits 6 via the inverter circuit 5;, 711
My child has BHIcε. Further, the address input terminals 17, 18, 19.degree. 20 are connected to the latch data input terminals of the four latch circuits 6, respectively. Each address latch circuit output terminal is connected to the input terminal of the next stage decoder circuit.

The self-circuit group 7 of the circuit generates a tri-force signal 12 that detects the change point of the address input signal and takes in the address information to the address latch circuit 6, and uses this tri-force signal 12 to control the data input signal of the latch circuit 6. Load into address latch circuit.

FIG. 2 shows operating waveforms of the address buffer circuit of the semi-dedicated memory device of FIG.

Address input waveforms AO to A3 are manually input with phase differences as shown in FIG. The circuit group 7 generates positive signals 8, 9, 1011 having the pulse width set by the delay circuit 2, and wires the stop signals 8, 9, 10, 11 to generate a trigger pulse No. 4g 12.

The four address latch circuits 6 are falling edge trigger circuits that perform data latching operations at the falling edge of the trigger signal input, and the outputs of the address latch circuits have address latch output waveforms 13, 14, 15, 16, This output waveform is transmitted to the next stage decoder circuit. Here, depending on the magnitude of the phase difference between the address input signals, the delay $jE I! in the circuit group 7 is determined. l! Changing the delay time of 1 path and 2 [Effects of the invention] Since the configuration is as described above, according to the present invention, the following effects can be obtained.

1. H operation and data destruction due to address input phase difference and noise can be prevented.

2. The above effect can be obtained by using an external trigger signal, and a single history can be used asynchronously.

4 1st year celebration of the section FIG. 3 is an operational waveform diagram of the illustrated circuit.

1... Buffer circuit 2... Delay circuit 3... Match circuit 4... Wired (JR circuit 5... Inverter circuit 6... Address latch circuit 7... Circuit group 8-11...
...Pulse signal 12...Triforce signal 13-16...
・Latch output signals 17 to 20...address input terminal younger brother / Figure 2

Claims (1)

[Claims] 1. In an address buffer circuit of a semiconductor memory device that sends an address signal input from an input terminal to a decoder circuit, the address buffer circuit has an address latch circuit for each address input signal, and further includes an address latch circuit for each address input terminal. Then, a pulse signal is created for each valley address by detecting the rising and falling changes of the address signal, and the pulse signal for each valley address input terminal is set to logic 0) and L to become a trigger signal for one address latch circuit. The trigger signal is commonly input to the trigger input terminal of each address latch circuit, and each address signal applied to the data input terminal of the valley address latch circuit is taken into the valley address latch circuit by the trigger signal and each address 1. An address buffer circuit for a semi-integrated memory device, characterized in that an output terminal of a latch circuit is connected to a decoder circuit.