JPS6359017A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To output a pulse with an always constant width independently of the width of a trigger input signal by controlling other RS flip-flop circuit so as not to be triggered again until the output of a pulse is finished after the circuit is triggered once by one RS flip-flop circuit. CONSTITUTION:When an input signal (a) is inputted, the 1st RS flip-flop circuit 11 is set and its Q output (g) changes from L to H. The change sets the 2nd RS flip-flop circuit 12 after a prescribed time. The Q output of the RS flip-flop circuit 12 resets the RS flip-flop circuit 12 resets the RS flip-flop circuit 11 through an inverter 16. Thus, a pulse having a prescribed time width obtained by a delay circuit is outputted. In such a case, the Q output (d) of the RS flip- flop circuit 12 is at L until the input signal (a) goes to L and reset to prevent the RS flip-flop circuit 11 from being set again.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generation circuit that generates a pulse by triggering at the edge of a trigger pulse.

C. Conventional technology] FIG. 4 shows a conventionally commonly used pulse generation circuit.

In the figure, 1.2.3 is an inverter, 4 is an AND gate with negative logic input, and 5 is a capacitor.
．． 2 and the capacitor 5 constitute a delay circuit. 5 is a timing chart showing the operation of FIG. 4, where a'-6 indicates the signal waveform at each point in FIG. 4, and p indicates the threshold value of the inverter 2.

Next, the operation will be explained. The trigger pulse a is delayed by tWl by the delay circuit, as shown in FIG.
It is input to D gate 4. At the same time, the polarity is inverted by the inverter 3 and input to the other input of the AND gate 4. AND gate 4 has both re-inputs “L”
6H" is output, so a pulse with a width of tw+ is output at the rising edge of Trikahalus a, as shown in e in Figure 5. Note that no pulse is output at the falling edge. .

In this way, the circuit shown in FIG. 4 functions as a pulse generating circuit that outputs a pulse triggered by the rising edge of an input signal.

Note that in this circuit, when a narrow pulse like the pulse at t8 is input, the delay circuit does not operate sufficiently, and a pulse with the same pulse width at t2 is output.

[Problem that the invention seeks to solve]

In the conventional pulse generation circuit shown in Fig. 4, if the width of the input signal becomes too narrow, the delay circuit will not operate sufficiently, so a pulse with the same width as the input signal will be output. If the generator circuit is used to reset a shift register as shown in Figure 6 at the rising edge of a certain signal, it will definitely be reset if the width of the input signal is wide enough, but if the width of the input signal is When the width becomes narrower, there is a problem that the reset may not be performed, resulting in malfunction of the system.

This invention was made to solve the above problems, and it is possible to output a pulse with a constant width by triggering at the rising or falling edge of an input signal, regardless of the width of the input signal. The purpose is to obtain a pulse generation circuit.

[Means for solving problems]

The pulse generation circuit according to the present invention includes a first 2379717071 circuit whose trigger input is connected to the S input, and a second 2379717071 circuit whose trigger input is connected to the R input.
717071 circuit and the above first 2379717071
The Q output of the circuit is changed to the second 23797 after a certain period of time.
A delay circuit input to the S input of the 17071 circuit and an inverter inverting the 100 output of the second 2379717071 circuit and inputting it to the R input of the first 2379717071 circuit are provided.

[Effect]

In this invention, since the Rs rough flop circuit is used, the width of the trigger input signal is 23797170.
As long as the width is longer than the operating time of the 71 circuit, the trigger can be guaranteed even if it is thin, and the second 237971
After the 7071 circuit has been triggered, the first R
Since it controls the S flip shift circuit, even if the trigger input signal is longer than the output pulse width, the first R379717071 circuit is reset so that it will not be triggered again, and the width will always be constant regardless of the width of the trigger input signal. can output pulses.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a pulse generation circuit according to an embodiment of the present invention. In the figure, 11 is a first R379717071 circuit, 12 is a second R379717071 circuit, and these circuits 11 and 12 are N.

It is configured using an R gate. 13 to 16 are inverters, 17 is a capacitor, and inverter 13.14
and a capacitor 17 constitute a delay circuit. FIG. 2 is a timing chart showing signal waveforms at each point in FIG. 1.

Next, the operation will be explained.

When input signal a is input, tI
The first RS flip-flop circuit 11 is set, and its Q output 2 output g changes from "L" to "H".

This change passes through a delay circuit composed of inverters 13 and 14 and a capacitor 17, and sets the second R flip-flop circuit 12 after a certain period of time. and,
The Q output of the 2379717071 circuit 12 passes through the inverter 16 and resets the first RS flip-flop circuit 11, and the Q output g changes from "H" to "L". A pulse having a constant time width obtained by the delay circuit is outputted to the Q output g. Note that at this time, the second RS flip-flop circuit 12 is reset until the input signal a becomes "L" again and the output d becomes "L" and the first RS flip-flop circuit 11 is reset. Prevent it from being set again.

Furthermore, even if the width of the input signal a is extremely narrow as t8, the R379717071 circuit is always set as long as the width of the input signal a is greater than or equal to the operating time (operating speed) of the R379717071 circuit. Output is from “L” to H”
Changes to Then, as in the case where the width is t, the first R
The S flip-flop circuit 11 outputs a pulse having a constant width. In this case, the second RS flip-flop circuit 12 is reset before it finishes outputting the pulse and enters the state of waiting for the next input signal, but since the first RS flip-flop circuit 11 is still in the reset state, Even if the next signal is input during the pulse output, the pulse will not become longer due to being triggered again.

In this way, in this example circuit, two R3797170
The second R329217071 circuit uses a second R329217071 circuit to prevent the first R379717 from being triggered again until the pulse has finished outputting.
Since the 071 circuit is controlled, it is possible to always output a pulse of a constant width regardless of the width of the trigger input signal.

Furthermore, if this pulse generating circuit is used in a system reset pulse generator as shown in FIG. 6, a stable system that is not affected by the width of the signal for applying the reset can be constructed.

Further, FIG. 3 shows a pulse generating circuit according to another embodiment of the present invention. In this embodiment, the R379717071 circuit is constructed using a NAND gate instead of a NOR gate, and thereby a pulse triggered by a falling edge can be generated.

Note that in the above embodiment, the delay circuit has a configuration consisting of two inverters and a capacitor, but this may have another configuration. For example, the delay circuit can be configured as R
If it is configured with C, it is possible to output a pulse with a width determined by the RCO time constant.

〔Effect of the invention〕

As described above, according to the pulse generation circuit of the present invention, two R379717071 circuits are used, and the second R3797
The 17071 circuit controls the first RSS flip-flop circuit so that it will not be triggered again until the pulse has finished being output after it has been triggered. This has the effect of being able to output pulses of a constant width.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing a pulse generating circuit according to one embodiment of the present invention, FIG. 2 is a timing chart thereof, and FIG. 3 is a pulse generating circuit according to another embodiment of the present invention. 4 is a circuit diagram showing a conventional pulse generating circuit, FIG. 5 is a timing chart thereof, and FIG. 6 is a diagram showing an example of a system using the pulse generating circuit. In the figure, 11 is a first RS flip-flop circuit;
12 is the second R379717071 circuit, 13.14.
15 and 16 are inverters, and 17 is a capacitor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A first RS flip-flop circuit whose trigger input is connected to the S input, and a second RS flip-flop circuit whose trigger input is connected to the R input.
a flip-flop circuit; a delay circuit for inputting the Q output of the first RS flip-flop circuit to the S input of the second RS flip-flop circuit after a certain period of time; and a Q output of the second RS flip-flop circuit. and an inverter that inverts the output and inputs it to the R input of the first RS flip-flop circuit, and generates a pulse from the Q output of the first RS flip-flop circuit. (2) The pulse generation circuit according to claim 1, wherein the RS flip-flop circuit is constructed using a NOR circuit or a NAND circuit.