JPH0784011A - Clock generation circuit for scan test - Google Patents

Abstract

PURPOSE:To achieve a shortening or testing time by changing first and second clocks for scan test according to the rising and falling of an input clock signal. CONSTITUTION:A logic circuit changes according to the rising and falling of a CLOCK signal and outputs a clock SC1 for scan test as continuous signal having '001' as one unit and a clock SC2 as continuous signal having '011' as one unit. The cycle of the clocks SC1 and SC2 is 1.5 fold as compared with the CLOCK signal. The clock SC1 is inputted into an FF circuit with a latch on the slave side in a scan test circuit made up of flip flop FF circuits connected in series and the clock SC2 into the FF circuit with a latch on the master side. Reading into IN, holding of data and outputting to SOUT, three of circuit operations, are performed at a cycle 1.5 times as much as the CLOCK signal, thereby achieving a scan pass test at a higher speed than ever.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for dividing and controlling a clock signal input to a flip-flop circuit for performing a scan test.

[0002]

2. Description of the Related Art A conventional test circuit will be described with reference to FIGS.

FIG. 6 is a diagram showing the configuration of a conventional circuit for generating a scan test clock.

This conventional example is composed of two flip-flop circuits 66 and 67 which perform a latch operation. Each flip-flop circuit is used as a frequency dividing circuit that receives each inverted output as an input. External clock signal CLOCK as an operation clock of each flip-flop circuit
Are input so that the phases of the flip-flop circuits are different, the flip-flop circuits 66,
The relationship between the scan clock signals SC3 and SC4 output by 67 is shifted by 1/2 cycle of the external clock signal CLOCK.

Scan clock signals SC3 and SC4
Is input to the scan test circuit composed of a latch circuit in which the flip-flop circuits shown in FIG. 8 are connected in series.

In the scan test circuit, flip-flop circuits 88 and 89 are connected in series, and the whole constitutes a shift register. By operating the shift register, the contents of the flip-flop circuits 88 and 89 can be observed. The flip-flop circuit 89 receives the scan test signal SC3 as a clock input, and the flip-flop circuit 88 receives the inverted output of the adder circuit OR81 for adding the scan test signals SC3 and SC4 as a clock input. Data is transferred from the flip-flop circuit. The time required for one transfer to the next-stage flip-flop circuit is one test cycle.

A scan path test is performed by connecting a plurality of stages of the scan test circuit configured as described above in series.

The test cycle of the scan test circuit of FIG. 8 will be described with reference to FIG.

First, the flip-flop circuit 88 reads the data at the SIN terminal, and then holds it. Next, the flip-flop circuit 89 changes the flip-flop circuit 88.
The data held by is output to the SOUT pin.

The sum of the above three operation times is 1 in the test.
It becomes a cycle. In the test cycle, there is a period during which data is held between the read operation of the SIN terminal and the output operation to SOUT. Due to this period, malfunction due to skew that occurs between flip-flop circuits can be prevented.

[0011]

The problem of the test cycle in the scan test described in the prior art is shown in FIG.
Will be described with reference to.

The read time and the data retention time of the SIN terminal correspond to 1/2 cycle of the CLOCK signal, respectively.
The output time to OUT corresponds to one cycle of the CLOCK signal. Therefore, one cycle of the test corresponds to two cycles of the CLOCK signal.

Thus, only the output time to SOUT is
Since it takes twice as long as the SIN reading time and the data holding time, there is a problem that it takes time to perform the scan test.

The present invention has been made in view of the problems of the above-described conventional technique, and it halves the output time of SOUT and generates a scan test clock that can perform a scan test in a short time. The purpose is to realize a circuit.

[0015]

A scan test clock generating circuit of the present invention synthesizes a frequency dividing circuit for dividing an input clock signal and a signal generated by the dividing circuit with the clock signal. A scan test clock generation circuit configured to generate a scan test clock of a scan test circuit including a logic circuit and a latch circuit in which flip-flop circuits are connected in series,
The logic circuit changes in increments of "001" as a unit in response to rising and falling of the clock signal, and inputs the first scan test clock input to the slave side latch of the scan test circuit and the clock. A second scan test clock that changes in increments of “011” in response to the rising and falling edges of the signal and is input to the master side latch of the scan test circuit;
Is generated.

[0016]

In the present invention, the first and second scan test clocks for performing the scan test change according to the rising and falling edges of the input clock. Since these change states are "001" or "011", the cycle is 1.5 times the input clock in either case.

The scan test circuit reads SIN in accordance with the above-mentioned first and second scan test clocks,
Since three operations of holding data and outputting to SOUT are performed, each of these operations is 1.5 times the cycle of the input clock signal.
Everything will be done in a double cycle.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram showing a scan test clock generated by the embodiment of FIG. 1, and FIG. 3 is an embodiment shown in FIG. 6 is a circuit diagram showing a configuration of a scan test circuit using the scan test clock generated by FIG.

In this embodiment, as shown in FIG. 1, the output of the frequency dividing circuit in which flip-flop circuits 1 to 3 are connected in series is
AND gates AN1 to AN9, OR gates OR1 to OR
6 and the inverters IN1 to IN6 are combined with the CLOCK signal to generate scan test clocks SC1 and SC2.

As shown in FIG. 2, the above logic circuit has a CL
The scan test clock SC1 is "001" because it changes according to the rise and fall of the OCK signal.
Is output as a continuous signal, and the scan test clock SC2 is output as a continuous signal in which "011" is set as a unit. As described above, the scan test clocks SC1 and SC2 are 1.
It has a cycle of 5 times.

The scan test clock SC1 is shown in FIG.
Flip-flop circuit 3 connected in series as shown in
4, the scan test clock SC2 is input to the flip-flop circuit 35 serving as the master side latch.
FIG. 6 is a diagram showing an operation timing of the scan test circuit configured as described above. The three operations of reading SIN, holding data, and outputting to SOUT are all performed in a cycle that is 1.5 times the cycle of the CLOCK signal, compared to the conventional example shown in FIGS. 6 to 9. It is possible to perform campus tests at high speed.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a circuit diagram showing the configuration of the second embodiment of the present invention.

In this embodiment, a delay circuit 53 is added to the embodiment shown in FIG. Delay circuit 53
Are inserted between the input terminal of the CLOCK signal and the logic circuit. Since the other structure is similar to that of the embodiment shown in FIG. 1, the same reference numerals are given and the description thereof is omitted.

The CLOCK signal passed through the delay circuit 53 receives the AND gates AN7 to AN9 and the OR gates OR4 to OR4.
Each of the flip-flop circuits 1 to
It is combined with each signal of the internal points A, B and C generated in 3.

In the logic synthesis circuit 54, CLOCK
The signal is faster than the CLOCK signal at interior points A, B and C. This is the output of the frequency divider (Q1, Q2, Q3)
From the above, it is clear when the number of logic elements existing between the wiring paths of the internal points (A, B, C) is considered. Therefore, the output signals of the scan test clocks SC1 and SC2 are shown in FIG.
The pattern may change. Therefore, by inserting the delay circuit 13 in the path of the CLOCK signal,
Internal points A, B, C and CLOC in the logic synthesis circuit 14
It is possible to reduce the delay difference of the K signal. This will prevent SC1 and SC2 from generating erroneous patterns.

The delay circuit 13 can be constructed by using, for example, an even number of inverters, and the configuration is not particularly limited. Also, the configuration of the logic circuit
The scan test clocks SC1 and SC2 are not particularly limited as long as they have the above-mentioned characteristics.

[0029]

Since the present invention is constructed as described above, it has the following effects.

According to the present invention, it is possible to generate a scan test clock having a period 1.5 times the period of the clock signal input from the outside. Compared with the conventional scan test clock having a cycle twice that of the external input clock signal, the scan test clock cycle itself is 25% shorter, and the time required for the scan test can be reduced accordingly. There is an effect that the test can be performed quickly.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is an output pattern diagram of the first embodiment of the present invention.

FIG. 3 is a scan test circuit diagram according to the first embodiment of the present invention.

FIG. 4 is a scan test cycle according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional technique.

FIG. 7 is an output pattern diagram of a conventional circuit.

FIG. 8 is a scan test circuit diagram in the related art.

FIG. 9 is a scan test cycle of a conventional technique.

[Explanation of symbols]

1, 2, 3, 34, 35 Flip-flop circuit (flip-flop) 53 Delay circuit 54 Logic synthesis circuit AN1 to AN9 AND gate OR1 to OR6 OR gate IN1 to IN6 Inverter

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[Procedure amendment]

[Submission date] July 5, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. A latch comprising a frequency divider circuit for dividing an input clock signal and a logic circuit for synthesizing a signal generated by the frequency divider circuit with the clock signal, and a flip-flop circuit connected in series. A scan test clock generating circuit for generating a scan test clock of a scan test circuit configured by a circuit, wherein the logic circuit uses "001" as a unit in response to rising and falling of the clock signal. The first scan test clock that changes and is input to the slave side latch of the scan test circuit, and changes in increments of "011" in response to rising and falling of the clock signal. And a second scan test clock input to the master side latch. Scan test clock generation circuit.