JPH10133768A - Clock system and semiconductor device, and method for testing semiconductor device, and cad device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily realize a sequential circuit and a clock system, and to reduce the power consumption of the clock system itself by generating a 1f clock with a frequency necessary for a state storage circuit from a 1/2f clock. SOLUTION: A clock with a frequency 1/2 of the frequency of a clock, whose pulse width is narrow and used for a state storage circuit 54 constituting a sequential circuit, is inputted from the outside of a semiconductor device. This 1/2f clock is inputted to a clock input terminal, and fetched in the semiconductor device by a clock buffer 51. The fetched 1/2f clock is distributed from the clock input buffer 51 to each part of the semiconductor device, and a clock buffer 52 is provided in the middle for compensating the insufficiency of a driving capability due to the presence of only the clock input buffer 51. A 1f clock generating circuit 53 generates a 1f narrow pulse clock 1f CK with a frequency twice the size of the frequency of the distributed 1/2f clock, and supplies it to a latch circuit 54 constituting the adjacent sequential circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock system for supplying a clock to a state storage circuit (register circuit) operating in synchronization with a clock, a semiconductor device having such a clock system, a test method therefor, and the like. CAD (Compute) to create a simple clock system
r Aided Design)
The present invention relates to a clock system for realizing a circuit configuration capable of reducing a circuit scale.

[0002]

2. Description of the Related Art In recent years, large-scale semiconductor integrated circuits (LSIs)
The integration scale of LSIs is increasing more and more, and despite the miniaturization due to the progress of the manufacturing process technology, the power consumption of the LSI itself is increasing. Then, the power consumption of the LSI alone determines the circuit scale that can be integrated. Also, in a semiconductor device system in which a large number of such semiconductor devices are mounted on a printed wiring board, power consumption is a major problem.

In some semiconductor devices, the power consumption of a clock wiring or a clock driver circuit for transmitting a clock and a state storage circuit (register circuit) operating in synchronization with the clock is １ ／ of the power consumption of the entire LSI chip. In some cases, reduction of power consumption in these parts is a major issue. A similar problem also occurs in a semiconductor device system in which a large number of semiconductor devices are arranged on a printed wiring board and operated in synchronization with a clock. The present invention is applicable to both a clock system in a semiconductor device and a semiconductor device system in which a semiconductor device is combined. Here, a clock system in a semiconductor device will be described as an example.

FIG. 1 is a diagram showing a basic configuration of a conventional example of a clock system in a semiconductor device. In the conventional example shown in FIG. 1, a clock is supplied from outside to a clock input terminal, and a plurality of clock buffers 11, 1
The signals are supplied to the state storage circuit 14 via the terminals 2 and 13. In FIG. 1, the clock buffer 11 is shown to include a clock input terminal. In general, a master-slave flip-flop circuit is used as the state storage circuit. Note that the clock may not be supplied from the outside but may be generated inside the semiconductor device.

FIG. 2 is a timing chart showing the operation of the conventional example. As shown in the figure, an external clock signal CK input from the outside and complementary signals CK and XCK, which are FF clock signals used for the synchronous operation of the flip-flop circuit, are signals having the same cycle as the external clock signal CK. It is. In addition, since it takes time from the clock input terminal to be transmitted to each flip-flop circuit through the clock system, the FF clock signal is actually delayed with respect to the external clock signal. This delay has been omitted for simplicity.
As described above, in the conventional clock system, the clock necessary for the operation of the flip-flop 14, which is the state storage circuit, is transmitted as it is. In general, the operating frequency of a clock is very high and the operating rate is high, so that a clock system consumes a great deal of power.

FIG. 3 is a diagram showing an example of a system configuration using a flip-flop as a state storage circuit.
FIG. 3 is a diagram showing a configuration of a master-slave flip-flop. In the example shown in FIG. 3, the flip-flop (F
F1) Data D is input to 21 and FF1 is clock C
This data D is taken in synchronism with K and output as output Q. The output Q passes through a logic circuit (combinational circuit) 22 composed of a gate or the like, and a flip-flop (FF) at the subsequent stage.
2) Input to 23. The FF 2 takes in the output of the combinational circuit 22 in synchronization with the clock CK and outputs it to the next stage as the output Q. Thus, each flip-flop transfers data one stage at a time in synchronization with the clock. In an actual circuit, outputs from a plurality of flip-flops are input to the combinational circuit 22, but here, for simplicity, only the output from one flip-flop is shown.

As shown in FIG. 4, the master-slave type flip-flop connects two latch circuits 31 and 32 in series so that the output of the preceding latch circuit becomes the input of the subsequent latch circuit. And input a clock of opposite phase to the subsequent stage. When the clock has one logical value, the preceding latch circuit 31 is in the passing state, the succeeding latch circuit 32 is in the cutoff state, and the input data is taken in by the preceding latch circuit 31, but the latter latch circuit is not. The state is stopped at 32. Next, when the clock changes to the other logical value, the preceding-stage latch circuit 31 is turned off, the latter-stage latch circuit 32 is passed, and the preceding-stage latch circuit 31 is turned off.
Is taken into the latch circuit 32 of the subsequent stage and outputted. Even if the input data D changes in this state, the state of the flip-flop is not affected. When the clock changes to one logical value again, the preceding latch circuit 31 takes in the input data, but the subsequent latch circuit 3
The output of 2 does not change. Therefore, the output data is held in a stable state for one cycle of the clock.

FIG. 5 is a diagram showing an operation in a system using the flip-flop shown in FIG. As shown in the figure, the input data to the FF1 at the preceding stage changes with one cycle of the clock as a cycle. When the clock CK changes as shown with respect to such input data, the preceding stage FF1 latches in synchronization with the rising edge of the clock CK, so that the output of the preceding stage FF1 changes from the rising edge of the clock CK to the FF1. It will change with a delay. The output of the FF1 is delayed by the combinational circuit 22 and is input to the subsequent FF2. Therefore, the subsequent FF
The change of the input data to 2 is as shown in the figure. Latter stage F
Since F2 also latches the input data in synchronization with the rising edge of the clock CK, the input data to the FF2 at the subsequent stage needs to be determined at the rising edge of the clock CK. Also, even if the delay amount of the flip-flop or combinational circuit is small and the input to the next-stage flip-flop changes immediately after the output of the previous-stage flip-flop changes,
The next flip-flop takes in the next clock CK
Is not performed until the rising edge of.

As described above, in a circuit in which conventional state storage circuits are combined, data supplied to each state storage circuit needs to be processed for predetermined data.
By using a flip-flop to transfer data to each state storage circuit portion in synchronization with a clock, data to be processed is temporally defined. A circuit in which such a plurality of state storage circuits are combined and the state storage circuit sequentially transfers data of each part in synchronization with a clock is referred to as a sequential circuit in the following description.

As shown in FIG. 4, a commonly used master-slave type flip-flop is composed of two latch circuits, and the circuit size thereof is large. In some cases, the area occupies about half the area of the combinational circuit. As described above, there is a demand for a reduction in power consumption and a circuit scale in a sequential circuit. If the master-slave flip-flop shown in FIG. Therefore, the reduction of the circuit scale has been a major issue.

Japanese Patent Laying-Open No. 3-26104 discloses that a sequential circuit can be formed by using a latch circuit instead of a master-slave flip-flop by using a sliver clock having a short pulse width instead of a clock. Has been disclosed. FIG. 6 is a diagram illustrating an example of a system in which a sequential circuit is configured using a latch circuit instead of a master-slave flip-flop, and FIG. 7 is a diagram when a sliver clock having a narrow pulse width is used as a clock. 6 is a diagram illustrating the operation of the circuit of FIG.

As is apparent from FIG. 4, the master-slave flip-flop also has a latch circuit provided at the subsequent stage in order to cut off data latched at the preceding stage. When only the latch circuit is used, that is, when only the preceding latch circuit is provided and the subsequent latch circuit is not provided, the data is not interrupted. Therefore, when the clock is in one logic state, the data captured by the preceding latch circuit is immediately output. Therefore, while the clock is in one of the logic states, data to be input to the next-stage latch circuit is pierced, which causes a problem that a normal operation cannot be performed.
Therefore, in the system disclosed in Japanese Patent Application Laid-Open No. 3-26104, a clock called a sliver clock having a narrow pulse width as shown in FIG. By setting the latch circuit in a holding state before the data is transmitted to the memory, it is possible to prevent such data penetration. The latch circuit is half the circuit scale as compared with the master-slave flip-flop, so that not only the area required for the circuit but also the power consumption can be reduced by half.

However, in reality, a system that uses a latch circuit instead of such a master-slave type flip-flop and uses a sliver clock as a clock is not often used. This is because there are many restrictions in the design and it is difficult to actually realize the system. In order for the latch circuit to operate normally and to prevent data penetration, the pulse width of the sliver clock must be equal to or greater than the minimum pulse width required for the latch circuit to operate normally, and the amount of delay in the latch circuit And the delay amount in the combinational circuit must be smaller than the sum of the delay amounts, and it is necessary that the waveform be a predetermined clear waveform with less rounding. There are two constraints, that a predetermined pulse width must be generated, and that the clock skew must be kept within a negligible range over the entire chip, and it is very difficult to satisfy both at the same time. Even if it can be realized, there has been a problem that the wiring capacity of the clock net becomes unnecessarily large and power consumption in the clock net increases.

FIG. 8 is a diagram showing a configuration of a clock system for distributing a sliver clock when a latch circuit is used instead of the master-slave flip-flop. As shown in FIG. 8, each of the input terminals to which a basic clock signal for generating a sliver clock is supplied and a clock buffer 45 provided therewith pass through a path that causes substantially the same amount of delay. The signal is supplied to the sliver clock generation circuit 46. In order to provide a path that generates almost the same amount of delay, it is necessary to make the number of buffers provided in the middle, the load capacity, and the like the same.
It is common to use an H-tree-like clock wiring method as shown in FIG. 1, but in such an H-tree-like clock wiring path, it is necessary to match the entire length to the longest wiring length, so that it is more than necessary. There has been a problem that the wiring capacity increases and power consumption in the clock net increases. Further, in the case of the H-tree clock wiring, there is a problem that the arrangement position of each sliver clock generation circuit at the end is restricted.

[0015]

As described above, if a sliver clock having a narrow pulse width is used and a latch circuit is used instead of the master-slave type flip-flop,
An equivalent sequential circuit can be realized with half the circuit scale, and the power consumption is also halved. However, the above timing adjustment is necessary, and it is necessary to perform clock wiring in an H-tree form, which makes it difficult to actually realize it because the power consumption of the clock distribution system increases. .

The present invention solves the problem of realizing a sequential circuit using a sliver clock having a narrow pulse width and using a latch circuit instead of a master-slave flip-flop. Another object of the present invention is to make it possible to easily realize a clock system and to reduce power consumption of the clock system itself.

[0017]

FIG. 9 is a diagram showing the principle configuration of a clock system according to the present invention. In the clock system of the present invention, in order to achieve the above object, the clock to be transmitted is a half frequency of half the frequency of the clock used in the state storage circuit, and the 1/2 clock is used by the state storage circuit. A 1f clock having a frequency that is twice as high is generated.

That is, the clock system of the present invention comprises:
A state storage circuit that operates in synchronization with the clock, and a frequency that is 1/2 of the frequency of 1/2 of the 1f clock used in the state storage circuit.
A 1 / 2f clock source for outputting a 2f clock;
a clock transmission path for transmitting a 1 / 2f clock output from the f clock source, and a 1f clock provided near the state storage circuit and multiplying the 1 / 2f clock transmitted on the clock transmission path to generate a 1f clock And a 1f clock generated by the 1f clock generation circuit is supplied to the state storage circuit.

According to the clock system of the present invention, the transmission of the clock in the semiconductor device is performed in the form of a 1 / 2f clock having a half frequency of the clock used in the state storage circuit. The power consumption of each circuit related to transmission is greatly reduced. As the state storage circuit, a latch circuit which performs the same logical function operation as an edge trigger type register circuit by clocking with a 1f narrow pulse clock having a predetermined narrow pulse width, or a dynamic master latch circuit is provided at an input portion of the latch circuit. It is desirable to use a master-slave flip-flop circuit to which a transmission gate is added.

As described above, the latch circuit has a half circuit scale as compared with the master-slave type flip-flop shown in FIG. 4, so that the circuit area and power consumption can be reduced.
A master-slave flip-flop in which a transmission gate is added as a dynamic master latch circuit to the input portion of the latch circuit performs the same operation as the master-slave flip-flop shown in FIG. 4, but the circuit scale is small. , The circuit area and power consumption can be reduced. As the state storage circuit, only a latch circuit or only a master-slave flip-flop to which a transmission gate is added may be used, but may be appropriately combined. For example, a master-slave flip-flop to which a transmission gate is added is used as a state storage circuit used in a place where it is difficult to realize the above condition due to a small amount of delay in a combinational circuit. Use a latch circuit.

As described above, when a latch circuit is used as a state storage circuit, it is necessary to use a sliver clock having a narrow pulse width in order to prevent penetration of data. was there. However, in the clock system of the present invention, the transmission of the clock in the semiconductor device is performed in the form of a 1 / 2f clock having a frequency of 1/2 of the clock used in the state storage circuit, so that the deterioration is small. In addition, since the generation of the 1f clock is performed in the vicinity of each element of the sequential circuit, the skew of the 1f clock received by each element from the 1f clock generation circuit is small, and the pulse width of the sliver clock is normal for the latch circuit. More than the minimum pulse width required to operate
The condition that it is necessary to be smaller than the sum of the delay amount in the latch circuit and the delay amount in the combinational circuit can be easily satisfied, and data penetration hardly occurs. Therefore, the restriction on the supply of the clock to each part of the sequential circuit in the semiconductor device is reduced.

The generation circuit for generating the 1f narrow pulse clock has a pulse width larger than the minimum pulse width necessary for the operation of the latch circuit, and the amount of delay in the preceding latch circuit and the input from the preceding latch circuit to the latch circuit. A pulse having a pulse width smaller than the total delay amount of the signal before the pulse is generated. When a combinational circuit that outputs data to be input to the latch circuit receives outputs from a plurality of state storage circuits, a pulse width in which the total delay amount is smaller than the minimum delay amount in the paths is set. I do. Actually, the generation circuit that generates the 1f narrow pulse clock is a delay circuit that delays the 1 / 2f clock by the delay amount in the latch circuit, and outputs an exclusive OR signal of the output of the delay circuit and the 1 / 2f clock. And an exclusive OR gate for outputting.

Since it is only necessary to generate a clock whose pulse width is within a predetermined range, 1/2 f is used as the clock.
It is sufficient to generate a pulse having a pulse width within a predetermined range at the rising and falling edges of the clock, and the circuit can be realized very easily. Therefore, this circuit simultaneously realizes two functions, that is, a multiplication for generating a clock of twice the frequency from the 1 / 2f clock and a pulse for generating a narrow pulse.

Further, when the narrow pulse generation circuit is constituted by a delay circuit and an exclusive OR gate, if the delay circuit is a circuit that generates a delay amount equal to the delay amount in the latch circuit, the pulse width of the narrow pulse can be increased. Is always larger than the minimum pulse width required for the latch circuit to operate. Therefore, with respect to variations in element manufacturing, and fluctuations in the operating environment such as temperature and power supply voltage,
Since the delay amounts of the delay circuit and the latch circuit always change with the same tendency, stable operation is possible.

When a master-slave flip-flop to which a transmission gate is added is used as the state storage circuit, there is no limitation on the pulse width unlike the latch circuit, but the duty of the large pulse width is close to 50%. When the clock is generated by the 1f clock generation circuit, the area of the delay means constituting this circuit must be increased. Therefore, even when a master-slave flip-flop with a transmission gate is used, a latch circuit is required. As in the above case, it is desirable to use a circuit that generates a 1f narrow pulse clock as the 1f clock generation circuit.

When the clock is supplied from the outside to the semiconductor device and the external clock supplied from the outside has the same frequency as the 1f clock used in the state storage circuit, the external clock is divided by １ ／. When a frequency dividing circuit is provided and the external clock supplied from the outside is a clock having a half frequency of the 1f clock such as a differential 1 / 2f clock signal, the input external clock is converted into 1 / f at the same frequency. Used as 2f clock signal. When the external clock is a differential 1 / 2f clock signal, a signal whose waveform has been shaped using a differential amplifier circuit (operational amplifier) or the like may be output as a 1 / 2f clock.

Japanese Unexamined Patent Publication No. Hei 7-321208 discloses an arrangement in which the skew to the final clock buffer of a clock system is reduced, and the elements of the sequential circuit are arranged within a predetermined range from the final clock buffer. Although a clock system with a small skew that reduces the constraint of the above is disclosed, it is desirable to perform such an arrangement also when transmitting a 1 / 2f clock of the present invention. In this case, in each group, a second position is determined within a first predetermined range based on the position of each 1f clock generation circuit, and a second position is determined within a second predetermined range based on the second position. A fixed number of state storage circuits may be arranged in a concentrated manner, or in each group, the state storage circuits may be arranged in a column, and a 1f clock generation circuit may be arranged near the center of the column of the state storage circuits. It is desirable to do.

Since the sequential circuit transfers data one stage at a time in accordance with the clock, when testing whether the sequential circuit or the combinational circuit operates normally, various input data are supplied and the output of the final stage at that time has a desired value. Is generally performed by detecting whether However, input data must pass through all stages of the sequential circuit before an output is obtained, and the time required for obtaining an output is long. There is a problem that it takes an enormous amount of time to test all combinations of input data because there are many combinations of. Therefore, the state storage circuit constituting the sequential circuit is set to the passing state so that the state storage circuit and the combination circuit operate as one combination circuit.
It is known that a test as to whether a sequential circuit or a combinational circuit operates normally can be performed by testing whether or not the circuit operates normally.

As shown in FIG. 4, the master-slave type flip-flop used conventionally has a latch circuit of two.
In order to forcibly switch to the pass state during the test, it is necessary to add a transmission gate or a transistor in addition to the conventional configuration, which causes a problem that the circuit scale is further increased. On the other hand, in the present invention, a latch circuit is used as an element of the sequential circuit, but the latch circuit can easily enter the passing state only by fixing the clock to one logical value. When a master-slave flip-flop circuit with a transmission gate is used, the transmission gate may be forcibly turned into a passing state by bypassing the transmission gate with a transistor or the like. Good. Therefore,
Even when the above-described test can be performed, the increase in the circuit scale is small.

Further, the CAD apparatus of the present invention automatically generates a clock system having the above configuration, and automatically assigns a master-slave flip-flop circuit to which a latch circuit or a transmission gate is added as a state storage circuit. When the latch circuit is used as the state storage circuit, the sum of the delay amount in the preceding latch circuit and the delay amount of the signal from the preceding latch circuit to the latch circuit is smaller than the pulse width of the 1f narrow pulse clock. If the above condition cannot be satisfied because of the small size, it is desirable to automatically assign a master-slave flip-flop circuit to which a transmission gate is added, and to assign a latch circuit otherwise.

Further, when there is a feedback loop composed of a state storage circuit and a combinational circuit, when the state storage circuit is set to the passing state, the state becomes similar to the oscillation.
It is generally known that testing becomes difficult. Therefore, when such a feedback loop exists, only the state storage circuit constituting the feedback loop is supplied with a normal 1f clock so that the normal 1f clock is supplied so as not to be forced into the passing state even during the test. Separate 1f clock generation circuit. If a large number of such feedback loops exist, the number of 1f clock generation circuits increases, and the test becomes difficult. However, such feedback loops are generally small in number and do not cause much problem.

In a semiconductor device having a large circuit scale, a circuit is divided into a plurality of circuit blocks. When such a semiconductor device is tested, a state memory circuit near input / output terminals of each circuit block is driven by a system clock. So that a test can be performed for each circuit block.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock system for a semiconductor device according to a first embodiment of the present invention has a configuration shown in FIG. 9 showing the principle configuration of the present invention. In the first embodiment, a latch circuit is used as a state storage circuit. As shown in FIG. 9, a state storage circuit 54 constituting a sequential circuit is provided from outside the semiconductor device.
Clock having a frequency half of that of a clock having a narrow pulse width (1f narrow pulse clock), ie, 1 / 2f
Clock is input. As an example of such a clock, an LVDS that supplies a differential signal having a half frequency of a clock used in a conventional semiconductor device is used.
There is a clock supply system called a (Low Voltage Differential Signal) system. In this LVDS system, 1
Since the complementary signal of the / 2f clock is input, as shown in FIG. 40, the waveform of the differential 1 / 2f clock input to the input terminals 511 and 512 is shaped using a differential amplifier (op-amp) 513 or the like. The signal may be output as a 1 / 2f clock via the buffer circuit 514. This one
The / 2f clock is input to a clock input terminal, and is taken into the semiconductor device by a clock buffer 51 provided near the clock input terminal. The captured 1 / 2f clock is distributed from the clock input buffer 51 to various parts in the semiconductor device. However, since the clock input buffer 51 alone has insufficient driving capability, a clock buffer 52 is provided in the middle as shown in the figure. Although the clock buffer 52 has only one stage in FIG. 9, it is generally provided in a plurality of stages.
At this time, it is desirable that the number of stages of the clock buffer 52 in the path to the distribution destination is the same and the length of the clock signal line is also approximately the same so as to reduce the skew generated in the distributed 1 / 2f clock. The 1f clock generation circuit 53 generates a 1f narrow pulse clock 1fCK having a double frequency from the 1 / 2f clock distributed in this way, and supplies the same to a latch circuit 54 constituting a neighboring sequential circuit. As described above, the 1f clock generation circuit 53 generates the 1f narrow pulse clock 1fCK.
The clock generation circuit 53 is referred to as a 1f narrow pulse clock generation circuit. As will be described later, the latch circuits are grouped together in the vicinity, and one group of latch circuits is provided with one 1f narrow pulse clock 53, from which a 1f narrow pulse clock 1fCK is supplied to each latch circuit. You.

FIG. 10 shows a 1f narrow pulse clock generation circuit 5
FIG. 11 is a time chart for explaining the generation of the 1f narrow pulse clock 1fCK in the first embodiment. Note that the external input clock signal 1 / 2f
Since the clock is directly distributed to the 1f narrow pulse clock generation circuit 53, the signal distributed to the 1f narrow pulse clock generation circuit 53 is shown as an external input clock signal 1 / 2f clock in FIG. As shown in FIG. 10, the 1f narrow pulse clock generation circuit 53 includes a delay circuit 61 for delaying the distributed 1 / 2fCK and a 1 / 2fC
K and an exclusive NOR (EXNOR) gate 62 to which the output of the delay circuit 61 is input. The output of the EXNOR gate 62 is a complementary 1f narrow pulse clock CK via inverters 63, 64 and 65. And XCK. As shown in FIG. 11, a pulse width having a width equal to the delay amount of the delay circuit 61 is generated at the rising and falling edges of 1 / 2fCK, so that a narrow pulse is generated at twice the frequency of 1 / 2fCK. Will be done. That is, the 1f narrow pulse clock generation circuit 53 of FIG.
The generation of the signal whose frequency is 1/2 fCK doubled and the generation of the sliver clock are performed simultaneously.

FIG. 12 is a diagram more specifically showing the configurations of the delay circuit and EXNOR gate of the 1f narrow pulse clock generation circuit 53 of FIG. Since the configuration of the EXNOR gate 73 is widely known, the description is omitted here.
The delay circuit 72 has a configuration similar to a latch circuit to be described later, and the delay amount in the delay circuit 72 is made substantially the same as that of the latch circuit. Thus, the condition that the pulse width of the generated sliver clock is equal to or longer than the minimum time required for the latch circuit to operate can be satisfied. The amount of delay in the circuit varies according to variations in device manufacturing and changes in the operating environment such as temperature and power supply voltage. However, since the delay circuit has the same configuration as the latch circuit, it always has the same tendency against such variations. , The above condition can be satisfied even with such a fluctuation.

FIGS. 13 and 14 are diagrams showing examples of the circuit configuration of the latch circuit. All the circuits other than the circuit shown in FIG. 13 (4) have a clear terminal for clearing the latched value. . In the circuits shown in (2) and (3) of FIG. 14, an inverter formed of a small-sized transistor is used as an inverter forming a feedback loop. The latch circuits shown in FIG. 13 and FIG. 14 are well-known circuits that have been used in the related art, and thus further description is omitted here.

FIG. 15 is a diagram showing an example of a circuit used when an output obtained by inverting input data is required as an output of a latch circuit. When the output is not inverted, the latch circuit shown in FIGS. 13 and 14 is used as it is, as shown in (1). When inverting the output, as shown in (2),
The data input to the latch circuit is inverted and then input. Here, it is conceivable to invert the output of the latch circuit. However, since the inverter for inverting the input data is included in the combination circuit provided between the latch circuit and the preceding stage, the inverter satisfies the condition of the 1f narrow pulse clock described above. It is preferable to use a configuration as shown in FIG.

In the first embodiment, the external clock is LVDS
Although the clock is a 1 / 2f clock according to the system or the like, it is general that a clock 1f having the same frequency as the 1f narrow pulse clock used in the state storage circuit and having a duty close to 50% is generally supplied. An example in which such an external clock is supplied will be described as a second embodiment. FIG. 16 is a diagram illustrating a configuration of a clock system of the semiconductor device according to the second embodiment. As is apparent from comparison with FIG. 9, the difference from the first embodiment is that a 1/2 frequency dividing circuit for dividing the clock 1f output from the clock input buffer 91 into 1/2 is provided.
A master-slave flip-flop circuit (DM-F) in which a clock is generated and a transmission gate is added as a dynamic master latch circuit to an input portion of the latch circuit as well as a latch circuit as a state storage circuit
F) is also used.

FIG. 17 is a timing chart showing the clock of each section in the second embodiment. As shown in FIG. 17, the external input clock signal 1fCK is frequency-divided by な り into ｆfCK, and distributed to the 1f narrow pulse clock generation circuit 94 in each part in the semiconductor device. The 1f narrow pulse clock generation circuit 94 has the same configuration as the circuits shown in FIGS. 10 and 12, and generates a clock having a narrow pulse width of twice the frequency, that is, a 1f narrow pulse clock from the distributed 1 / 2fCK. Then, the data is supplied to the state storage circuit 95.

As described above, in the present invention, the 1f narrow pulse clock generation circuit 94 is provided near the state storage circuit that supplies the 1f narrow pulse clock therefrom. The condition for normal operation without the occurrence of punch-through can be easily satisfied. However, there may be a case where it is necessary to supply a 1f narrow pulse clock from the 1f narrow pulse clock generation circuit 94 which is not in the vicinity of the state storage circuit due to layout restrictions. In such a case, the pulse width of the 1f narrow pulse clock described above is larger than the minimum pulse width necessary for the operation of the latch circuit, and the amount of delay in the previous-stage latch circuit and the previous-stage latch circuit It may not be possible to satisfy the condition that it is smaller than the total amount of delay of the signal from the input to the latch circuit. In the second embodiment, in such a case, instead of the latch circuit, a master-slave flip-flop circuit (DM-FF) in which a transmission gate is added as a dynamic master latch circuit at the input of the latch circuit is used.

FIG. 18 is a diagram showing a circuit configuration of a master-slave flip-flop circuit (DM-FF) to which a transmission gate is added as a dynamic master latch circuit, wherein (1) shows an equivalent circuit, and (2) shows an equivalent circuit. An example of an actual circuit is shown. FIG. 19 shows a DM-F without a clear function.
FIG. 4 is a diagram illustrating a circuit example of F. As shown, DM-FF
Has a simple configuration in which a transmission gate is provided in a latch circuit, and has a smaller circuit size than a normal master-slave flip-flop. However, since the DM-FF operates as a flip-flop, the delay amount in the combinational circuit is small in the second embodiment, making it difficult to realize the above condition. Use FF. Detailed description of the DM-FF shown in FIGS. 18 and 19 is omitted.

In the first embodiment, a latch circuit is used as a state storage circuit.
Although M-FFs were used together, D
Only M-FF may be used. Even with such a configuration, the circuit configuration is simpler than that of the conventional master-slave flip-flop circuit shown in FIG. 4, so that the circuit scale can be reduced and power consumption can be reduced. With this configuration, it is not necessary for the 1f clock to generate a 1f narrow pulse clock having a narrow pulse width. However, when the circuit shown in FIG. 10 is used as the 1f clock generation circuit, in order to generate a clock having a large pulse width, the delay circuit 61 needs to generate a large amount of delay. Therefore, it is desirable to use a circuit that generates a 1f narrow pulse clock as the 1f clock generation circuit as in the above embodiment.

The above is the description of the first and second embodiments of the semiconductor device having the semiconductor device clock system of the present invention. Currently, the design of such circuits is performed using CAD equipment. Next, a CAD system in which the clock system shown in the first and second embodiments is automatically generated.
First, the basic processing in the CAD apparatus will be described.

FIG. 20 is a block diagram schematically showing an entire configuration of a CAD apparatus for automatically arranging circuit elements of a semiconductor device and designing wiring between them, and FIG. (B) functionally shows a mechanical device. As shown in FIG. 20A, the CAD device includes an input device 301 and a display device 30.
2, a storage device 303, and a processing device 304. The input device 301 is used by an operator to give a command to a CAD device by performing a predetermined operation, and includes a keyboard, a mouse, a tablet, and the like. Display device 302
Displays various images, and an operator performs an operation while checking images on the display device 302. The processing device 304 performs predetermined processing in accordance with instructions and data input from the input device 301 and various information from the storage device 303, and sequentially displays images on the display device 302. As shown in FIG. 20B, the storage device 303 stores the combinational circuit information 3 such as a net list.
31, wiring attribute information 332 for distinguishing a clock or a signal, resource information 333 of information on components (physical pattern and terminal information, etc.) necessary for a chip, and a program 334 for processing procedures (arrangement and wiring procedures), etc. Contains.

FIG. 21 is a flowchart showing an example of a placement and routing process in a conventional CAD device. As shown in the figure, in step 901, RTL (resistance transistor combination circuit) design data is generated, in step 902, logic synthesis is performed based on the RTL design data, and in step 903, gate-level design data is generated. Is performed to determine the layout and wiring of circuit elements, and mask data is generated in step 905. When generating the RTL design data and the gate level design data, a simulation 906 is performed as needed.

FIG. 22 is a flowchart showing processing in a CAD device for realizing the clock system of the present invention. A DM-FF is assigned to a latch circuit as a state storage circuit, and a 1f clock generation circuit is a 1f narrow pulse clock (swing). This is an example of a case where a (river clock) is generated. As is apparent from comparison with FIG. 21, the difference is that, after the gate level design data is generated in step 912, the clock scheme (sliver clock scheme) is narrowed based on the gate level design data in step 913. Is performed, and sliver clock type gate level design data is generated in step 914. That is, conversion processing to the sliver clock method is performed on the gate level design data.

FIG. 23 is a flowchart showing another process in the CAD apparatus according to the present invention, which is different from FIG. 22 in that the process of converting the RTL design data into the sliver clock method is performed. Yes, step 921
The RTL design data is converted to the sliver clock method in step 922, and sliver clock RTL design data is generated in step 922. In step 923, the logic synthesis processing is performed. Sliver clock type gate level design data is generated. The sliver clock type gate level design data is the same as the design data generated in step 914 of FIG. 22, and the layout is similarly performed in step 925 and the mask data is generated in step 926. Also in this case, a simulation is performed on the RTL design data and the gate level design data.

FIG. 24 shows a CAD apparatus according to the present invention.
At the time of the conversion process to the sliver clock method, a latch circuit is used as an element of the sequential circuit or a DM-FF
FIG. 25 is a flowchart showing a process of selecting whether or not to use. FIG. 25 to FIG. 27 are diagrams for explaining this process. As already described, the pulse width of the 1f narrow pulse clock is larger than the minimum pulse width necessary for the operation of the latch circuit, and the delay amount in the preceding latch circuit and the signal from the preceding latch circuit to this latch circuit. If the condition of being smaller than the total amount of delay of the signal before input cannot be satisfied, a DM-FF is used, and in other cases, a latch circuit is used.

In step 930, a state storage circuit of interest is selected as shown in FIG. The circuit 115 is the state storage circuit of interest in this case. In step 931, as shown in FIG. 26, all the signal paths related to the delay of the data input to the circuit 115 are searched, and the delay time of each path is calculated. In the example of the figure, data from the combination circuit 114 is input to the circuit 115,
The outputs of the preceding circuits (latch circuits or DM-FFs) 111, 112 and 113 are input to the combination circuit 114, and the output data of the combination circuit 114
Determined by the outputs of the two circuits 111, 112 and 113. Therefore, three paths from the outputs of the three circuits 111, 112 and 113 to the output of the combinational circuit 114 are problematic, and the delay time of each path is calculated. Specifically, a delay A occurs in the circuit 111 and the combinational circuit 11
4, a delay a occurs, so that the total delay amount is A + a. Similarly, the total delay until the output of the circuit 112 affects the input of the circuit 115 is B + b, and the total delay until the output of the circuit 113 affects the input of the circuit 115 is C.
+ C. When the type of the state storage circuit, that is, whether the circuit is a latch circuit or a DM-FF, is not determined, the value of the state storage circuit having the least delay among the types of the state storage circuit used as the worst case for convenience is used. .
Further, the delay time when the signal reaches the input terminal of the circuit 115 is the delay of the combinational circuit until reaching the input terminal, and includes the delay of the input buffer.

In step 932, as shown in FIG. 27, a path having the minimum delay time among the above three paths is determined. Since the problem here is data penetration, 3
The delay time of the shortest path from the outputs of the circuits 111, 112 and 113 to the output of the combinational circuit 114 is a problem. Here, since the output of the circuit 111 is the shortest path, the delay time A + a is to be determined.

In step 933, the pulse width of the sliver clock is compared with the shortest delay time obtained in step 932. If the delay time of the shortest path is larger, a latch circuit is applied as the circuit 115 in step 934,
If the delay time of the shortest path is shorter, there is a possibility of data penetration, and therefore, in step 935, a DM-FF is applied as the circuit 115. Such processing is performed for all elements of the state storage circuit.

The same processing can be performed when only one of the DM-FFs is assigned to the latch circuit as the state storage circuit. When only the DM-FF is used, it is not necessary to generate a 1f clock having a narrow pulse width. However, as described above, it is preferable to generate a 1f narrow pulse clock also in this case. The above is the description of the CAD apparatus of the present invention. An example of generation of a clock system generated by such a CAD apparatus will be described in comparison with a conventional example.

FIG. 28 is a diagram showing an example of generation of a clock system when a clock 1fCK is supplied as an external clock generated by a conventional CAD apparatus. FIG.
As shown in FIG. 8, the clock 1fCK supplied to the clock input terminal 121 is input to the clock input buffer 122, and is supplied to the flip-flop 125 forming the sequential circuit via the clock buffers 123 and 124 of a plurality of stages. Therefore, the clock is a signal of the same frequency from the clock input terminal 121 to the flip-flop 125.

On the other hand, when the generation example of FIG. 28 is applied to the CAD apparatus of the present invention, a configuration as shown in FIG. 29 is obtained. As shown in FIG. 29, the clock input terminal 121
Of the clock 1fCK supplied to the
A 1/2 frequency dividing circuit 132 for generating fCK is newly provided, and 1 / 2fCK is supplied to a 1f clock generating circuit 135 provided for each state memory circuit group via clock buffers 133 and 134. Here, a latch circuit or a DM-FF is used as the state storage circuit, and a 1f narrow pulse clock generation circuit 135 that generates a 1f narrow pulse clock is generated as the 1f clock generation circuit 135. The 1f narrow pulse clock having the same frequency as the clock 1fCK, which is a complementary signal generated by the 1f narrow pulse clock generation circuit 135, is supplied to the latch circuit or the DM-FF 138 which is an element of the sequential circuit via the buffers 136 and 137. . Therefore, 1 /
Between the 2 frequency dividing circuit 132 and the 1f narrow pulse clock generating circuit 135 to each element of the sequential circuit, the frequency is transmitted as the frequency of the clock 1fCK, and the 1/2 frequency dividing circuit 1
Between 32 and each 1f narrow pulse clock generation circuit 135, the signal is transmitted as a signal having a half frequency of the clock 1fCK.

FIG. 30 is a diagram showing an example of generation of a clock system in the case where the above-described LVDS system clock is supplied as an external clock generated by a conventional CAD apparatus. As shown in FIG. 30, the clock input terminal 141
The clock ｆfCK supplied to the clocks 142 and 142 is input to the frequency multiplier 143, the frequency of which is doubled, and the two-phase signal is converted into a one-phase signal 1fCK and input to the clock input buffer 144. Clock input buffer 144
Are output from a plurality of clock buffers 145 and 146.
, A flip-flop 147 constituting a sequential circuit
Supplied to

On the other hand, when the example of FIG. 30 is applied to the CAD apparatus of the present invention, a configuration as shown in FIG. 31 is obtained. As shown in FIG. 31, the clock input terminal 151
And the clock 1 / 2fCK supplied to the clock 152 are shown in FIG.
The two-phase signal is converted into a one-phase signal by the phase conversion circuit 153 as shown in FIG. Here, since the frequency is not multiplied, the phase conversion circuit 153 outputs the clock 1 / 2fCK having the same frequency as the external clock. This 1 / 2f
CK is supplied via clock buffers 154 and 155 to a 1f narrow pulse clock generation circuit 156 provided for each group of state storage circuits forming a sequential circuit. Other parts are the same as the example shown in FIG.

As shown in FIGS. 29 and 31, according to the present invention, the 1f narrow pulse clock generation circuit 156 is provided in the vicinity of a group obtained by dividing the elements constituting the sequential circuit, and the element of the sequential circuit in the group is provided. Is supplied with the 1f narrow pulse clock from the corresponding 1f narrow pulse clock generation circuit 156, so that the above condition can be easily satisfied. However, the clock 1 / 2fCK supplied from the clock input buffer is converted into each 1f narrow pulse. If there is a large skew when the clock generation circuit 156 receives the clock, there is a problem that the entire operation is not synchronized. Therefore, the clock input buffer sends a clock 1/2 to each 1f narrow pulse clock generation circuit 156.
The path for supplying fCK needs to have a small skew. As a clock system with low skew, the paths from the clock source such as a clock input buffer to each element of the sequential circuit are equidistant and the number of buffers provided in the middle is the same, so that the skew is reduced. An H-tree-like clock wiring path to reduce the size is known. However, such a clock system has a problem that the arrangement of the state storage circuit and the buffer is largely restricted. To solve such a problem, Japanese Patent Application Laid-Open No. 7-3 is disclosed.
Japanese Patent Application Laid-Open No. 21208 discloses a configuration in which arrangement and wiring are performed so as to have a small skew up to the final clock buffer, and a state storage circuit is arranged within a predetermined range from the final clock buffer. In this case, the restriction on the arrangement of the state storage circuit is greatly eased. Here, such a clock system is referred to as a CDDM system. The CAD apparatus of the present invention also uses such a CDDM system.

FIG. 32 is a diagram showing an arrangement of a final clock buffer (local clock buffer) 161 and a state storage circuit in a clock distribution system configured according to the CDDM system. Arrangement and wiring are performed so as to have a small skew from the clock source to the local clock buffer 161. The state storage circuit is a flip-flop, and is arranged within a predetermined range from the local clock buffer 161. As shown, the state storage circuit is divided into four groups of 162, 163, 164, and 165, and a clock is supplied to each group by four wires extending from the local clock buffer 161. As a matter of course, the clock supplied from the clock source to the local clock buffer 161 is the same as the clock supplied from the local clock buffer 161 to each flip-flop, and the local clock buffer 161 is merely a buffer, Etc. are not performed.

FIG. 33 shows a conventional CD as shown in FIG.
FIG. 3 is a diagram showing an example obtained by applying the present invention to a clock distribution system of a DM system, wherein (1) shows a case where a local clock buffer is provided by a 1f narrow pulse clock generation circuit 17;
(2) is an example in which 1f narrow pulse clock generation circuits 182, 184, 186, and 188 are arranged at the center of each group of the state storage circuits 183, 185, 187, and 189. The state storage circuit in this case is a latch circuit or a DM-FF. The clock is transmitted in the form of 1/2 fCK from the clock source to the 1f narrow pulse clock generation circuit. The 1f narrow pulse clock generation circuit generates 1f narrow pulse clock from 1 / 2fCK and supplies it to each state storage circuit. I do. In the example of (1),
Only one 1f narrow pulse clock generation circuit 171 needs to be provided for the number of state storage circuits shown. In the example of (2), four 1f narrow pulse clock generation circuits are provided.
Since the load driven by the 1f narrow pulse clock generation circuit is reduced, there is an advantage that the waveform of the 1f narrow pulse clock is less deteriorated.

As described above, when testing whether the sequential circuit or the combinational circuit operates normally, each state storage circuit of the sequential circuit is set to the passing state, and the sequential circuit and the combinational circuit operate as one combinational circuit. It is known that the test can be easily performed. The semiconductor device of the present invention can easily perform such a test, and the CAD device generates a circuit that can perform such a test.

FIG. 34 is a diagram showing a basic configuration of a semiconductor device test method to which the present invention is applied. During testing,
As shown in the drawing, the state storage circuit unit 201 is set in the passing state so as to operate as a combination circuit, and to operate integrally with the original combination circuit 202 as one combination circuit. Then, a test signal is given as an input signal, and it is confirmed whether the output signal of the final stage at that time has a desired value.

In order to be able to perform the above test, it is necessary to make the state storage circuit passable at the time of the test.
Since the latch circuit enters a passing state only by fixing the clock to one logical value, it is sufficient that the 1f narrow pulse clock can be fixed to a logical value that causes the latch circuit to pass in the test state. FIG. 35 is a diagram showing a configuration of a 1f narrow pulse clock generation circuit with a test mode capable of performing the above test. As shown, the circuit of FIG.
A D gate 213 is added, and the output C
The point is that K is fixed at “high (H)” and XCK is fixed at “low (L)”. As a result, the latch circuit to which the clock from the 1f narrow pulse clock generation circuit is applied enters the pass state in the test mode. FIG. 36 is a diagram showing a specific circuit configuration of FIG.

In the present invention, DM-
When an FF is used, and particularly when a latch circuit is used, data penetration occurs, a DM-FF is used. This D
The M-FF does not enter the passing state simply by fixing the clock to one logical value. Therefore, it is necessary to force the DM-FF into the passing state in the test mode. FIG. 37 is a diagram showing a configuration of a DM-FF that can pass in the test mode, (1) shows an equivalent circuit, and (2) shows a specific circuit example. As shown, the circuit of FIG.
A transistor 223 that is turned on in response to the test mode signal is provided in parallel with the transmission gate 221.
It is possible to bypass. As described above, a DM-FF capable of performing the above test can be realized with a very simple circuit in which only a transistor is added.

Further, as described above, as shown in FIG. 38, the state storage circuit section 246 and the combinational circuit 242
It is generally known that when there is a feedback loop 248 constituted by the following equation, the state becomes similar to the oscillation when the state storage circuit is set to the passing state, and the test becomes difficult. Therefore, when such a feedback loop exists, as shown in FIG. 39, only the state storage circuit 246 forming the feedback loop 248 is forcibly set so as not to be forced into the passing state even during the test.
An ordinary narrow clock is supplied. Specifically, a circuit as shown in FIG. 10 is used as a 1f narrow pulse clock generation circuit for supplying a 1f narrow pulse clock to such a state storage circuit 246, and a 1f narrow pulse clock is stored in another state storage circuit. A circuit as shown in FIG. 35 is used as a 1f narrow pulse clock generation circuit for supplying the clock signal. When the state storage circuit included in such a feedback loop is a DM-FF, the circuit shown in FIG. 18 is used and the circuit shown in FIG. 37 is not used.
In this case, there is no need to provide a separate 1f narrow pulse clock generation circuit.

In the example described so far, the 1f clock generation circuit or the 1f narrow pulse clock generation circuit generates the 1f clock or 1f narrow pulse clock that is a two-phase complementary signal, that is, two-phase complementary clocks CK and XCK. It has been supplied to a state storage circuit such as a latch circuit or a DM-FF. However, a 1f clock generation circuit or a 1f narrow pulse clock generation circuit generates a 1-phase 1f clock or a 1f narrow pulse clock and supplies it to the state storage circuit. A circuit part for generating the two-phase complementary clocks CK and XCK may be arranged inside the state storage circuit.

FIGS. 41 to 48 are circuit diagrams showing modified examples in which a circuit portion for generating two-phase complementary clocks CK and XCK is provided inside the state storage circuit. FIG.
FIG. 7 is a diagram corresponding to FIG. 6 and shows a configuration example of a sequential circuit in a state storage circuit in this modified example. FIG.
A diagram corresponding to FIG. 29 shows a generation example of the clock system of this modification. FIG. 43 is a view corresponding to FIG. 10 and shows a configuration example of a narrow clock generation circuit in this modification. FIG. 44 is a diagram corresponding to (2) in FIG. 13 and shows a configuration example of a latch circuit in this modification. FIG.
Is a diagram corresponding to (1) in FIG. 18 and shows a configuration example of a DM-FF in this modified example. FIG. 46 is a view corresponding to FIG. 35 and shows a configuration example of a narrow-width clock generation circuit with a test mode in this modification. FIG. 47 is a diagram corresponding to FIG. 37 and shows a configuration example of a DM-FF with a test mode in this modification. FIG. 48 is a diagram corresponding to FIG. 33 and is a diagram illustrating a configuration example of a clock distribution system in this modification.

As shown in FIGS. 41 to 48, in this modification, the 135f, 171 ', 182', and 18f clock generation circuits or the 1f narrow pulse clock generation circuit are used.
In 4 ', 186' and 188 ', one-phase 1f clock or 1f narrow pulse clock is generated and supplied to the state storage circuit, and each state storage circuit includes a circuit for generating two-phase complementary clocks CK and XCK. I have. Detailed description of each figure is omitted.

[0068]

As described above, according to the present invention,
Since the operating frequency of most parts of the clock system for transmitting the clock is reduced by half, the power consumption of this part can be greatly reduced. Further, the circuit scale of the sequential circuit is almost half, and a circuit with significantly reduced power consumption can be easily realized.

When a latch circuit is used as the state storage circuit, it is not necessary to add a new circuit to the state storage circuit for the test, and the test can be easily performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional example of a clock system for transmitting a clock.

FIG. 2 is a timing chart showing operation timing in a conventional clock system.

FIG. 3 is a diagram showing a configuration of a normal sequential circuit using flip-flops.

FIG. 4 is a diagram illustrating a configuration of a flip-flop.

FIG. 5 is a time chart showing an operation of a normal sequential circuit using a flip-flop.

FIG. 6 is a diagram showing a configuration of a sequential circuit using a latch circuit.

FIG. 7 is a time chart showing an operation of a sequential circuit using a latch circuit.

FIG. 8 is a diagram illustrating an example of a clock system when a latch circuit and a narrow clock (sliver clock) are used.

FIG. 9 is a principle configuration diagram of a clock system of the present invention.

FIG. 10 is a diagram showing a configuration of a circuit for generating a narrow clock (sliver clock).

FIG. 11 is a time chart for explaining generation of a narrow clock (sliver clock) in the first embodiment.

FIG. 12 is a diagram showing a specific configuration of a circuit for generating a narrow clock (sliver clock).

FIG. 13 is a diagram illustrating a configuration example of a latch circuit.

FIG. 14 is a diagram illustrating a configuration example of a latch circuit.

FIG. 15 is a diagram illustrating a configuration example of an inverted output latch circuit;

FIG. 16 is a diagram illustrating a configuration of a clock system according to a second embodiment.

FIG. 17 is a time chart showing a clock in the second embodiment.

FIG. 18 is a diagram illustrating a configuration of a DM-FF.

FIG. 19 is a diagram showing a specific circuit configuration of a DM-FF.

FIG. 20 is a diagram showing a configuration of a conventional CAD device.

FIG. 21 is a diagram showing processing in a conventional CAD device.

FIG. 22 is a diagram showing processing in the CAD device of the present invention.

FIG. 23 is a diagram showing another process in the CAD device of the present invention.

FIG. 24 shows a latch circuit and D in the CAD device of the present invention.
It is a flowchart which shows the selection process of M-FF.

FIG. 25 shows a latch circuit and a DM-FF in a CAD device.
It is an explanatory view of the selection processing.

FIG. 26 shows a latch circuit and a DM-FF in a CAD device.
It is an explanatory view of the selection processing.

FIG. 27 shows a latch circuit and a DM-FF in a CAD device.
It is an explanatory view of the selection processing.

FIG. 28 is a diagram showing an example of generating a clock system by a conventional CAD device.

FIG. 29 is a diagram illustrating an example of generating a clock system by the CAD device of the present invention.

FIG. 30 is a diagram illustrating an example of generation of a clock system by a conventional CAD device.

FIG. 31 is a diagram showing an example of generating a clock system by the CAD device of the present invention.

FIG. 32 is a diagram illustrating an example of a clock distribution system according to a conventional example.

FIG. 33 is a diagram showing an example of a clock distribution system according to the present invention.

FIG. 34 is a diagram showing a basic configuration of a test method of a semiconductor device to which the present invention is applied.

FIG. 35 is a diagram showing a configuration of a 1f narrow pulse clock generation circuit with a test mode.

FIG. 36 is a diagram showing a specific configuration of a 1f narrow pulse clock generation circuit with a test mode.

FIG. 37 is a diagram showing a circuit configuration of a DM-FF with a test mode.

FIG. 38 is a diagram showing a signal path in a normal operation when a feedback loop is formed by a combination circuit of a sequential circuit.

FIG. 39 is a diagram showing a signal path at the time of a test when a feedback loop is formed by a combination of sequential circuits.

FIG. 40 is a circuit diagram showing a configuration of a 1 / 2f clock source when a differential 1 / 2f clock is supplied from outside.

FIG. 41 is a diagram illustrating a configuration example of a state storage circuit in a modification in which a two-phase complementary clock is generated in a cell of the state storage circuit.

FIG. 42 is a diagram illustrating a generation example of a clock system according to a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

FIG. 43 is a diagram showing a configuration example of a narrow-width clock generation circuit in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

FIG. 44 is a diagram illustrating a configuration example of a latch circuit in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

FIG. 45 is a diagram illustrating a configuration example of a DM-FF in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

FIG. 46 is a diagram showing a configuration example of a narrow-width clock generation circuit with a test mode in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

FIG. 47 shows a DM-FF with a test mode in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.
FIG. 3 is a diagram showing an example of the configuration of FIG.

FIG. 48 is a diagram illustrating a configuration example of a clock distribution system in a modification in which a two-phase complementary clock is generated in a cell of a state storage circuit.

[Explanation of symbols]

 51: Clock input terminal + clock input buffer 52: Clock buffer 53: 1f narrow pulse clock generation circuit 54: Element of sequential circuit (latch circuit or DM-FF)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822 H01L 21/82 C H03K 3/037 27/04 T

Claims (39)

[Claims] 1. A state storage circuit that operates in synchronization with a clock, a 1 / 2f clock source that outputs a 1 / 2f clock having a half frequency of a 1f clock used in the state storage circuit, A clock transmission path for transmitting the 1 / 2f clock output from the / 2f clock source; and a 1f which is provided near the state storage circuit and multiplies the 1 / 2f clock transmitted by the clock transmission path. And a 1f clock generation circuit for generating a clock, wherein the 1f clock generated by the 1f clock generation circuit is supplied to the state storage circuit. 2. The clock system according to claim 1, wherein at least a part of the state storage circuit is clocked by a 1f narrow pulse clock having a predetermined narrow pulse width, thereby forming an edge trigger type register circuit and A clock system that is a latch circuit that performs the same logical function operation. 3. The clock system according to claim 2, wherein at least a part of the state storage circuit other than the latch circuit has a transmission gate added as a dynamic master latch circuit to an input portion of the latch circuit. A clock system that is a slave flip-flop circuit. 4. The clock system according to claim 2, wherein the 1f clock generation circuit generates the 1f narrow pulse clock from the 1 / 2f clock transmitted on the clock transmission path. . 5. The clock system according to claim 4, wherein a pulse width of the 1f narrow pulse clock is larger than a minimum pulse width required for operating the latch circuit.
A clock system that is smaller than the sum of the delay amount in the preceding latch circuit and the delay amount of a signal from the preceding latch circuit to the latch circuit. 6. The clock system according to claim 5, wherein the 1f clock generation circuit delays the 1 / 2f clock by a delay amount in the latch circuit, and outputs the delay circuit output from the delay circuit. A clock system comprising: an exclusive OR gate that outputs an exclusive OR signal with a 1 / 2f clock. 7. The clock system according to claim 3, wherein when the logic value of the 1f narrow pulse clock is set to a logic value that allows the latch circuit to pass, the dynamic master latch type flip-flop circuit And a circuit for setting the dynamic master latch circuit therein to a passing state. 8. The clock system according to claim 2, wherein a part of said 1f clock generation circuit causes said latch circuit to pass said 1f narrow pulse clock. A clock system that can be fixed to a value. 9. The master-slave flip-flop according to claim 1, wherein at least a part of the state storage circuit has a transmission gate added as a dynamic master latch circuit to an input of a latch circuit. A clock system that is a circuit. 10. The clock system according to claim 9, wherein the 1f clock generation circuit generates a 1f narrow pulse clock having a predetermined narrow pulse width from the 1 / 2f clock transmitted through the clock transmission path. Clock system. 11. The clock system according to claim 9, wherein the dynamic master latch type flip-flop circuit includes a circuit for setting the dynamic master latch circuit to a passing state. 12. The clock system according to claim 11, wherein the part of the 1f clock generation circuit fixes the 1f clock to a logical value at which the dynamic master latch type flip-flop circuit passes. Clock system that has the function of 13. The clock system according to claim 1, wherein the 1 / 2f clock source divides an external clock supplied from outside by １ ／. A clock system with a circuit. 14. The clock system according to claim 1, wherein the ｆf clock source is a differential signal supplied from the outside.
/ 2f clock signal at the same frequency,
A clock system that outputs as f clock. 15. A semiconductor device comprising the clock system according to claim 1, wherein the state storage circuit is divided into a plurality of groups including elements arranged in the vicinity. The delay amount of the 1 / 2f clock transmitted from the 1 / 2f clock source to each of the plurality of groups through the clock transmission path is substantially equal, so that the delay amount does not cause a timing error such as a hold error. Wherein the 1f clock generation circuit is provided in each of the plurality of groups. 16. The semiconductor device according to claim 15, wherein, in each group, a second position is determined within a first predetermined range based on a position of each 1f clock generation circuit. A semiconductor device in which a predetermined number of the state storage circuits are intensively arranged in a second predetermined range based on the position of the state storage circuit. 17. The semiconductor device according to claim 15, wherein, in each group, said state storage circuits are intensively arranged in a column, and said 1f clock generation circuit is arranged at a center of a column of said state storage circuit. A semiconductor device arranged in the vicinity. 18. A state storage circuit which is a latch circuit which at least partially performs a logic function operation equivalent to that of an edge trigger type register circuit by clocking with a 1f narrow pulse clock having a predetermined narrow pulse width; A 1 / 2f clock source for outputting a 1 / 2f clock having a frequency of 1/2 of a 1f clock used in the state storage circuit, and a clock transmission for transmitting the 1 / 2f clock output from the 1 / 2f clock source. A 1f clock generation circuit provided near the latch circuit and configured to generate the 1f narrow pulse clock from the 1 / 2f clock transmitted through the clock transmission path. A test method for a semiconductor device including a clock system in which the 1f narrow pulse clock is supplied to the state storage circuit. At the time of the test, the 1f clock generation circuit is set to output a signal fixed to a logic value at which the latch circuit passes, and the output value of the final stage at that time is measured and matched with the desired value. How to test semiconductor devices. 19. The method for testing a semiconductor device according to claim 18, wherein at least a part of the state storage circuit other than the latch circuit is provided as a dynamic master latch circuit at an input of the latch circuit. And the above 1
When the narrow pulse clock is set to a logic value that allows the latch circuit to pass, the dynamic master latch circuit is configured to pass the logic master latch circuit. A test method for a semiconductor device in which a master-slave type flip-flop circuit to which a syngate is added also measures an output value of a final stage when the flip-flop circuit is in a passing state and checks whether the output value matches a desired value. 20. The method for testing a semiconductor device according to claim 18 or 19, wherein when a feedback loop including the state storage circuit exists, each of the feedback loops included in the feedback loop during a test. A semiconductor device that supplies the 1f narrow pulse clock to at least one of the state storage circuits and supplies the other clocks supplied to the state storage circuit to a logic value that causes the element to be in a passing state. Test method. 21. A state storage circuit which is a master-slave flip-flop circuit which operates at least in part in synchronization with a 1f clock with a transmission gate added as a dynamic master latch circuit at an input portion of the latch circuit; A 1 / 2f clock source for outputting a 1 / 2f clock having a frequency of 1/2 of a 1f clock used in the state storage circuit, and a clock for transmitting the 1 / 2f clock output from the 1 / 2f clock source A transmission path, and a 1f clock generation circuit provided near the latch circuit and configured to generate the 1f clock from the 1 / 2f clock transmitted through the clock transmission path.
The 1f clock generated by the clock generation circuit is supplied to the state storage circuit, and the master-slave type flip-flop circuit to which the transmission gate is added causes the dynamic master latch when the 1f clock is fixed to one logic state. A test method for a semiconductor device comprising a clock system having a circuit for passing a circuit, wherein during the test, the 1f clock generation circuit outputs a signal fixed to a logic value at which the latch circuit passes. A test method for a semiconductor device in which a set value is measured, and an output value of a final stage at that time is measured to confirm whether the output value matches a desired value. 22. The method of testing a semiconductor device according to claim 21, wherein when a feedback loop including the dynamic master latch type flip-flop circuit exists, each of the feedback loops is tested at the time of testing. The 1f clock is supplied to at least one of the included master-slave flip-flop circuits to which the transmission gate is added, and the other 1f clock is supplied to the other master-slave flip-flop circuits to which the transmission gate is added. A test method for a semiconductor device, wherein a clock signal is supplied while being fixed to a logical value that causes the circuit to pass. 23. An input device for inputting predetermined data,
A clock for supplying a clock to a state storage circuit operating in synchronization with a clock, comprising: a storage device storing predetermined data; and a processing device executing a process in accordance with the data from the input device and the storage device. A CAD apparatus for automatically generating logic circuit data of a system, wherein at least a part of the state storage circuits are clocked by a 1f narrow pulse clock having a predetermined narrow pulse width, so that an edge trigger type register circuit is provided. An element allocating means for allocating a latch circuit that performs a logical function operation equivalent to the above, and 1 / (1/2) of a frequency of 1/2 of the 1f narrow pulse clock transmitted by a clock transmission path near the latch circuit.
A CAD apparatus comprising: a 1f clock generation circuit that generates the 1f narrow pulse clock from the 2f clock. 24. The CAD apparatus according to claim 23, further comprising a clock source generating unit that generates a 1 / 2f clock source that supplies the 1 / 2f clock. 25. The CAD apparatus according to claim 23, further comprising a clock transmission path generating unit that transmits the 1 / 2f clock output from the 1 / 2f clock source. 26. The CAD device according to claim 23, wherein the 1f narrow pulse clock generated by the 1f clock generation circuit is supplied to a nearby state storage circuit. A CAD apparatus further comprising wiring generation means. 27. The CAD device according to claim 23, wherein the element allocating unit includes an input unit of a latch circuit in at least a part of the state storage circuits other than the latch circuit. And a master-slave flip-flop circuit to which a transmission gate is added as a dynamic master latch circuit. 28. The CAD apparatus according to claim 27, wherein said element allocating means calculates a delay amount in a preceding latch circuit and a delay amount of a signal from the preceding latch circuit to the latch circuit. When the sum is larger than the pulse width of the 1f narrow pulse clock, the latch circuit is assigned as the state storage circuit, and when the sum is smaller than the pulse width of the 1f narrow pulse clock, the transmission gate is added as the state storage circuit. A CAD device to which a master-slave flip-flop circuit is assigned. 29. The CAD device according to claim 27, wherein said element allocating means includes: a master-slave flip-flop circuit to which said transmission gate not included in a feedback loop is added; A CAD device to which a master-slave flip-flop circuit to which a transmission gate having a function of passing a state is added when a pulse clock is set to a logical value that allows the latch circuit to pass therethrough. 30. The CAD device according to claim 23, wherein said generating means of said 1f clock generating circuit stores said 1f narrow pulse clock in said state storage circuit not included in a feedback loop. A CAD apparatus in which a 1f clock generation circuit with a test mode having a function of fixing an output to a logical value that allows the state storage circuit to pass is disposed in the 1f clock generation circuit that supplies the clock signal. 31. An input device for inputting predetermined data,
A clock for supplying a clock to a state storage circuit operating in synchronization with a clock, comprising: a storage device storing predetermined data; and a processing device executing a process in accordance with the data from the input device and the storage device. A CAD device for automatically generating a logic circuit data of a system, wherein at least a part of the state storage circuit is provided with a transmission gate as a dynamic master latch circuit at an input portion of the latch circuit, and at 1f clock. Element allocating means for allocating an operating master-slave flip-flop circuit; and generating the 1f clock from a ｆf clock having a frequency １ ／ of the 1f clock transmitted by a clock transmission path near the state storage circuit. And a generating means for a 1f clock generating circuit. Location. 32. The CAD apparatus according to claim 31, further comprising a clock source generating unit that generates a 1 / 2f clock source that supplies the 1 / 2f clock. 33. The CAD apparatus according to claim 31, further comprising a clock transmission path generating unit that transmits the 1 / 2f clock output from the 1 / 2f clock source. 34. The CAD device according to claim 31, wherein the 1f clock wiring that supplies the 1f clock generated by the 1f clock generation circuit to a nearby state storage circuit. A CAD apparatus further comprising a generation unit. 35. The CAD device according to claim 31, wherein said element allocating means includes a master-slave flip-flop circuit to which said transmission gate not included in a feedback loop is added. Is a CAD apparatus to which a master-slave flip-flop circuit to which a transmission gate having a function of passing when the 1f clock is fixed to one logical value is added. 36. The CAD device according to claim 31, wherein the generation means of the 1f clock generation circuit supplies the 1f clock to the state storage circuit not included in a feedback loop. A CAD apparatus in which a 1f clock generation circuit with a test mode having a function of fixing an output to a logical value that allows the state storage circuit to pass is disposed in the 1f clock generation circuit. 37. The CAD device according to claim 24, wherein the clock source generating unit is configured to output the clock signal when the external clock supplied from the outside has the same frequency as the clock used in the state storage circuit. Dividing the external clock by １ ／
A CAD device in which a divide-by-2 circuit is arranged. 38. The CAD device according to claim 24, wherein the clock source generating means is configured to output the external clock supplied from the outside with a differential signal having a half frequency of a clock used in the state storage circuit. A CAD device that outputs the differential 1 / 2f clock supplied from the outside as the 1 / 2f clock at the same frequency when the clock is a / 2f clock. 39. The CAD apparatus according to claim 23, wherein the elements constituting the state storage circuit are divided into a plurality of groups including elements arranged in the vicinity. An element arranging means for arranging, wherein the generating means of the 1f clock generating circuit arranges the 1f clock generating circuit in the vicinity of each group of the state storage circuits; A CAD apparatus for setting wiring so that the delay amount of the 1 / 2f clock transmitted from the 1 / 2f clock source to the 1f clock generation circuit is equal.