JP2004127012A - Synchronous circuit and its design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous circuit capable of designing a circuit by using design environment of the synchronous circuit and reducing power consumption like an asynchronous circuit, and to provide its design method. <P>SOLUTION: In synthesizing a clock tree including clock control cells, arrangement of the clock control cells in the clock tree is determined according to the number of first storage elements driven by the clock control cells and a timing restriction value of the clock control cells is changed and timing verification before arrangement and wiring is performed in consideration of phase shift between first clock signals to be inputted in the first storage elements and second clock signals to be inputted in the clock control cells to be changed according to the arrangement of the clock control cells. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronous circuit including a plurality of storage elements operating in synchronization with a plurality of clock signals generated by a clock tree, and a method for designing the same.
[0002]
[Prior art]
In designing LSIs (Large Scale Integrated Circuits) which are becoming larger in scale, synchronous circuits are mainly used. Synchronous circuits have a well-designed design environment (currently the mainstream design method), easy timing verification (static timing verification), and scan testing as a test-friendly design. On the other hand, there are advantages such as the above, but there are disadvantages such as higher power consumption as compared with the asynchronous circuit and lower reliability against PVT fluctuation as compared with the asynchronous circuit.
[0003]
Here, the PVT fluctuation means fluctuations in the semiconductor manufacturing process (P), the power supply voltage (V), and the temperature (T).
[0004]
By the way, with the increase in the absolute value of the wiring delay and the increase in the relative value of the wiring delay with respect to the gate delay accompanying the miniaturization of the semiconductor manufacturing process, the clock signal is speeded up using a synchronous circuit in a large-scale semiconductor chip. Things are getting harder and harder. One answer to this problem is asynchronous circuits. However, there are many applications where the clock frequency is relatively low, and a synchronous circuit is often preferred for them.
[0005]
Asynchronous circuits have advantages and disadvantages that conflict with synchronous circuits. That is, an asynchronous circuit has advantages such as lower power consumption than a synchronous circuit and higher reliability against PVT fluctuations than a synchronous circuit, but has a poor design environment and difficult timing verification. (Static timing analysis cannot be used.) There are drawbacks such as that all must be performed by event-driven simulation and that scan tests cannot be used as testability design.
[0006]
In a synchronous circuit, the ratio of the charge / discharge current of the clock line to the power consumption is very high, and depending on the circuit, it may occupy more than half of the power consumption. In particular, at present, low power consumption is very demanding in mobile applications such as mobile phones.
[0007]
On the other hand, as described above, low power consumption can be realized by designing a circuit using an asynchronous circuit. However, there is a problem that the design environment of the asynchronous circuit is not prepared and a design for facilitating test such as a scan test cannot be used.
[0008]
[Problems to be solved by the invention]
Therefore, an object of the present invention is to solve the problems based on the conventional technique, to perform circuit design using a synchronous circuit design environment, and to realize low power consumption like an asynchronous circuit. To provide a synchronous circuit and a design method thereof.
[0009]
[Means for Solving the Problems]
To achieve the above object, the present invention is a synchronous circuit including a plurality of first storage elements that operate in synchronization with a plurality of first clock signals generated by a clock tree,
The clock tree includes a gate element that outputs the second clock signal at a predetermined timing specified by an enable signal that specifies a timing of outputting a second clock signal whose phase is earlier than the first clock signal. A synchronous circuit including a clock control cell is provided.
[0010]
Here, it is preferable that the clock control cell includes a second storage element holding the enable signal, and the gate element is controlled by the enable signal held in the second storage element.
[0011]
Further, it is preferable that the second storage element holds the enable signal by the second clock signal.
[0012]
The present invention is a method for designing a synchronous circuit according to any of the above,
In synthesizing a clock tree including the clock control cell,
The first storage, wherein an arrangement of the clock control cells in the clock tree is determined according to the number of the first storage elements driven by the clock control cells, and the first storage changes in accordance with the arrangement of the clock control cells. Changing a timing constraint value of the clock control cell in consideration of a phase shift between the first clock signal input to the element and the second clock signal input to the clock control cell; Provided is a method for designing a synchronous circuit, which performs a previous timing verification.
[0013]
Here, it is preferable that the timing constraint value of the clock control cell is changed in consideration of the delay time of the clock control cell due to the second storage element, and the timing verification before the placement and routing is performed.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a synchronous circuit and a design method thereof according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0015]
FIG. 1 is a conceptual diagram of a configuration of an embodiment of a synchronous circuit of the present invention.
The synchronous circuit 10 shown in FIG. 1 includes a clock tree 12 that generates a plurality of clock signals (first clock signals) CLKO from a clock signal CLK of a base (root), and a plurality of clocks generated by the clock tree 12. A plurality of flip-flops (first storage elements) 14 operating in synchronization with the signal CLKO and a combinational logic circuit 16 are provided.
[0016]
The clock tree 12 includes a root buffer (CTS) 18 and a plurality of clock control cells 20. The original clock signal CLK is input to the input terminal of the root buffer 18, and the output signal CLKI of the root buffer 18 is input to one input terminal (the lower input terminal in the figure) of each clock control cell 20. . Further, the output signal CLKO of each clock control cell 20 is input to the clock input terminal of the corresponding flip-flop 14.
[0017]
The clock tree 12 is automatically generated using a clock tree synthesis tool. Although not shown, a tree structure is formed between the root buffer 18 and each clock control cell 20 and between each clock control cell 20 and each corresponding flip-flop 14 as necessary. One or more buffers or inverters are appropriately inserted. Thereby, the output signal CLKO of the clock control cell 20 is distributed to a plurality of clock signals.
[0018]
The arrangement of the clock control cell 20 in the clock tree 12 is automatically determined by the clock tree synthesis tool according to the fan-out number, that is, the number of flip-flops 14 that the clock control cell 20 finally drives. . That is, the clock control cell 20 is arranged relatively upstream in the clock tree when the number of fanouts is large, and is arranged relatively downstream when the number of fanouts is small.
[0019]
The flip-flop 14 operates in synchronization with the clock signal CLKO generated by the clock tree 12. In the case of the flip-flop 14 of the present embodiment, the signal input to the data input terminal D is held and output from the data output terminal Q in synchronization with the rise of the clock signal CLKO. The output signal from the combination circuit 16 is input to the data input terminal D of the flip-flop 14, and the output signal from the data output terminal Q is input to the combination logic circuit 16.
[0020]
In the illustrated example, the output signal CLKO from each clock control cell 20 is input to the clock input terminal of the corresponding flip-flop 14. Although not shown, each flip-flop 14 conceptually represents a plurality of flip-flops as one flip-flop 14, and a clock input terminal of each flip-flop is connected to a clock control terminal. A plurality of clock signals generated by distributing the output signal CLKO of the cell 20 are input.
[0021]
The combinational logic circuit 16 conceptually represents circuits other than the clock tree 12 and the flip-flop 14. An external signal is also input to the combinational logic circuit 16. A part of the output signal from the combinational logic circuit 16 is supplied not only to the data input terminal D of the flip-flop 14 but also to the other input terminal (upper input terminal in the drawing) of the clock control cell 20 constituting the clock tree 12. , And the remaining output signal is output to the outside.
[0022]
The synchronous circuit 10 shown in FIG. 1 can be designed using a conventionally known synchronous circuit design environment. Further, it is also possible to adopt a test facilitation method such as a scan test.
[0023]
Next, before describing the operation of the synchronous circuit 10, the clock control cell 20 will be described with reference to the configuration circuit diagram of FIG. 2 and the timing chart of FIG.
[0024]
The clock control cell 20 shown in FIG. 2 includes a latch (second storage element) 22 and an AND gate (gate element) 24. The enable signal CLKE is input to the data input terminal D of the latch 22, and the clock signal (second clock signal) CLKI is input to its inverted clock input terminal G. The output signal from the data output terminal Q of the latch 22 and the clock signal CLKI are input to the AND gate 24, and the AND gate 24 outputs the clock signal CLKO.
[0025]
As shown in the timing chart of FIG. 3, the clock signal CLKI is input directly from the root buffer 18 of the clock tree 12 shown in FIG. 1, or through a tree-shaped buffer or inverter as required. This is a clock signal of a predetermined frequency. The clock signal CLKI has a predetermined time advance in phase with respect to the clock signal input to the flip-flop 14 in accordance with the arrangement of the clock control cells 20 in the clock tree 12.
[0026]
The enable signal CLKE is a control signal that specifies the timing at which the clock signal CLKI is output as the clock signal CLKO from the clock control cell 20, and is input from the combinational logic circuit 16 shown in FIG. Since the enable signal CLKE changes in synchronization with the clock signal input to the flip-flop 14, the enable signal CLKE changes at a timing delayed by a predetermined time from the rising edge of the clock signal CLKI.
[0027]
In the clock control cell 20, the latch 22 is in the transparent mode while the clock signal CLKI is at the low level (L), and the enable signal CLKE input to the data input terminal D is output from the data output terminal Q. In addition, the holding mode is set while the clock signal CLKI is at the high level (H), and the state of the enable signal CLKE input to the data input terminal D is held at the rising timing of the clock signal CLKI.
[0028]
As shown in the timing chart of FIG. 4, in order to correctly operate the latch 22, there is a physical timing constraint on the data holding period of the enable signal CLKE with respect to the rising edge of the clock signal CLKI. That is, in order to operate the latch 22 correctly, enable signal CLKE is required predetermined set-up time _{t s} and the hold time _{t h} with respect to rising edge of the clock signal CLKI.
[0029]
In the clock control cell 20, as shown in the timing chart of FIG. 3, when a high level is input as the enable signal CLKE, the latch 22 is in the transparent mode during the low level of the clock signal CLKI, as described above. A high level is output from the data output terminal Q. Then, AND operation with the clock signal CLKI is performed by the AND gate 24, and a high level is output as the clock signal CLKO during the next high level period of the clock signal CLKI.
[0030]
Next, the operation of the synchronous circuit 10 shown in FIG. 1 will be described.
[0031]
In the synchronous circuit 10, the original clock signal CLK is distributed by the clock tree 12, and a plurality of clock signals CLKO are generated. The clock control cell 20 receives the enable signal CLKE from the combinational logic circuit 16. The clock signal CLKO supplied from the clock control cell 20 to the corresponding flip-flop 14 requires the flip-flop 14 to operate. Since it changes only at times, power consumption due to charging and discharging of the clock line can be significantly reduced.
[0032]
Each flip-flop 14 operates in synchronization with clock signal CLKO input from clock tree 12 as described above, and its output signal is input to combinational logic circuit 16. The combinational logic circuit 16 operates based on an external input and an output signal from each flip-flop 14. A part of the output signal is input to the clock control cell 20 as the enable signal CLKE, the other part is input to the data input terminal D of the flip-flop 14, and the rest is output to the outside.
[0033]
Next, a method of designing a synchronous circuit according to the present invention will be described.
[0034]
As described above, the clock tree 12 is synthesized by the clock tree synthesis tool. At this time, the clock control cell 20 is given a transparency attribute by setting the output signal of the latch 22 to a high level, for example, and is treated as one of the buffers constituting the clock tree 12. Thus, the clock tree 12 can be synthesized using a conventionally known clock tree synthesis tool.
[0035]
When the clock tree 12 is synthesized by the clock tree synthesis tool, the arrangement of the clock control cells 20 in the clock tree 12 is automatically determined according to the number of fan-outs. In accordance with the arrangement of clock control cell 20, clock signal CLKI input to clock control cell 20 has a phase leading clock signal CLKO input to flip-flop 14 by a predetermined time in accordance with the number of fan-outs. In.
[0036]
For example, when the number of fan-outs of the clock control cells 20 is small, the clock control cells 20 are arranged relatively downstream in the clock tree 12, and when the number is large, they are arranged relatively upstream. Therefore, as the number of fan-outs of the clock control cell 20 increases, the clock control cell 20 is gradually arranged on the upstream side in the clock tree 12, so that the clock signal CLKI input to the clock control cell 20 advances. growing.
[0037]
Normally, in synchronous circuit design, timing verification before placement and routing, for example, timing verification at the time of simulation or logic synthesis, assumes that all nodes on a clock line have the same phase, such as flip-flops and latches. The verification of the timing constraint of each storage element is performed.
[0038]
However, when the clock tree 12 is synthesized using the clock control cell 20, the phase of the clock signal CLKI input to the clock control cell 20 is predetermined with respect to the clock signal CLKO input to the flip-flop 14 from the clock tree 12. Therefore, if the timing verification is performed on the assumption that all the clock signals have the same phase, there is a high possibility that a problem will occur in the timing verification after the actual placement and wiring.
[0039]
The reason is that the arrangement of the clock control cells 20 in the clock tree 12 moves upstream and downstream in accordance with the fan-out number of the clock control cells 20, and the phase of the clock signal CLKI input to the clock control cells 20 advances. This is because the phase shift width between the clock signal CLKO input to the flip-flop 14 from the clock tree 12 and the clock signal CLKI input to the clock control cell 20 changes.
[0040]
On the other hand, in the synchronous circuit design method of the present invention, the number of fan-outs of each clock control cell 20 is detected by performing a netlist analysis, and the number changes depending on the number of fan-outs, that is, the arrangement of the clock control cells 20. Considering the phase shift between the clock signal input to the flip-flop 14 and the clock signal CLKI input to the clock control cell 20, the timing constraint value of the clock control cell 20 is dynamically changed, Perform previous timing verification.
[0041]
In other words, assuming that the clock signal CLKI input to the clock control cell 20 has the same phase as the clock signal input to the flip-flop 14, even if the timing verification before the placement and routing is performed, An offset is given to the timing constraint value of the clock control cell 20 so that the timing verification before the placement and routing is performed so that the probability that a failure occurs in the verification is reduced.
[0042]
For example, when the setup time and the hold time are 2 ns and 1 ns, respectively, as the physical timing constraint values of the clock control cell 20, the clock input to the clock control cell 20 depends on the number of fan-outs of the clock control cell 20. Assuming that the advance time of the signal CLKI is 1 ns, the setup time and the hold time of the clock control cell 20 are changed to 3 ns and 0 ns, respectively, in the timing verification before placement and routing.
[0043]
As described above, by dynamically changing the timing constraint value according to the number of fan-outs of the clock control cell 20 and performing timing verification before placement and routing, it is possible to reduce the probability of occurrence of a timing error after placement and routing. Can be.
[0044]
In the clock control cell 20, the output delay by the latch 22 is generated, in consideration of this delay time, is better to unnecessary pulses to adjust the set-up time t _s of the latch 22 so as not to generate from the AND gate 24 preferable. In the synchronous circuit design method of the present invention, only one clock control cell 20 is provided on the same clock line because the timing constraint value is dynamically changed according to the number of fan-outs of each clock control cell 20. It is preferable to do so.
[0045]
Next, an example in which the present invention is applied to a conventionally known synchronous circuit will be described.
[0046]
FIG. 5A is a configuration circuit diagram of an example of a conventional synchronous circuit.
The synchronous circuit 26 includes a multiplexer 28 and a flip-flop 30. The output signal OUT from the data output terminal Q of the flip-flop 30 is input to the input terminal 0 of the multiplexer 28, and the input signal IN is input to the input terminal 1. The clock signal CLK is input to the clock input terminal of the flip-flop 30, and the output signal from the multiplexer 28 is input to the data input terminal D.
[0047]
In the synchronous circuit 26, when the enable signal ENBL is at a high level, the input signal IN is held in the flip-flop 30 via the multiplexer 28 and output as the output signal OUT in synchronization with the rise of the clock signal CLK. You. On the other hand, when the enable signal ENBL is at the low level, the output signal OUT of the flip-flop 30 is held again by the flip-flop 30 via the multiplexer 28, so that the output signal OUT of the flip-flop 30 does not change.
[0048]
The synchronous circuit 26 prevents the output signal OUT of the flip-flop 30 from being unnecessarily changed according to the state of the enable signal ENBL. A useless clock is input, and useless power consumption occurs due to charging and discharging of the clock line.
[0049]
FIG. 5B shows a synchronous circuit of the present invention configured by applying the present invention to the conventional synchronous circuit shown in FIG. The synchronous circuit 32 shown in FIG. 5B is different from the synchronous circuit 26 shown in FIG. 5A in that the output signal of the clock control cell 20 is input to the clock input terminal of the flip-flop 30 instead of the clock signal CLK. It was done. Further, the clock signal CLK and the enable signal ENBL are input to the clock control cell 20.
[0050]
In the synchronous circuit 32, the output signal of the clock control cell 20 changes only when the flip-flop 30 needs to operate according to the state of the enable signal ENBL. Power consumption due to discharging can be reduced. In particular, the greater the number of flip-flops 30 to which the output signal CLKO of the clock control cell 20 is input, and the smaller the rate at which the flip-flop 30 operates, the more the charge and discharge of the output signal CLKO of the clock control cell 20 The effect of reducing power consumption increases.
[0051]
FIG. 5 (c) shows a further optimization of the synchronous circuit of the present invention shown in FIG. 5 (b). In the synchronous circuit 34 shown in FIG. 5C, the multiplexer 28 is removed from the synchronous circuit 32 shown in FIG. 5B, and the input signal IN is directly input to the data input terminal D of the flip-flop 30. . In the synchronous circuit 32 shown in FIG. 5B, the multiplexer 28 is unnecessary because the output signal of the clock control cell 20 changes only when the flip-flop 30 needs to operate.
[0052]
As described above, in the synchronous circuit to which the present invention is applied, not only the charge / discharge current of the clock line can be reduced and the power consumption of the synchronous circuit can be reduced, but also FIGS. As can be seen from FIG. 2), the output signal of the flip-flop is prevented from being unnecessarily changed by using a circuit such as a multiplexer, but the clock signal is prevented from being changed by a circuit such as a multiplexer. The effect of reducing the number of transistors is that the number of transistors and power consumption can be reduced.
[0053]
Note that the clock control cell 20 is not limited to the configuration in FIG. 2, but may use another configuration that realizes a predetermined function. For example, a flip-flop instead of the latch 22 may be used. In the case of a flip-flop synchronized with the rising edge of the clock, the change timing of the output signal from the data output terminal is shifted one clock backward. In the case of the flip-flop synchronized with the clock falling, the change timing of the output signal is not delayed, but the delay time constraint imposed on the data input signal becomes strict about half a clock cycle. When the flip-flop 14 is synchronized with the falling edge of the clock or when the polarity of the enable signal ENBL is different, the polarities of the input and output signals of the latch 22 and the AND gate 24 in the clock control cell 20 are appropriately adjusted accordingly. It needs to be changed.
[0054]
The present invention is basically as described above.
As described above, the synchronous circuit and the design method thereof according to the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.
[0055]
【The invention's effect】
As described above in detail, according to the synchronous circuit of the present invention, the clock signal supplied from the clock control cell to each corresponding first storage element changes only when the first storage element needs to operate. Therefore, power consumption due to charging and discharging of the clock line can be significantly reduced. In addition, the synchronous circuit of the present invention can be designed in a short time by using a synchronous circuit design environment, and can also facilitate a test by using a test method such as a scan test. is there.
Further, according to the synchronous circuit design method of the present invention, the timing constraint value is dynamically changed in accordance with the number of fan-outs of the clock control cell to perform timing verification before placement and routing. The probability that a timing error will occur at the time of timing verification can be reduced.
Further, according to the present invention, the skew between clock signal groups generated via the same clock control cell in the clock tree is reduced, so that there is also an effect that a timing error after placement and routing hardly occurs. For example, when a clock control cell is added to the shift register circuit, it is expected that the probability of occurrence of a hold time constraint error is reduced.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram illustrating a configuration of a synchronous circuit according to an embodiment of the present invention.
FIG. 2 is a configuration circuit diagram of an embodiment of a clock control cell.
FIG. 3 is a timing chart of an embodiment showing an operation of a clock control cell.
FIG. 4 is a timing chart of an embodiment showing timing constraints of a clock control cell.
FIGS. 5 (a), (b) and (c) are embodiments showing a conventional synchronous circuit, a synchronous circuit to which the present invention is applied, and an optimized state of the synchronous circuit of the present invention, respectively. FIG.
[Explanation of symbols]
10, 26, 32, 34 Synchronous circuit 12 Clock tree 14, 30 Flip-flop 16 Combinational logic circuit 18 Root buffer 20 Clock control cell 22 Latch 24 AND gate 28 Multiplexer

Claims (5)

A synchronous circuit including a plurality of first storage elements operating in synchronization with a plurality of first clock signals generated by a clock tree,
The clock tree includes a gate element that outputs the second clock signal at a predetermined timing specified by an enable signal that specifies a timing of outputting a second clock signal whose phase is earlier than the first clock signal. A synchronous circuit comprising a clock control cell. The synchronization according to claim 1, wherein the clock control cell includes a second storage element holding the enable signal, and the gate element is controlled by the enable signal held in the second storage element. Expression circuit. The synchronous circuit according to claim 2, wherein the second storage element holds the enable signal in accordance with the second clock signal. A method for designing a synchronous circuit according to claim 1,
In synthesizing a clock tree including the clock control cell,
The first storage, wherein an arrangement of the clock control cells in the clock tree is determined according to the number of the first storage elements driven by the clock control cells, and the first storage changes in accordance with the arrangement of the clock control cells. Changing a timing constraint value of the clock control cell in consideration of a phase shift between the first clock signal input to the element and the second clock signal input to the clock control cell; A method for designing a synchronous circuit, comprising performing timing verification before. The synchronous circuit according to claim 4, further comprising: changing a timing constraint value of the clock control cell in consideration of a delay time of the clock control cell by a second storage element, and performing timing verification before the placement and routing. Design method.

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