JPH11166959A - Scan path circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan path circuit that is in a small-scale and short, total wiring length device configuration and is capable of highly reliable operation. SOLUTION: A circuit is provided with a plurality of flip-flops 13, 15, 17, and 19 being connected in series that latch the data of an SI terminal according to a clock signal and outputs the latched data from an output terminal according to a scan mode signal in a scan mode. Then, the circuit supplies scan mode signals SCK1 , SCK2 , SCK3 , and SCK4 that are delayed by each different delay time as compared with a reference scan mode signal SCK being inputted to an SCK terminal 66 according to the difference in a wiring distance from the SCK terminal 66 to the SCK terminal of the flip-flops 13, 15, 17, and 19 in the scan mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan path circuit including a skew countermeasure flip-flop having a scan function.

[0002]

2. Description of the Related Art A shift register using a large number of master / slave type flip-flops is usually used in a digital logic circuit. In particular, in a large-scale digital logic circuit, a flip-flop is operated as a shift register at the time of testing in order to facilitate manufacturing test.
So-called scan path technology is widely used. By the way, in recent years, the ratio of the wiring delay to the signal delay has increased due to the improvement of the integrated circuit technology. As a result, a delay difference, that is, a clock skew, is likely to occur in a clock signal to be supplied equally to each flip-flop. ing.
In particular, the shift register structure is vulnerable to clock skew,
There is a possibility of malfunction. Further, a gated clock signal is frequently used for the purpose of reducing power consumption, which also causes an increase in clock skew. Therefore, it is difficult to design a digital logic circuit using the scan path technology.

Here, a function clock (g
ated clock) Scan path circuit 1 using generating circuit 14
Think one. The scan path circuit 11 shown in FIG. 9 is configured by connecting four flip-flops 13, 15, 17, and 19 in series. In the scan path circuit 11, the scan mode signal SCK holds a high level in the general mode, and has a pulse waveform shown in FIG. 10C in the scan mode. The function clock generation circuit 14 includes a NAND circuit 21
And an AND circuit 23.

In the function clock generation circuit 14, for example,
The signal Q from the Q terminal of the flip-flop 13 is shown in FIG.
The scan mode signal SCK is used as the clock enable signal XEN shown in FIG.
When N is at a low level, the output signal of the NAND circuit 21 goes to a high level, and the output signal of the AND circuit 23 is
The clock signal CK ′ shown at 0 (B) is output to the CK terminals of the flip-flops 17 and 19. As a result, the flip-flops 17 and 19 are driven. On the other hand, in the general mode, when the clock enable signal XEN is at the high level, the output signal of the NAND circuit 21 goes to the low level, the clock signal CK 'is not supplied to the flip-flops 17 and 19, and the flip-flops 17 and 19 Is stopped. Thereby, power consumption is suppressed.

On the other hand, in the scan path circuit 11, in order to perform the shift register operation in the scan mode, the scan mode signal SCK is set to the low level, and the function clock generation circuit 14 is forcibly set to the through state. The scan path circuit 11 shown in FIG.
When general flip-flops having no skew prevention function are used as 5, 17, and 19, the scan operation can be performed correctly.

The scan path circuit 51 shown in FIG.
Is supplied with the clock signal CKA to the CK terminals of the flip-flops 13 and 15. Also, flip-flop 1
The clock signal CK is input to the CK terminals 7 and 19 in the general mode.
Independently of A, clock signal CKA in scan mode
And a clock signal CKB synchronized with the clock signal CKB. In the scan path circuit 51, in the general mode, the clock signal CKA
And CKB, there is a time difference, so that the power consumption of the entire circuit is temporally dispersed, and the power consumption at the peak can be reduced.

[0007]

By the way, if the power consumption can be reduced by using the function clock generation circuit 14 like the scan path circuit 11 shown in FIG. 9, the width of the power supply wiring can be reduced and the number of power supply wirings can be reduced. Thus, the degree of integration of the chip can be improved. However, in the scan path circuit 11 shown in FIG. 9, in the scan mode, all the flip-flops 13, 15, 17, and 19 constituting the scan path are operated at the same time. It will be almost the same as without. Therefore, if the width and the number of the power supply wiring are determined according to the power consumption in the general mode, the power supply wiring cannot supply the power required for the scan operation, causing the scan operation to malfunction or disconnection of the power supply wiring due to electromigration. May occur. Here, electromigration is a phenomenon in which aluminum atoms cause mass transport due to momentum conversion with electrons. Therefore, in the scan path circuit 51, it is necessary to increase the width of the power supply wiring or increase the number of power supply wirings in accordance with the scan mode, and there is a problem that the chip area increases.

The scan path circuit 51 shown in FIG.
Now, in the scan mode, the clock signals CKA and CKB
As in the case of the scan path circuit 11, the power consumption is concentrated, the scan operation may malfunction, or the power supply wiring may be disconnected due to electromigration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and can reduce the peak of the power consumption of the entire circuit. It is an object of the present invention to provide a scan path circuit capable of performing the above operation.

[0010]

As described above, since most of the power consumption during the scanning operation is generated when the output of the flip-flop changes, a flip-flop having a skew countermeasure function is used. If the output change timing can be distributed among the flip-flops, the peak power consumption can be reduced. From such a viewpoint, in order to solve the above-described problems of the related art and achieve the above-described object, the scan path circuit of the present invention converts the data of the input terminal according to the clock signal in the scan mode. A plurality of serially-connected flip-flops for latching and outputting the latched data from an output terminal in response to a scan mode signal; and Scan mode signal supply means for supplying a mode signal.

Here, the scan mode signal supply means specifically receives a reference scan mode signal, and, based on the reference scan mode signal, supplies a plurality of scan mode signals having different timings to be supplied to the plurality of flip-flops. Generate At this time, the scan mode signal supply means may provide a wiring so as to be different between the plurality of flip-flops, or connect an input terminal of the reference scan mode signal and an input terminal of the scan mode signal of the plurality of flip-flops. A delay circuit having a different signal transmission delay time is provided in each wiring path, or a wiring path between an input terminal of the reference scan mode signal and an input terminal of a scan mode signal of the plurality of flip-flops is provided. By providing a different number of delay circuits having the same delay time, signal transmission delay times until the reference scan mode signal is transmitted to the scan mode signal input terminals of the plurality of flip-flops are different from each other. The output change timing among multiple flip-flops. There.

In the scan path circuit of the present invention, since the scan mode signals having different timings are supplied to the plurality of flip-flops, the output changes of the flip-flops requiring high power consumption are shifted from each other. The peak power consumption of the entire device is reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A scan path circuit according to an embodiment of the present invention will be described below. The scan path circuit of the present embodiment uses a skew countermeasure flip-flop having a scan function. FIG. 1 is a configuration diagram of a skew suppression flip-flop 1 having a scan function. As shown in FIG. 1, the flip-flop 1 includes a multiplexer 3, a master latch 5, an AND circuit 6, a slave latch 7, and a NOT circuit 9. FIG. 2 is a timing chart of each signal of the flip-flop 1 shown in FIG. The multiplexer 3 receives the system input signal D and the serial input signal SI shown in FIG. 2A. In the scan mode, when the scan mode signal SCK shown in FIG. SI is output to the IN terminal of the master latch 5.
On the other hand, in the multiplexer 3, in the general mode, the scan mode signal SCK is held at a high level, and the system input signal D is output to the IN terminal of the master latch 5.

In the scan mode, the master latch 5 passes the serial input signal SI input from the IN terminal to the OUT terminal while the clock signal CK input from the CK terminal shown in FIG. At the rising timing of the signal CK, the serial input signal S
Latch I. In the slave latch 7, at the timing when the signal XG shown in FIG. 2D from the AND circuit 6 corresponding to the scan mode signal SCK rises, the serial input signal SI latched by the master latch 5 is applied from the IN terminal to the Q terminal.
The signal passes through the terminal and is output as a signal Q shown in FIG. Thereafter, at the timing when the signal XG falls, the serial input signal SI is latched. As described above, in the flip-flop 1, the operation of latching the serial input signal SI is performed at the timing of the rising of the clock signal CK, and the operation of outputting the signal Q is performed at the timing of the rising of the scan mode signal SCK. The time difference becomes a skew margin, and malfunction due to clock skew is avoided. When the clock signal CK input to the CK terminal is at a low level, the master latch 5
The slave latch 7 is a low-active latch circuit that passes a signal at the N terminal to the OUT terminal. The slave latch 7 passes a signal at the IN terminal to the Q terminal when the signal XG input to the CK terminal is at a high level. Is a latch circuit.

As shown in FIG. 2, for example, the change of the signal Q which is the output of the anti-skew flip-flop 1 having the scan function shown in FIG. That is,
It occurs at the timing of switching from the scan mode to the general mode. In the scan path circuit of the present embodiment, the peak power consumption during the scan operation is reduced by temporally dispersing the scan mode signals reaching the plurality of flip-flops constituting the scan path circuit.

FIG. 3 is a circuit diagram of a scan path circuit 61 according to the first embodiment . As shown in FIG. 3, the scan path circuit 61 has, for example, a configuration in which flip-flops 13, 15, 17, and 19 are connected in series. That is, the Q terminal of the flip-flop 13 is connected to the SI terminal of the flip-flop 15, the Q terminal of the flip-flop 15 is connected to the SI terminal of the flip-flop 17,
Q terminal is connected to the SI terminal of the flip-flop 19. D of flip-flops 13, 15, 17, and 19
The terminal is connected to the combination circuit 70 on the system side,
The system input signal D is input. Here, the combination circuit 70 on the system side is an arbitrary digital signal processing circuit that realizes a predetermined function. Flip-flop 13, 1
For example, the flip-flop 1 shown in FIG.

The SCK terminal of the flip-flop 13 is connected to the SCK input terminal 66 via the wiring 62. The SCK terminal of the flip-flop 15 is connected to the SCK input terminal 66 via a part of the wiring 62 and the wiring 63. The SCK terminal of the flip-flop 17
It is connected to the SCK input terminal 66 via a part of the wiring 62, a part of the wiring 63, and a wiring 64. The SCK terminal of the flip-flop 19 is connected to a part of the wiring 62,
, A part of the wiring 64 and the wiring 65,
It is connected to the K input terminal 66. Here, the wiring 62,
63, 64 and 65 are made of the same material and the same wiring width. As a material for the wiring, for example, aluminum or the like is used. In the present embodiment, the wirings 62, 63, 6
The scan mode signal supply means is constituted by 4, 65. The SCK input terminal 66 and the flip-flop 1
The distances along the wiring with the SCK terminals of 3, 15, 17, and 19 are, for example, 5000 μm, 7000 μm,
9000 μm and 11000 μm.

The SI terminal of the flip-flop 13 is shown in FIG.
The serial input signal SI shown in (A) is input, and the serial signal output SO from the Q terminal of the flip-flop 19 is output. Also, the CK of the flip-flops 13 and 15
For example, a clock signal CK shown in FIG.
Is entered. In addition, C of the flip-flops 17 and 19
For example, a clock signal CK ′ is input to the K terminal from the function clock generation circuit 14 including the NAND circuit 21 and the AND circuit 23 illustrated in FIG.

The operation of the scan path circuit 61 in the scan mode will be described below. FIG. 4 is a timing chart for explaining the operation of the scan path circuit 61 in the scan mode. The serial input signal SI is input to the SI terminal of the flip-flop 13. Further, the reference scan mode signal SC shown in FIG.
FIG. 4 in which K is input and the reference scan mode signal SCK is delayed by a time t in accordance with the distance of the wiring 62.
Scan mode signal SCK ₁ shown in (D) is input to the SCK terminal of the flip-flop 13. In the flip-flop 13 at the timing when the scan mode signal SCK ₁ rises, as shown in FIG. 4 (E), rises the signal XG ₁ corresponding to the signal XG shown in FIG. Then, the flip-flop 13 at the rising timing of the signal XG _1, the serial input signal SI is master latch 5 shown in FIG. 1 and latch is through to the Q terminal, the signal S
13 is output to the SI terminal of the flip-flop 15. That is, the timing t1 when the signal XG ₁ rises
Thus, the power consumption of the flip-flop 13 reaches a peak.

The SCK along the wirings 62 and 63
The SCK ₂ signal shown in FIG. 4F delayed from the SCK signal by a time 2t in accordance with the distance between the input terminal 66 and the SCK terminal of the flip-flop 15
5 is input to the SCK terminal. In the flip-flop 15, at the timing when the scan mode signal SCK ₂ rises, as shown in FIG. 4 (G), rises the signal XG ₂ corresponding to the signal XG shown in FIG. Then, the flip-flop 15 at the rising timing of the signal XG _2, signal S is the master latch 5 shown in FIG. 1 latches
13 is passed through the Q terminal and output to the SI terminal of the flip-flop 17 as a signal S15. That is, at the timing t2 when the signal XG ₂ rises, the power consumption of the flip-flop 15 becomes a peak.

Further, S along the wirings 62, 63, 64
The SCK ₃ signal shown in FIG. 4H delayed from the SCK signal by the time 3t with respect to the distance between the CK input terminal 66 and the SCK terminal of the flip-flop 17 is input to the SCK terminal of the flip-flop 17. Flip-flop 1
In 7, at the timing when the scan mode signal SCK ₃ rises, as shown in FIG. 4 (I), signal shown in FIG. 1 X
Signal XG ₃ corresponding to G rises. Then, the flip-flop 17 at the rising timing of the signal XG _3, signal S15 master latch 5 is latched as shown in FIG. 1 is through the Q terminal, and output as a signal S17 to the SI terminal of the flip-flop 19. That is,
At the timing t3 when the signal XG ₃ rises, the power consumption of the flip-flop 17 becomes a peak.

Further, the SCK input terminal 66 and the SC of the flip-flop 19 along the wirings 62, 63, 64, 65
Time 4t for the SCK signal according to the distance to the K terminal
The SCK ₄ signal shown in FIG. 4J delayed by only this amount is input to the SCK terminal of the flip-flop 19. In the flip-flop 19, at the timing when the scan mode signal SCK ₄ rises, as shown in FIG. 4 (K), rises the signal XG ₄ corresponding to the signal XG shown in FIG. And
In the flip-flop 19 at the rising timing of the signal XG _4, signal S17 master latch 5 is latched as shown in FIG. 1 is through the Q terminal, and output as a serial output signal SO. That is, at timing t4 at which the signal XG ₄ rises, the power consumption of the flip-flop 19 becomes a peak.

In the general mode, the SCK input terminal 6
6 is held at a high level, the output signal of the NAND circuit 21 goes high when the clock enable signal XEN of the function clock generation circuit 14 shown in FIG. The clock signal C is output from the output terminal of the AND circuit 23.
K ′ is output to the CK terminals of the flip-flops 17 and 19. As a result, the flip-flops 17 and 19 are driven. On the other hand, in the general mode, when the clock enable signal XEN is at the high level, the NAND circuit 21
Output signal goes low, flip-flop 1
The clock signal CK ′ is not supplied to 7, 7 and the flip-flops 17 and 19 are stopped. This allows
Power consumption is reduced.

As described above, according to the scan path circuit 61, the wiring distance between the SCK terminal and the SCK input terminal 66 among the flip-flops 13, 15, 17, and 19 is determined to be different from each other. Thus, in the scan mode, the flip-flops 13, 15, 17, 1
9 scan mode signal SCK input to the SCK terminal
₁ , SCK ₂ , SCK ₃ and SCK ₄ can be shifted in timing. As a result, FIGS. 4 (E), (G),
As shown in (I) and (K), the flip-flop 13,
The rising timing of the signals XG ₁ , XG ₂ , XG ₃ , XG ₄ corresponding to the signal XG shown in FIG.
The peak of power consumption is shifted among 5, 17, and 19, and the peak of power consumption in the entire scan path circuit 61 can be reduced. Further, according to the scan path circuit 61, since the peak of the power consumption can be reduced, it is not necessary to use an excessive power supply current, and the reliability of the circuit operation is improved. Also,
It is not necessary to reinforce the power supply wiring, so that the chip area can be reduced, the yield can be improved, and the production cost can be reduced.

Second Embodiment FIG. 5 is a circuit diagram of a scan path circuit 81 according to this embodiment. 5, the same components as those in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 5, the scan path circuit 81 includes, for example, flip-flops 13, 15, 17, and 1 similarly to the scan path circuit 61 illustrated in FIG.
9 are connected in series. However, buffers 82, 83, 84 as delay circuits are inserted into wirings 85, 86, 87 connecting the SCK input terminal 66 and the SCK terminals of the flip-flops 13, 15, 17, 19, respectively. In the present embodiment, the buffers 82, 83, 84
This constitutes a scan mode signal supply unit.

Here, the buffers 82, 83 and 84 delay the input reference scan mode signal SCK by a predetermined time and output the delayed reference scan mode signal SCK.
It becomes shorter in the order of 3,84. In this embodiment, for the sake of convenience, the transmission time of the reference scan mode signal SCK corresponding to the distance between the wirings 85, 86, 87, and 88 is not considered.

In the scan path circuit 81, the buffer 8
Since the delay times in 2, 83 and 84 become shorter in order, the scan mode signals SCK ₁₁ , SCK ₁₂ ,
The delay time of the SCK ₁₃ becomes smaller in order than the reference scan mode signal SCK input to the SCK terminal of the flip-flop 19. That is, according to the scan path circuit 81, the S of the flip-flops 13, 15, 17, 19
Scan mode signals SCK ₁₁ and SCK input to the CK terminal
The timings of CK ₁₂ , SCK ₁₃ and SCK can be shifted. As a result, similarly to the above-described scan path circuit 61, the peak of the power consumption is shifted among the flip-flops 13, 15, 17, and 19, and the peak of the power consumption of the entire scan path circuit 81 can be reduced.

Third Embodiment FIG. 6 is a circuit diagram of a scan path circuit 91 according to the third embodiment . 6, the same components as those in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 6, the scan path circuit 91 includes, for example, flip-flops 13, 15, 17, 1 similarly to the scan path circuit 61 shown in FIG.
9 are connected in series. However, buffers 92, 93, and 94 are inserted in a wiring 98 that connects the SCK input terminal 66 and the SCK terminal of the flip-flop 19. SCK input terminal 66 and S of flip-flop 13
The CK terminal is connected to a part of the wiring 98 and the wiring 95. The output terminal of the buffer 92 and the SCK terminal of the flip-flop 15 are connected. The output terminal of the buffer 93 and the SCK terminal of the flip-flop 17 are connected. The output terminal of the buffer 94 and the SCK terminal of the flip-flop 19 are connected. Here, the buffers 92, 93, and 94 function as delay circuits, and output the input reference scan mode signal SCK with the same time delay. In the present embodiment, for the sake of convenience, the transmission time of the reference scan mode signal SCK according to the distance between the wirings 95, 96, 97, 98 is not considered. In the present embodiment, the buffers 92, 93, and 94 constitute a scan mode signal supply unit.

In the scan path circuit 91, no buffer exists between the SCK input terminal 66 and the SCK terminal of the flip-flop 13, and a buffer 92 exists between the SCK input terminal 66 and the SCK terminal of the flip-flop 15. Exists, the SCK input terminal 66 and the flip-flop 17 SC
Buffers 92 and 93 exist between the KCK terminal and SCK.
Buffers 92, 93 and 94 exist between the input terminal 66 and the SCK terminal of the flip-flop 19. Therefore,
Assuming that the delay time in the buffers 92, 93, 94 is s,
The reference scan mode signal SCK is supplied to the SCK terminal of the flip-flop 13 and the SCK terminal of the flip-flop 15
Scan mode signal SCK ₂₂ delayed by time s for the reference scan mode signal SCK is supplied to the CK terminal. A scan mode signal SCK ₂₃ delayed by 2 s with respect to the reference scan mode signal SCK is supplied to the SCK terminal of the flip-flop 17, and a time 3 s with respect to the reference scan mode signal SCK is supplied to the SCK terminal of the flip-flop 19. The scan mode signal SCK ₂₄ delayed by only this time is supplied.

That is, according to the scan path circuit 91, the SCK of the flip-flops 13, 15, 17, 19
Can be shifted timing of the reference scan mode signal SCK and the scan mode signal SCK _22, SCK _23, SCK ₂₄ is input to the terminal. As a result, similar to the above-described scan path circuit 61, the flip-flops 13,
The peak of power consumption is shifted among 15, 17, and 19,
The peak of power consumption in the entire scan path circuit 91 can be reduced.

Fourth Embodiment FIG. 7 is a circuit diagram of a scan path circuit 101 according to this embodiment. 7, the same components as those in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 7, the scan path circuit 101 includes, for example, flip-flops 13, 15, 1
7, 19, 102, 103 and 104. As shown in FIG. 7, the scan path circuit 101 has a configuration in which, for example, flip-flops 13, 15, 17, and 19 are connected in series, similarly to the scan path circuit 61 shown in FIG. In the present embodiment, the flip-flops 102 and 10
3, 104 constitute a flip-flop for generating a scan mode signal.

In the scan path circuit 101, the Q terminal of the flip-flop 102 is connected to the flip-flop 103
, And the Q terminal of the flip-flop 103 is connected to the D terminal of the flip-flop 104.
Further, the SCK input terminal 66 is connected to the R (reset) terminals of the flip-flops 102, 103, 104 via a NOT circuit. Also, flip-flop 1
02 is connected to the flip-flop 1 via the wiring 111.
5 is connected to the SCK terminal of the flip-flop 103, and the Q terminal of the flip-flop 103
The CK terminal is connected, and the Q terminal of the flip-flop 104 is connected to the SCK terminal of the flip-flop 19 via the wiring 113.

In the scan path circuit 101, the D terminal of the flip-flop 102 is connected to the VDD which holds the high level.
A signal is applied and flip-flops 102, 103, 1
The clock signal YCK is applied to the CK terminal 04. In the present embodiment, the flip-flops 102, 103, 10
4 constitutes a scan mode signal supply means.

The scan path circuit 101 shown in FIG.
Will be described. FIG. 8 is a timing chart for explaining the operation of the scan path circuit 101 shown in FIG. In the scan path circuit 101, the reference scan mode signal SCK shown in FIG. 8A is applied to the SCK input terminal 66, delayed by the wiring 110, and turned into a flip-flop as the scan mode signal SCK ₃₁ shown in FIG. 1
3 as well as to the R terminals of flip-flops 102, 103 and 104 via a NOT circuit. Here, the scan mode signal SCK ₃₁ is
It is delayed by the time u from the reference scan mode signal SCK.

[0035] Then, the flip-flop 10 in the scan mode signal SCK ₃₁ rises example timing t1
After the reset of 2, 103 and 104 is released, FIG.
At the timing t2 when the clock signal YCK rises to (B), the flip-flop 102 latches the high level of VDD signal as the scan mode signal SCK _32. Thus, as shown in FIG. 8 (D), from the timing t2 after a lapse of the passing time of the flip-flop 102, the scan mode signal SCK ₃₂ rises. At this time, the flip-flops 103 and 104 also
Scan mode signals SCK ₃₂ , SCK input to the terminals
₃₃ is latched and output from the Q terminal.
Since the scan mode signals SCK ₃₂ and SCK ₃₃ maintain the low level,
The levels of K ₃₃ and SCK ₃₄ do not change.

Next, the clock signal YC shown in FIG.
At timing t3 when K rises, flip-flop 1
03 latches the high level of the scan mode signal SCK ₃₂ as a scan mode signal SCK _33. As a result, as shown in FIG.
K ₃₃ is switched to a high level. At this time, the flip-flop 104 latches the scan mode signal SCK ₃₃ input to the D terminal and outputs the scan mode signal SCK ₃₃ from the Q terminal. At the timing t3, since the scan mode signal SCK ₃₃ is at the low level, the scan mode signal SCK ₃₃ Level ₃₄ remains unchanged.

Next, the clock signal YC shown in FIG.
At timing t4 when K rises, flip-flop 1
04 latches the high level of the scan mode signal SCK ₃₃ as a scan mode signal SCK _34. As a result, as shown in FIG.
K ₃₄ is switched to a high level.

As described above, the scan path circuit 1
01, flip-flops 13, 15, 17, 1
9 scan mode signal SCK input to the SCK terminal
₃₁ , SCK ₃₂ , SCK ₃₃ and SCK ₃₄ can be shifted in timing. As a result, similarly to the above-described scan path circuit 61, the flip-flops 13, 15, 17, 1
The peak of the power consumption is shifted among the scan path circuits 9 and the peak of the power consumption of the entire scan path circuit 101 can be reduced.

The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, four flip-flops such as flip-flops 13, 15, 17, and 19 are connected in series, but the number of connected flip-flops is arbitrary.

In the scan path circuit 61 shown in FIG. 3, the SCK input terminal 66 and the flip-flop 1
By using different wiring lengths among the scan mode signals SCK ₁ , SCK ₂ , SCK
₃ , the timing of SCK ₄ is shifted. However, according to the present invention, even if the same wiring length is used, for example, the wiring may have different delay characteristics by changing the material and thickness of the wiring. . Further, the number of times the contact passes between the wiring layers may be changed.

In the above-described scan path circuit of the present embodiment, the flip-flops 13, 15, and 1 are converted from the reference scan mode signal input from the SCK input terminal 66.
The scan mode signals to be supplied to the SCK terminals 7 and 19 are generated. If the timings are shifted from each other, the scan mode signals to be supplied to the SCK terminals of the flip-flops 13, 15, 17, and 19 are generated independently. You may do so.

Further, in the scan path circuit of the above-described embodiment, a case where the scan mode signal having a longer delay time than the reference scan mode signal SCK is supplied in the order of the flip-flops 13, 15, 17, and 19 has been exemplified. However, according to the present invention, if the delay times are different from each other, the order of the delay times of the scan mode signals supplied to the flip-flops 13, 15, 17, 19 can be arbitrarily changed.

[0043]

According to the scan path circuit of the present invention, the peak of the power consumption of the entire circuit can be reduced, and a highly reliable operation that does not cause disconnection or the like can be realized with a small-sized and short wiring configuration. It can be carried out. Further, according to the scan path circuit of the present invention, the power consumption can be suppressed by providing the function clock generating circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a skew suppression flip-flop having a scan function.

FIG. 2 is a timing chart for explaining the operation of the flip-flop shown in FIG.

FIG. 3 is a circuit diagram of a scan path circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart for explaining an operation in a scan mode of the scan path circuit shown in FIG. 3;

FIG. 5 is a circuit diagram of a scan path circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a scan path circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a scan path circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart for explaining an operation in a scan mode of the scan path circuit shown in FIG. 7;

FIG. 9 is a circuit diagram of a scan path circuit using a conventional function clock (gated clock) generation circuit.

FIG. 10 is a timing chart for explaining the operation of the function clock generation circuit shown in FIG. 9;

FIG. 11 is a circuit diagram of another conventional scan path circuit.

[Explanation of symbols]

13, 15, 17, 19: flip-flop with anti-skew function, 14: function clock generating circuit, 62, 6
3, 64, 65, 110, 111, 112, 113, ...
Wiring, 66: SCK terminal, 70: combination circuit on the system side, 102, 103, 104: flip-flop

Claims (11)

[Claims] A plurality of flip-flops connected in series for latching data at an input terminal in response to a clock signal in a scan mode and outputting the latched data from an output terminal in response to a scan mode signal; And a scan mode signal supply unit that supplies a scan mode signal at a mutually different timing to each of the plurality of flip-flops in a scan mode. 2. The scan mode signal supply means receives a reference scan mode signal, and generates scan mode signals having different timings to be supplied to the plurality of flip-flops from the reference scan mode signal. 3. The scan path circuit according to 1. 3. The scan mode signal supply means according to claim 1, wherein a wiring delay time until the reference scan mode signal is transmitted to a scan mode signal input terminal of the plurality of flip-flops is set between the plurality of flip-flops. 2. The scan path circuit according to claim 1, wherein wirings are provided differently. 4. The method according to claim 1, wherein the scan mode signal supply means includes a signal transmission delay time in each wiring path between the input terminal of the reference scan mode signal and the input terminal of the scan mode signal of the plurality of flip-flops. 2. The scan path circuit according to claim 1, further comprising a different delay circuit. 5. The scan path circuit according to claim 4, wherein said delay circuit is a buffer circuit. 6. The scan mode signal supply means according to claim 1, wherein the signal transmission delay time is the same for each of the wiring paths of the reference scan mode signal input terminal and the scan mode signal input terminals of the plurality of flip-flops. 2. The scan path circuit according to claim 1, wherein a different number of circuits are provided. 7. The scan path circuit according to claim 6, wherein said delay circuit is a buffer circuit. 8. The scan mode signal supply means is reset in response to switching of the reference scan mode signal to a predetermined level, and operates at an input terminal in response to a pulse signal including a plurality of pulses after the reset. A plurality of scan mode signal generation flip-flops connected in series for outputting a level from an output terminal, wherein a scan mode signal is output from the output terminal of each scan mode signal generation flip-flop to the corresponding flip-flop. Item 2. The scan path circuit according to item 1. 9. The scan path circuit according to claim 1, wherein said flip-flop is a master-slave type flip-flop having a skew countermeasure function. 10. A function clock generating circuit for supplying a clock signal to the flip-flop in a scan mode and determining whether to supply a clock signal based on a clock enable signal in a general mode. 2. The scan path circuit according to claim 1, further comprising: 11. The scan path circuit according to claim 1, wherein said reference scan mode signal is held at a predetermined level in a general mode.